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1 ;; Scheduling description for IBM PowerPC 476 processor.
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2 ;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
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3 ;; Contributed by Peter Bergner (bergner@vnet.ibm.com).
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify
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8 ;; it under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful,
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13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 ;; GNU General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; PPC476 Embedded PowerPC controller
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22 ;; 3 issue (476) / 4 issue (476fp)
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23 ;;
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24 ;; i_pipe - complex integer / compare
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25 ;; lj_pipe - load-store / simple integer arithmetic
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26 ;; b_pipe - branch pipe
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27 ;; f_pipe - floating point arithmetic
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28
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29 (define_automaton "ppc476_core,ppc476_apu")
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30
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31 (define_cpu_unit "ppc476_i_pipe,ppc476_lj_pipe,ppc476_b_pipe" "ppc476_core")
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32 (define_cpu_unit "ppc476_issue_fp,ppc476_f_pipe" "ppc476_apu")
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33 (define_cpu_unit "ppc476_issue_0,ppc476_issue_1,ppc476_issue_2" "ppc476_core")
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34
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35 (define_reservation "ppc476_issue" "ppc476_issue_0|ppc476_issue_1|ppc476_issue_2")
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36 (define_reservation "ppc476_issue2" "ppc476_issue_0+ppc476_issue_1\
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37 |ppc476_issue_0+ppc476_issue_2\
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38 |ppc476_issue_1+ppc476_issue_2")
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39 (define_reservation "ppc476_issue3" "ppc476_issue_0+ppc476_issue_1+ppc476_issue_2")
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40
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41 (define_insn_reservation "ppc476-load" 4
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42 (and (eq_attr "type" "load,load_l,store_c,sync")
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43 (eq_attr "cpu" "ppc476"))
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44 "ppc476_issue,\
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45 ppc476_lj_pipe")
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46
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47 (define_insn_reservation "ppc476-store" 4
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48 (and (eq_attr "type" "store")
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49 (eq_attr "cpu" "ppc476"))
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50 "ppc476_issue,\
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51 ppc476_lj_pipe")
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52
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53 (define_insn_reservation "ppc476-fpload" 4
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54 (and (eq_attr "type" "fpload")
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55 (eq_attr "cpu" "ppc476"))
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56 "ppc476_issue,\
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57 ppc476_lj_pipe")
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58
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59 (define_insn_reservation "ppc476-fpstore" 4
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60 (and (eq_attr "type" "fpstore")
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61 (eq_attr "cpu" "ppc476"))
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62 "ppc476_issue,\
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63 ppc476_lj_pipe")
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64
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65 (define_insn_reservation "ppc476-simple-integer" 1
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66 (and (ior (eq_attr "type" "integer,insert")
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67 (and (eq_attr "type" "add,logical,shift,exts")
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68 (eq_attr "dot" "no")))
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69 (eq_attr "cpu" "ppc476"))
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70 "ppc476_issue,\
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71 ppc476_i_pipe|ppc476_lj_pipe")
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72
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73 (define_insn_reservation "ppc476-complex-integer" 1
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74 (and (eq_attr "type" "cmp,cr_logical,delayed_cr,cntlz,isel,isync,sync,trap,popcnt")
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75 (eq_attr "cpu" "ppc476"))
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76 "ppc476_issue,\
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77 ppc476_i_pipe")
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78
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79 (define_insn_reservation "ppc476-compare" 4
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80 (and (ior (eq_attr "type" "mfcr,mfcrf,mtcr,mfjmpr,mtjmpr")
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81 (and (eq_attr "type" "add,logical,shift,exts")
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82 (eq_attr "dot" "yes")))
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83 (eq_attr "cpu" "ppc476"))
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84 "ppc476_issue,\
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85 ppc476_i_pipe")
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86
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87 (define_insn_reservation "ppc476-imul" 4
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88 (and (eq_attr "type" "mul,halfmul")
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89 (eq_attr "cpu" "ppc476"))
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90 "ppc476_issue,\
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91 ppc476_i_pipe")
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92
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93 (define_insn_reservation "ppc476-idiv" 11
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94 (and (eq_attr "type" "div")
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95 (eq_attr "cpu" "ppc476"))
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96 "ppc476_issue,\
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97 ppc476_i_pipe*11")
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98
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99 (define_insn_reservation "ppc476-branch" 1
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100 (and (eq_attr "type" "branch,jmpreg")
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101 (eq_attr "cpu" "ppc476"))
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102 "ppc476_issue,\
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103 ppc476_b_pipe")
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104
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105 (define_insn_reservation "ppc476-two" 2
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106 (and (eq_attr "type" "two")
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107 (eq_attr "cpu" "ppc476"))
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108 "ppc476_issue2,\
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109 ppc476_i_pipe|ppc476_lj_pipe,\
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110 ppc476_i_pipe|ppc476_lj_pipe")
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111
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112 (define_insn_reservation "ppc476-three" 3
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113 (and (eq_attr "type" "three")
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114 (eq_attr "cpu" "ppc476"))
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115 "ppc476_issue3,\
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116 ppc476_i_pipe|ppc476_lj_pipe,\
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117 ppc476_i_pipe|ppc476_lj_pipe,\
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118 ppc476_i_pipe|ppc476_lj_pipe")
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119
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120 (define_insn_reservation "ppc476-fpcompare" 6
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121 (and (eq_attr "type" "fpcompare")
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122 (eq_attr "cpu" "ppc476"))
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123 "ppc476_issue+ppc476_issue_fp,\
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124 ppc476_f_pipe+ppc476_i_pipe")
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125
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126 (define_insn_reservation "ppc476-fp" 6
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127 (and (eq_attr "type" "fp,fpsimple,dmul")
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128 (eq_attr "cpu" "ppc476"))
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129 "ppc476_issue_fp,\
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130 ppc476_f_pipe")
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131
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132 (define_insn_reservation "ppc476-sdiv" 19
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133 (and (eq_attr "type" "sdiv")
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134 (eq_attr "cpu" "ppc476"))
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135 "ppc476_issue_fp,
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136 ppc476_f_pipe*19")
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137
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138 (define_insn_reservation "ppc476-ddiv" 33
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139 (and (eq_attr "type" "ddiv")
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140 (eq_attr "cpu" "ppc476"))
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141 "ppc476_issue_fp,\
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142 ppc476_f_pipe*33")
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143
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