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annotate gcc/config/powerpcspe/e500mc64.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children
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1 ;; Pipeline description for Freescale PowerPC e500mc64 core.
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84e7813d76e9 gcc-8.2
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2 ;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
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3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com)
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20 ;;
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21 ;; e500mc64 64-bit SU(2), LSU, FPU, BPU
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22 ;; Max issue 3 insns/clock cycle (includes 1 branch)
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23
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24 (define_automaton "e500mc64_most,e500mc64_long,e500mc64_retire")
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25 (define_cpu_unit "e500mc64_decode_0,e500mc64_decode_1" "e500mc64_most")
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26 (define_cpu_unit "e500mc64_issue_0,e500mc64_issue_1" "e500mc64_most")
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27 (define_cpu_unit "e500mc64_retire_0,e500mc64_retire_1" "e500mc64_retire")
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28
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29 ;; SU.
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30 (define_cpu_unit "e500mc64_su0_stage0,e500mc64_su1_stage0" "e500mc64_most")
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31
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32 ;; MU.
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33 (define_cpu_unit "e500mc64_mu_stage0,e500mc64_mu_stage1" "e500mc64_most")
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34 (define_cpu_unit "e500mc64_mu_stage2,e500mc64_mu_stage3" "e500mc64_most")
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35
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36 ;; Non-pipelined division.
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37 (define_cpu_unit "e500mc64_mu_div" "e500mc64_long")
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38
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39 ;; LSU.
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40 (define_cpu_unit "e500mc64_lsu" "e500mc64_most")
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41
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42 ;; FPU.
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43 (define_cpu_unit "e500mc64_fpu" "e500mc64_most")
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44
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45 ;; Branch unit.
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46 (define_cpu_unit "e500mc64_bu" "e500mc64_most")
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47
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48 ;; The following units are used to make the automata deterministic.
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49 (define_cpu_unit "present_e500mc64_decode_0" "e500mc64_most")
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50 (define_cpu_unit "present_e500mc64_issue_0" "e500mc64_most")
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51 (define_cpu_unit "present_e500mc64_retire_0" "e500mc64_retire")
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52 (define_cpu_unit "present_e500mc64_su0_stage0" "e500mc64_most")
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53
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54 ;; The following sets to make automata deterministic when option ndfa is used.
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55 (presence_set "present_e500mc64_decode_0" "e500mc64_decode_0")
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56 (presence_set "present_e500mc64_issue_0" "e500mc64_issue_0")
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57 (presence_set "present_e500mc64_retire_0" "e500mc64_retire_0")
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58 (presence_set "present_e500mc64_su0_stage0" "e500mc64_su0_stage0")
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59
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60 ;; Some useful abbreviations.
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61 (define_reservation "e500mc64_decode"
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62 "e500mc64_decode_0|e500mc64_decode_1+present_e500mc64_decode_0")
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63 (define_reservation "e500mc64_issue"
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64 "e500mc64_issue_0|e500mc64_issue_1+present_e500mc64_issue_0")
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65 (define_reservation "e500mc64_retire"
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66 "e500mc64_retire_0|e500mc64_retire_1+present_e500mc64_retire_0")
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67 (define_reservation "e500mc64_su_stage0"
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68 "e500mc64_su0_stage0|e500mc64_su1_stage0+present_e500mc64_su0_stage0")
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69
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70 ;; Simple SU insns.
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71 (define_insn_reservation "e500mc64_su" 1
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72 (and (ior (eq_attr "type" "integer,insert,cntlz")
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73 (and (eq_attr "type" "add,logical,exts")
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74 (eq_attr "dot" "no"))
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75 (and (eq_attr "type" "shift")
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76 (eq_attr "dot" "no")
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77 (eq_attr "var_shift" "no")))
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78 (eq_attr "cpu" "ppce500mc64"))
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79 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
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80
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81 (define_insn_reservation "e500mc64_su2" 2
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82 (and (ior (eq_attr "type" "cmp,trap")
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83 (and (eq_attr "type" "add,logical,exts")
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84 (eq_attr "dot" "yes"))
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85 (and (eq_attr "type" "shift")
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86 (eq_attr "dot" "yes")
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87 (eq_attr "var_shift" "no")))
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88 (eq_attr "cpu" "ppce500mc64"))
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89 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
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90
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91 (define_insn_reservation "e500mc64_delayed" 2
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92 (and (eq_attr "type" "shift")
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93 (eq_attr "var_shift" "yes")
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94 (eq_attr "cpu" "ppce500mc64"))
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95 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
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96
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97 (define_insn_reservation "e500mc64_two" 2
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98 (and (eq_attr "type" "two")
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99 (eq_attr "cpu" "ppce500mc64"))
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100 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\
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101 e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
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102
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103 (define_insn_reservation "e500mc64_three" 3
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104 (and (eq_attr "type" "three")
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105 (eq_attr "cpu" "ppce500mc64"))
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106 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\
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107 e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\
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108 e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
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109
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110 ;; Multiply.
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111 (define_insn_reservation "e500mc64_multiply" 4
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112 (and (eq_attr "type" "mul")
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113 (eq_attr "cpu" "ppce500mc64"))
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114 "e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0,e500mc64_mu_stage1,\
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115 e500mc64_mu_stage2,e500mc64_mu_stage3+e500mc64_retire")
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116
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117 ;; Divide. We use the average latency time here.
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118 (define_insn_reservation "e500mc64_divide" 14
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119 (and (eq_attr "type" "div")
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120 (eq_attr "cpu" "ppce500mc64"))
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121 "e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0+e500mc64_mu_div,\
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122 e500mc64_mu_div*13")
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123
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124 ;; Branch.
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125 (define_insn_reservation "e500mc64_branch" 1
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126 (and (eq_attr "type" "jmpreg,branch,isync")
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127 (eq_attr "cpu" "ppce500mc64"))
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128 "e500mc64_decode,e500mc64_bu,e500mc64_retire")
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129
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130 ;; CR logical.
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131 (define_insn_reservation "e500mc64_cr_logical" 1
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132 (and (eq_attr "type" "cr_logical,delayed_cr")
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133 (eq_attr "cpu" "ppce500mc64"))
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134 "e500mc64_decode,e500mc64_bu,e500mc64_retire")
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135
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136 ;; Mfcr.
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137 (define_insn_reservation "e500mc64_mfcr" 4
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138 (and (eq_attr "type" "mfcr")
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139 (eq_attr "cpu" "ppce500mc64"))
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140 "e500mc64_decode,e500mc64_issue+e500mc64_su1_stage0,e500mc64_su1_stage0*3+e500mc64_retire")
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141
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142 ;; Mtcrf.
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143 (define_insn_reservation "e500mc64_mtcrf" 1
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144 (and (eq_attr "type" "mtcr")
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145 (eq_attr "cpu" "ppce500mc64"))
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146 "e500mc64_decode,e500mc64_issue+e500mc64_su1_stage0+e500mc64_retire")
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147
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148 ;; Mtjmpr.
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149 (define_insn_reservation "e500mc64_mtjmpr" 1
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150 (and (eq_attr "type" "mtjmpr,mfjmpr")
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151 (eq_attr "cpu" "ppce500mc64"))
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152 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
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153
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154 ;; Brinc.
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155 (define_insn_reservation "e500mc64_brinc" 1
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156 (and (eq_attr "type" "brinc")
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157 (eq_attr "cpu" "ppce500mc64"))
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158 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
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159
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160 ;; Loads.
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161 (define_insn_reservation "e500mc64_load" 3
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162 (and (eq_attr "type" "load,load_l,sync")
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163 (eq_attr "cpu" "ppce500mc64"))
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164 "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
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165
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166 (define_insn_reservation "e500mc64_fpload" 4
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167 (and (eq_attr "type" "fpload")
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168 (eq_attr "cpu" "ppce500mc64"))
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169 "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing*2,e500mc64_retire")
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170
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171 ;; Stores.
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172 (define_insn_reservation "e500mc64_store" 3
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173 (and (eq_attr "type" "store,store_c")
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174 (eq_attr "cpu" "ppce500mc64"))
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175 "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
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176
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177 (define_insn_reservation "e500mc64_fpstore" 3
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178 (and (eq_attr "type" "fpstore")
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179 (eq_attr "cpu" "ppce500mc64"))
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180 "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
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181
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182 ;; The following ignores the retire unit to avoid a large automata.
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183
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184 ;; FP.
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185 (define_insn_reservation "e500mc64_float" 7
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186 (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
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187 (eq_attr "cpu" "ppce500mc64"))
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188 "e500mc64_decode,e500mc64_issue+e500mc64_fpu")
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189 ; "e500mc64_decode,e500mc64_issue+e500mc64_fpu,nothing*5,e500mc64_retire")
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190
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191 ;; FP divides are not pipelined.
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192 (define_insn_reservation "e500mc64_sdiv" 20
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193 (and (eq_attr "type" "sdiv")
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194 (eq_attr "cpu" "ppce500mc64"))
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195 "e500mc64_decode,e500mc64_issue+e500mc64_fpu,e500mc64_fpu*19")
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196
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197 (define_insn_reservation "e500mc64_ddiv" 35
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198 (and (eq_attr "type" "ddiv")
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199 (eq_attr "cpu" "ppce500mc64"))
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200 "e500mc64_decode,e500mc64_issue+e500mc64_fpu,e500mc64_fpu*34")