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annotate gcc/config/powerpcspe/e5500.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children
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1 ;; Pipeline description for Freescale PowerPC e5500 core.
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84e7813d76e9 gcc-8.2
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2 ;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
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3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com)
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20 ;;
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21 ;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU
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22 ;; Max issue 3 insns/clock cycle (includes 1 branch)
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23
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24 (define_automaton "e5500_most,e5500_long")
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25 (define_cpu_unit "e5500_decode_0,e5500_decode_1" "e5500_most")
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26
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27 ;; SFX.
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28 (define_cpu_unit "e5500_sfx_0,e5500_sfx_1" "e5500_most")
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29
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30 ;; CFX.
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31 (define_cpu_unit "e5500_cfx_stage0,e5500_cfx_stage1" "e5500_most")
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32
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33 ;; Non-pipelined division.
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34 (define_cpu_unit "e5500_cfx_div" "e5500_long")
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35
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36 ;; LSU.
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37 (define_cpu_unit "e5500_lsu" "e5500_most")
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38
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39 ;; FPU.
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40 (define_cpu_unit "e5500_fpu" "e5500_long")
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41
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42 ;; BU.
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43 (define_cpu_unit "e5500_bu" "e5500_most")
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44
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45 ;; The following units are used to make the automata deterministic.
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46 (define_cpu_unit "present_e5500_decode_0" "e5500_most")
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47 (define_cpu_unit "present_e5500_sfx_0" "e5500_most")
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48 (presence_set "present_e5500_decode_0" "e5500_decode_0")
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49 (presence_set "present_e5500_sfx_0" "e5500_sfx_0")
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50
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51 ;; Some useful abbreviations.
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52 (define_reservation "e5500_decode"
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53 "e5500_decode_0|e5500_decode_1+present_e5500_decode_0")
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54 (define_reservation "e5500_sfx"
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55 "e5500_sfx_0|e5500_sfx_1+present_e5500_sfx_0")
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56
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57 ;; SFX.
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58 (define_insn_reservation "e5500_sfx" 1
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59 (and (ior (eq_attr "type" "integer,insert,cntlz")
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60 (and (eq_attr "type" "add,logical,exts")
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61 (eq_attr "dot" "no"))
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62 (and (eq_attr "type" "shift")
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63 (eq_attr "var_shift" "no")))
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64 (eq_attr "cpu" "ppce5500"))
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65 "e5500_decode,e5500_sfx")
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66
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67 (define_insn_reservation "e5500_sfx2" 2
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68 (and (ior (eq_attr "type" "cmp,trap")
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69 (and (eq_attr "type" "add,logical,exts")
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70 (eq_attr "dot" "yes"))
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71 (and (eq_attr "type" "shift")
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72 (eq_attr "dot" "yes")
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73 (eq_attr "var_shift" "no")))
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74 (eq_attr "cpu" "ppce5500"))
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75 "e5500_decode,e5500_sfx")
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76
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77 (define_insn_reservation "e5500_delayed" 2
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78 (and (eq_attr "type" "shift")
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79 (eq_attr "var_shift" "yes")
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80 (eq_attr "cpu" "ppce5500"))
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81 "e5500_decode,e5500_sfx*2")
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82
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83 (define_insn_reservation "e5500_two" 2
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84 (and (eq_attr "type" "two")
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85 (eq_attr "cpu" "ppce5500"))
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86 "e5500_decode,e5500_decode+e5500_sfx,e5500_sfx")
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87
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88 (define_insn_reservation "e5500_three" 3
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89 (and (eq_attr "type" "three")
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90 (eq_attr "cpu" "ppce5500"))
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91 "e5500_decode,(e5500_decode+e5500_sfx)*2,e5500_sfx")
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92
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93 ;; SFX - Mfcr.
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94 (define_insn_reservation "e5500_mfcr" 4
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95 (and (eq_attr "type" "mfcr")
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96 (eq_attr "cpu" "ppce5500"))
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97 "e5500_decode,e5500_sfx_0*4")
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98
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99 ;; SFX - Mtcrf.
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100 (define_insn_reservation "e5500_mtcrf" 1
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101 (and (eq_attr "type" "mtcr")
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102 (eq_attr "cpu" "ppce5500"))
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103 "e5500_decode,e5500_sfx_0")
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104
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105 ;; SFX - Mtjmpr.
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106 (define_insn_reservation "e5500_mtjmpr" 1
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107 (and (eq_attr "type" "mtjmpr,mfjmpr")
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108 (eq_attr "cpu" "ppce5500"))
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109 "e5500_decode,e5500_sfx")
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110
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111 ;; CFX - Multiply.
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112 (define_insn_reservation "e5500_multiply" 4
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113 (and (eq_attr "type" "mul")
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114 (eq_attr "dot" "no")
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115 (eq_attr "size" "32")
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116 (eq_attr "cpu" "ppce5500"))
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117 "e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1")
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118
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119 (define_insn_reservation "e5500_multiply_i" 5
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120 (and (eq_attr "type" "mul")
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121 (ior (eq_attr "dot" "yes")
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122 (eq_attr "size" "8,16"))
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123 (eq_attr "cpu" "ppce5500"))
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124 "e5500_decode,e5500_cfx_stage0,\
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125 e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1")
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126
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127 ;; CFX - Divide.
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128 (define_insn_reservation "e5500_divide" 16
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129 (and (eq_attr "type" "div")
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130 (eq_attr "size" "32")
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131 (eq_attr "cpu" "ppce5500"))
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132 "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
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133 e5500_cfx_div*15")
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134
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135 (define_insn_reservation "e5500_divide_d" 26
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136 (and (eq_attr "type" "div")
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137 (eq_attr "size" "64")
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138 (eq_attr "cpu" "ppce5500"))
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139 "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
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140 e5500_cfx_div*25")
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141
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142 ;; LSU - Loads.
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143 (define_insn_reservation "e5500_load" 3
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144 (and (eq_attr "type" "load,load_l,sync")
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145 (eq_attr "cpu" "ppce5500"))
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146 "e5500_decode,e5500_lsu")
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147
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148 (define_insn_reservation "e5500_fpload" 4
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149 (and (eq_attr "type" "fpload")
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150 (eq_attr "cpu" "ppce5500"))
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151 "e5500_decode,e5500_lsu")
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152
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153 ;; LSU - Stores.
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154 (define_insn_reservation "e5500_store" 3
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155 (and (eq_attr "type" "store,store_c")
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156 (eq_attr "cpu" "ppce5500"))
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157 "e5500_decode,e5500_lsu")
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158
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159 (define_insn_reservation "e5500_fpstore" 3
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160 (and (eq_attr "type" "fpstore")
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161 (eq_attr "cpu" "ppce5500"))
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162 "e5500_decode,e5500_lsu")
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163
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164 ;; FP.
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165 (define_insn_reservation "e5500_float" 7
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166 (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
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167 (eq_attr "cpu" "ppce5500"))
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168 "e5500_decode,e5500_fpu")
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169
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170 (define_insn_reservation "e5500_sdiv" 20
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171 (and (eq_attr "type" "sdiv")
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172 (eq_attr "cpu" "ppce5500"))
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173 "e5500_decode,e5500_fpu*20")
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174
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175 (define_insn_reservation "e5500_ddiv" 35
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176 (and (eq_attr "type" "ddiv")
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177 (eq_attr "cpu" "ppce5500"))
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178 "e5500_decode,e5500_fpu*35")
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179
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180 ;; BU.
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181 (define_insn_reservation "e5500_branch" 1
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182 (and (eq_attr "type" "jmpreg,branch,isync")
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183 (eq_attr "cpu" "ppce5500"))
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184 "e5500_decode,e5500_bu")
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185
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186 ;; BU - CR logical.
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187 (define_insn_reservation "e5500_cr_logical" 1
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188 (and (eq_attr "type" "cr_logical,delayed_cr")
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189 (eq_attr "cpu" "ppce5500"))
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190 "e5500_decode,e5500_bu")