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1 ;; Scheduling description for Motorola PowerPC processor cores.
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2 ;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published
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8 ;; by the Free Software Foundation; either version 3, or (at your
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9 ;; option) any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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14 ;; License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_automaton "mpc,mpcfp")
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21 (define_cpu_unit "iu_mpc,mciu_mpc" "mpc")
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22 (define_cpu_unit "fpu_mpc" "mpcfp")
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23 (define_cpu_unit "lsu_mpc,bpu_mpc" "mpc")
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24
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25 ;; MPCCORE 32-bit SCIU, MCIU, LSU, FPU, BPU
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26 ;; 505/801/821/823
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27
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28 (define_insn_reservation "mpccore-load" 2
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29 (and (eq_attr "type" "load,load_l,store_c,sync")
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30 (eq_attr "cpu" "mpccore"))
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31 "lsu_mpc")
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32
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33 (define_insn_reservation "mpccore-store" 2
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34 (and (eq_attr "type" "store,fpstore")
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35 (eq_attr "cpu" "mpccore"))
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36 "lsu_mpc")
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37
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38 (define_insn_reservation "mpccore-fpload" 2
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39 (and (eq_attr "type" "fpload")
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40 (eq_attr "cpu" "mpccore"))
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41 "lsu_mpc")
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42
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43 (define_insn_reservation "mpccore-integer" 1
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44 (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
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45 (and (eq_attr "type" "add,logical,shift,exts")
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46 (eq_attr "dot" "no")))
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47 (eq_attr "cpu" "mpccore"))
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48 "iu_mpc")
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49
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50 (define_insn_reservation "mpccore-two" 1
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51 (and (eq_attr "type" "two")
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52 (eq_attr "cpu" "mpccore"))
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53 "iu_mpc,iu_mpc")
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54
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55 (define_insn_reservation "mpccore-three" 1
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56 (and (eq_attr "type" "three")
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57 (eq_attr "cpu" "mpccore"))
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58 "iu_mpc,iu_mpc,iu_mpc")
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59
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60 (define_insn_reservation "mpccore-imul" 2
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61 (and (eq_attr "type" "mul")
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62 (eq_attr "cpu" "mpccore"))
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63 "mciu_mpc")
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64
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65 ; Divide latency varies greatly from 2-11, use 6 as average
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66 (define_insn_reservation "mpccore-idiv" 6
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67 (and (eq_attr "type" "div")
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68 (eq_attr "cpu" "mpccore"))
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69 "mciu_mpc*6")
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70
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71 (define_insn_reservation "mpccore-compare" 3
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72 (and (ior (eq_attr "type" "cmp")
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73 (and (eq_attr "type" "add,logical,shift,exts")
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74 (eq_attr "dot" "yes")))
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75 (eq_attr "cpu" "mpccore"))
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76 "iu_mpc,nothing,bpu_mpc")
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77
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78 (define_insn_reservation "mpccore-fpcompare" 2
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79 (and (eq_attr "type" "fpcompare")
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80 (eq_attr "cpu" "mpccore"))
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81 "fpu_mpc,bpu_mpc")
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82
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83 (define_insn_reservation "mpccore-fp" 4
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84 (and (eq_attr "type" "fp,fpsimple")
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85 (eq_attr "cpu" "mpccore"))
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86 "fpu_mpc*2")
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87
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88 (define_insn_reservation "mpccore-dmul" 5
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89 (and (eq_attr "type" "dmul")
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90 (eq_attr "cpu" "mpccore"))
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91 "fpu_mpc*5")
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92
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93 (define_insn_reservation "mpccore-sdiv" 10
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94 (and (eq_attr "type" "sdiv")
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95 (eq_attr "cpu" "mpccore"))
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96 "fpu_mpc*10")
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97
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98 (define_insn_reservation "mpccore-ddiv" 17
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99 (and (eq_attr "type" "ddiv")
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100 (eq_attr "cpu" "mpccore"))
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101 "fpu_mpc*17")
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102
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103 (define_insn_reservation "mpccore-mtjmpr" 4
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104 (and (eq_attr "type" "mtjmpr,mfjmpr")
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105 (eq_attr "cpu" "mpccore"))
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106 "bpu_mpc")
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107
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108 (define_insn_reservation "mpccore-jmpreg" 1
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109 (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr,mfcr,mtcr,isync")
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110 (eq_attr "cpu" "mpccore"))
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111 "bpu_mpc")
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