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1 ;; Scheduling description for IBM POWER6 processor.
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131
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2 ;; Copyright (C) 2006-2018 Free Software Foundation, Inc.
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111
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3 ;; Contributed by Peter Steinmetz (steinmtz@us.ibm.com)
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; Sources:
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22
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23 ;; The POWER6 has 2 iu, 2 fpu, 2 lsu, and 1 bu/cru unit per engine
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24 ;; (2 engines per chip). The chip can issue up to 5 internal ops
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25 ;; per cycle.
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26
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27 (define_automaton "power6iu,power6lsu,power6fpu,power6bu")
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28
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29 (define_cpu_unit "iu1_power6,iu2_power6" "power6iu")
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30 (define_cpu_unit "lsu1_power6,lsu2_power6" "power6lsu")
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31 (define_cpu_unit "bpu_power6" "power6bu")
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32 (define_cpu_unit "fpu1_power6,fpu2_power6" "power6fpu")
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33
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34 (define_reservation "LS2_power6"
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35 "lsu1_power6+lsu2_power6")
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36
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37 (define_reservation "FPU_power6"
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38 "fpu1_power6|fpu2_power6")
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39
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40 (define_reservation "BRU_power6"
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41 "bpu_power6")
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42
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43 (define_reservation "LSU_power6"
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44 "lsu1_power6|lsu2_power6")
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45
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46 (define_reservation "LSF_power6"
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47 "(lsu1_power6+fpu1_power6)\
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48 |(lsu1_power6+fpu2_power6)\
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49 |(lsu2_power6+fpu1_power6)\
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50 |(lsu2_power6+fpu2_power6)")
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51
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52 (define_reservation "LX2_power6"
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53 "(iu1_power6+iu2_power6+lsu1_power6)\
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54 |(iu1_power6+iu2_power6+lsu2_power6)")
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55
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56 (define_reservation "FX2_power6"
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57 "iu1_power6+iu2_power6")
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58
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59 (define_reservation "X2F_power6"
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60 "(iu1_power6+iu2_power6+fpu1_power6)\
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61 |(iu1_power6+iu2_power6+fpu2_power6)")
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62
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63 (define_reservation "BX2_power6"
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64 "iu1_power6+iu2_power6+bpu_power6")
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65
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66 (define_reservation "LSX_power6"
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67 "(iu1_power6+lsu1_power6)\
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68 |(iu1_power6+lsu2_power6)\
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69 |(iu2_power6+lsu1_power6)\
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70 |(iu2_power6+lsu2_power6)")
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71
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72 (define_reservation "FXU_power6"
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73 "iu1_power6|iu2_power6")
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74
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75 (define_reservation "XLF_power6"
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76 "(iu1_power6+lsu1_power6+fpu1_power6)\
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77 |(iu1_power6+lsu1_power6+fpu2_power6)\
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78 |(iu1_power6+lsu2_power6+fpu1_power6)\
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79 |(iu1_power6+lsu2_power6+fpu2_power6)\
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80 |(iu2_power6+lsu1_power6+fpu1_power6)\
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81 |(iu2_power6+lsu1_power6+fpu2_power6)\
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82 |(iu2_power6+lsu2_power6+fpu1_power6)\
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83 |(iu2_power6+lsu2_power6+fpu2_power6)")
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84
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85 (define_reservation "BRX_power6"
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86 "(bpu_power6+iu1_power6)\
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87 |(bpu_power6+iu2_power6)")
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88
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89 ; Load/store
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90
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91 ; The default for a value written by a fixed point load
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92 ; that is read/written by a subsequent fixed point op.
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93 (define_insn_reservation "power6-load" 2 ; fx
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94 (and (eq_attr "type" "load")
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95 (eq_attr "sign_extend" "no")
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96 (eq_attr "update" "no")
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97 (eq_attr "cpu" "power6"))
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98 "LSU_power6")
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99
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100 ; define the bypass for the case where the value written
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101 ; by a fixed point load is used as the source value on
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102 ; a store.
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103 (define_bypass 1 "power6-load,\
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104 power6-load-update,\
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105 power6-load-update-indexed"
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106 "power6-store,\
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107 power6-store-update,\
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108 power6-store-update-indexed,\
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109 power6-fpstore,\
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110 power6-fpstore-update"
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111 "rs6000_store_data_bypass_p")
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112
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113 (define_insn_reservation "power6-load-ext" 4 ; fx
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114 (and (eq_attr "type" "load")
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115 (eq_attr "sign_extend" "yes")
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116 (eq_attr "update" "no")
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117 (eq_attr "cpu" "power6"))
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118 "LSU_power6")
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119
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120 ; define the bypass for the case where the value written
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121 ; by a fixed point load ext is used as the source value on
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122 ; a store.
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123 (define_bypass 1 "power6-load-ext,\
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124 power6-load-ext-update,\
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125 power6-load-ext-update-indexed"
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126 "power6-store,\
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127 power6-store-update,\
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128 power6-store-update-indexed,\
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129 power6-fpstore,\
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130 power6-fpstore-update"
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131 "rs6000_store_data_bypass_p")
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132
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133 (define_insn_reservation "power6-load-update" 2 ; fx
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134 (and (eq_attr "type" "load")
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135 (eq_attr "sign_extend" "no")
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136 (eq_attr "update" "yes")
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137 (eq_attr "indexed" "no")
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138 (eq_attr "cpu" "power6"))
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139 "LSX_power6")
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140
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141 (define_insn_reservation "power6-load-update-indexed" 2 ; fx
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142 (and (eq_attr "type" "load")
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143 (eq_attr "sign_extend" "no")
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144 (eq_attr "update" "yes")
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145 (eq_attr "indexed" "yes")
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146 (eq_attr "cpu" "power6"))
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147 "LSX_power6")
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148
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149 (define_insn_reservation "power6-load-ext-update" 4 ; fx
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150 (and (eq_attr "type" "load")
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151 (eq_attr "sign_extend" "yes")
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152 (eq_attr "update" "yes")
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153 (eq_attr "indexed" "no")
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154 (eq_attr "cpu" "power6"))
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155 "LSX_power6")
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156
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157 (define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx
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158 (and (eq_attr "type" "load")
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159 (eq_attr "sign_extend" "yes")
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160 (eq_attr "update" "yes")
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161 (eq_attr "indexed" "yes")
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162 (eq_attr "cpu" "power6"))
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163 "LSX_power6")
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164
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165 (define_insn_reservation "power6-fpload" 1
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166 (and (eq_attr "type" "fpload")
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167 (eq_attr "update" "no")
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168 (eq_attr "cpu" "power6"))
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169 "LSU_power6")
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170
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171 (define_insn_reservation "power6-fpload-update" 1
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172 (and (eq_attr "type" "fpload")
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173 (eq_attr "update" "yes")
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174 (eq_attr "cpu" "power6"))
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175 "LSX_power6")
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176
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177 (define_insn_reservation "power6-store" 14
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178 (and (eq_attr "type" "store")
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179 (eq_attr "update" "no")
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180 (eq_attr "cpu" "power6"))
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181 "LSU_power6")
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182
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183 (define_insn_reservation "power6-store-update" 14
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184 (and (eq_attr "type" "store")
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185 (eq_attr "update" "yes")
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186 (eq_attr "indexed" "no")
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187 (eq_attr "cpu" "power6"))
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188 "LSX_power6")
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189
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190 (define_insn_reservation "power6-store-update-indexed" 14
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191 (and (eq_attr "type" "store")
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192 (eq_attr "update" "yes")
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193 (eq_attr "indexed" "yes")
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194 (eq_attr "cpu" "power6"))
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195 "LX2_power6")
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196
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197 (define_insn_reservation "power6-fpstore" 14
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198 (and (eq_attr "type" "fpstore")
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199 (eq_attr "update" "no")
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200 (eq_attr "cpu" "power6"))
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201 "LSF_power6")
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202
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203 (define_insn_reservation "power6-fpstore-update" 14
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204 (and (eq_attr "type" "fpstore")
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205 (eq_attr "update" "yes")
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206 (eq_attr "cpu" "power6"))
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207 "XLF_power6")
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208
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209 (define_insn_reservation "power6-larx" 3
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210 (and (eq_attr "type" "load_l")
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211 (eq_attr "cpu" "power6"))
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212 "LS2_power6")
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213
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214 (define_insn_reservation "power6-stcx" 10 ; best case
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215 (and (eq_attr "type" "store_c")
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216 (eq_attr "cpu" "power6"))
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217 "LSX_power6")
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218
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219 (define_insn_reservation "power6-sync" 11 ; N/A
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220 (and (eq_attr "type" "sync")
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221 (eq_attr "cpu" "power6"))
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222 "LSU_power6")
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223
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224 (define_insn_reservation "power6-integer" 1
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225 (and (ior (eq_attr "type" "integer")
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226 (and (eq_attr "type" "add,logical")
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227 (eq_attr "dot" "no")))
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228 (eq_attr "cpu" "power6"))
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229 "FXU_power6")
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230
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231 (define_insn_reservation "power6-isel" 1
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232 (and (eq_attr "type" "isel")
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233 (eq_attr "cpu" "power6"))
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234 "FXU_power6")
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235
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236 (define_insn_reservation "power6-exts" 1
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237 (and (eq_attr "type" "exts")
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238 (eq_attr "dot" "no")
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239 (eq_attr "cpu" "power6"))
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240 "FXU_power6")
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241
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242 (define_insn_reservation "power6-shift" 1
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243 (and (eq_attr "type" "shift")
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244 (eq_attr "var_shift" "no")
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245 (eq_attr "dot" "no")
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246 (eq_attr "cpu" "power6"))
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247 "FXU_power6")
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248
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249 (define_insn_reservation "power6-popcnt" 1
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250 (and (eq_attr "type" "popcnt")
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251 (eq_attr "cpu" "power6"))
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252 "FXU_power6")
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253
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254 (define_insn_reservation "power6-insert" 1
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255 (and (eq_attr "type" "insert")
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256 (eq_attr "size" "32")
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257 (eq_attr "cpu" "power6"))
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258 "FX2_power6")
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259
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260 (define_insn_reservation "power6-insert-dword" 1
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261 (and (eq_attr "type" "insert")
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262 (eq_attr "size" "64")
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263 (eq_attr "cpu" "power6"))
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264 "FX2_power6")
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265
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266 ; define the bypass for the case where the value written
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267 ; by a fixed point op is used as the source value on a
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268 ; store.
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269 (define_bypass 1 "power6-integer,\
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270 power6-exts,\
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271 power6-shift,\
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272 power6-insert,\
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273 power6-insert-dword"
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274 "power6-store,\
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275 power6-store-update,\
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276 power6-store-update-indexed,\
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277 power6-fpstore,\
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278 power6-fpstore-update"
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279 "rs6000_store_data_bypass_p")
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280
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281 (define_insn_reservation "power6-cntlz" 2
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282 (and (eq_attr "type" "cntlz")
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283 (eq_attr "cpu" "power6"))
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284 "FXU_power6")
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285
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286 (define_bypass 1 "power6-cntlz"
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287 "power6-store,\
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288 power6-store-update,\
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289 power6-store-update-indexed,\
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290 power6-fpstore,\
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291 power6-fpstore-update"
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292 "rs6000_store_data_bypass_p")
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293
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294 (define_insn_reservation "power6-var-rotate" 4
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295 (and (eq_attr "type" "shift")
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296 (eq_attr "var_shift" "yes")
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297 (eq_attr "dot" "no")
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298 (eq_attr "cpu" "power6"))
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299 "FXU_power6")
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300
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301 (define_insn_reservation "power6-trap" 1 ; N/A
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302 (and (eq_attr "type" "trap")
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303 (eq_attr "cpu" "power6"))
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304 "BRX_power6")
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305
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306 (define_insn_reservation "power6-two" 1
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307 (and (eq_attr "type" "two")
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308 (eq_attr "cpu" "power6"))
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309 "(iu1_power6,iu1_power6)\
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310 |(iu1_power6+iu2_power6,nothing)\
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311 |(iu1_power6,iu2_power6)\
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312 |(iu2_power6,iu1_power6)\
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313 |(iu2_power6,iu2_power6)")
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314
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315 (define_insn_reservation "power6-three" 1
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316 (and (eq_attr "type" "three")
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317 (eq_attr "cpu" "power6"))
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318 "(iu1_power6,iu1_power6,iu1_power6)\
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319 |(iu1_power6,iu1_power6,iu2_power6)\
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320 |(iu1_power6,iu2_power6,iu1_power6)\
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321 |(iu1_power6,iu2_power6,iu2_power6)\
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322 |(iu2_power6,iu1_power6,iu1_power6)\
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323 |(iu2_power6,iu1_power6,iu2_power6)\
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324 |(iu2_power6,iu2_power6,iu1_power6)\
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325 |(iu2_power6,iu2_power6,iu2_power6)\
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326 |(iu1_power6+iu2_power6,iu1_power6)\
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327 |(iu1_power6+iu2_power6,iu2_power6)\
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328 |(iu1_power6,iu1_power6+iu2_power6)\
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329 |(iu2_power6,iu1_power6+iu2_power6)")
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330
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331 (define_insn_reservation "power6-cmp" 1
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332 (and (eq_attr "type" "cmp")
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333 (eq_attr "cpu" "power6"))
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334 "FXU_power6")
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335
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336 (define_insn_reservation "power6-compare" 1
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337 (and (eq_attr "type" "exts")
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338 (eq_attr "dot" "yes")
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339 (eq_attr "cpu" "power6"))
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340 "FXU_power6")
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341
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342 (define_insn_reservation "power6-fast-compare" 1
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343 (and (eq_attr "type" "add,logical")
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344 (eq_attr "dot" "yes")
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345 (eq_attr "cpu" "power6"))
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346 "FXU_power6")
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347
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348 ; define the bypass for the case where the value written
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349 ; by a fixed point rec form op is used as the source value
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350 ; on a store.
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351 (define_bypass 1 "power6-compare,\
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352 power6-fast-compare"
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353 "power6-store,\
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354 power6-store-update,\
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355 power6-store-update-indexed,\
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356 power6-fpstore,\
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357 power6-fpstore-update"
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358 "rs6000_store_data_bypass_p")
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359
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360 (define_insn_reservation "power6-delayed-compare" 2 ; N/A
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361 (and (eq_attr "type" "shift")
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362 (eq_attr "var_shift" "no")
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363 (eq_attr "dot" "yes")
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364 (eq_attr "cpu" "power6"))
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365 "FXU_power6")
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366
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367 (define_insn_reservation "power6-var-delayed-compare" 4
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368 (and (eq_attr "type" "shift")
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369 (eq_attr "var_shift" "yes")
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370 (eq_attr "dot" "yes")
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371 (eq_attr "cpu" "power6"))
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372 "FXU_power6")
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373
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374 (define_insn_reservation "power6-lmul-cmp" 16
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375 (and (eq_attr "type" "mul")
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376 (eq_attr "dot" "yes")
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377 (eq_attr "size" "64")
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378 (eq_attr "cpu" "power6"))
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379 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
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380 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
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381
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382 (define_insn_reservation "power6-imul-cmp" 16
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383 (and (eq_attr "type" "mul")
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384 (eq_attr "dot" "yes")
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385 (eq_attr "size" "32")
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386 (eq_attr "cpu" "power6"))
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387 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
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388 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
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389
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390 (define_insn_reservation "power6-lmul" 16
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391 (and (eq_attr "type" "mul")
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392 (eq_attr "dot" "no")
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393 (eq_attr "size" "64")
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394 (eq_attr "cpu" "power6"))
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395 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
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396 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
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397
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398 (define_insn_reservation "power6-imul" 16
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399 (and (eq_attr "type" "mul")
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400 (eq_attr "dot" "no")
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401 (eq_attr "size" "32")
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402 (eq_attr "cpu" "power6"))
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403 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
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404 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
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405
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406 (define_insn_reservation "power6-imul3" 16
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407 (and (eq_attr "type" "mul")
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408 (eq_attr "size" "8,16")
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409 (eq_attr "cpu" "power6"))
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410 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
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411 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
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412
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413 (define_bypass 9 "power6-imul,\
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414 power6-lmul,\
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415 power6-imul-cmp,\
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416 power6-lmul-cmp,\
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417 power6-imul3"
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418 "power6-store,\
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419 power6-store-update,\
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420 power6-store-update-indexed,\
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421 power6-fpstore,\
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422 power6-fpstore-update"
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423 "rs6000_store_data_bypass_p")
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424
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425 (define_insn_reservation "power6-idiv" 44
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426 (and (eq_attr "type" "div")
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427 (eq_attr "size" "32")
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428 (eq_attr "cpu" "power6"))
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429 "(iu1_power6*44+iu2_power6*44+fpu1_power6*44)\
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430 |(iu1_power6*44+iu2_power6*44+fpu2_power6*44)");
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431
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432 ; The latency for this bypass is yet to be defined
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433 ;(define_bypass ? "power6-idiv"
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434 ; "power6-store,\
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435 ; power6-store-update,\
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436 ; power6-store-update-indexed,\
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437 ; power6-fpstore,\
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438 ; power6-fpstore-update"
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439 ; "rs6000_store_data_bypass_p")
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440
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441 (define_insn_reservation "power6-ldiv" 56
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442 (and (eq_attr "type" "div")
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443 (eq_attr "size" "64")
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444 (eq_attr "cpu" "power6"))
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445 "(iu1_power6*56+iu2_power6*56+fpu1_power6*56)\
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446 |(iu1_power6*56+iu2_power6*56+fpu2_power6*56)");
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447
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448 ; The latency for this bypass is yet to be defined
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449 ;(define_bypass ? "power6-ldiv"
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450 ; "power6-store,\
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451 ; power6-store-update,\
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452 ; power6-store-update-indexed,\
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453 ; power6-fpstore,\
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454 ; power6-fpstore-update"
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455 ; "rs6000_store_data_bypass_p")
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456
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457 (define_insn_reservation "power6-mtjmpr" 2
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458 (and (eq_attr "type" "mtjmpr,mfjmpr")
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459 (eq_attr "cpu" "power6"))
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460 "BX2_power6")
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461
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462 (define_bypass 5 "power6-mtjmpr" "power6-branch")
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463
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464 (define_insn_reservation "power6-branch" 2
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465 (and (eq_attr "type" "jmpreg,branch")
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466 (eq_attr "cpu" "power6"))
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467 "BRU_power6")
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468
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469 (define_bypass 5 "power6-branch" "power6-mtjmpr")
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470
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471 (define_insn_reservation "power6-crlogical" 3
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472 (and (eq_attr "type" "cr_logical")
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473 (eq_attr "cpu" "power6"))
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474 "BRU_power6")
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475
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476 (define_bypass 3 "power6-crlogical" "power6-branch")
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477
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478 (define_insn_reservation "power6-delayedcr" 3
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479 (and (eq_attr "type" "delayed_cr")
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480 (eq_attr "cpu" "power6"))
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481 "BRU_power6")
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482
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483 (define_insn_reservation "power6-mfcr" 6 ; N/A
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484 (and (eq_attr "type" "mfcr")
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485 (eq_attr "cpu" "power6"))
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486 "BX2_power6")
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487
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488 ; mfcrf (1 field)
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489 (define_insn_reservation "power6-mfcrf" 3 ; N/A
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|
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490 (and (eq_attr "type" "mfcrf")
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491 (eq_attr "cpu" "power6"))
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492 "BX2_power6") ;
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493
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494 ; mtcrf (1 field)
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495 (define_insn_reservation "power6-mtcr" 4 ; N/A
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496 (and (eq_attr "type" "mtcr")
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497 (eq_attr "cpu" "power6"))
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498 "BX2_power6")
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499
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500 (define_bypass 9 "power6-mtcr" "power6-branch")
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501
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502 (define_insn_reservation "power6-fp" 6
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503 (and (eq_attr "type" "fp,fpsimple,dmul,dfp")
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504 (eq_attr "cpu" "power6"))
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505 "FPU_power6")
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506
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|
507 ; Any fp instruction that updates a CR has a latency
|
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|
508 ; of 6 to a dependent branch
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509 (define_bypass 6 "power6-fp" "power6-branch")
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|
510
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511 (define_bypass 1 "power6-fp"
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512 "power6-fpstore,power6-fpstore-update"
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513 "rs6000_store_data_bypass_p")
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514
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515 (define_insn_reservation "power6-fpcompare" 8
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|
516 (and (eq_attr "type" "fpcompare")
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517 (eq_attr "cpu" "power6"))
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|
518 "FPU_power6")
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|
|
519
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520 (define_bypass 12 "power6-fpcompare"
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521 "power6-branch,power6-crlogical")
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|
522
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523 (define_insn_reservation "power6-sdiv" 26
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|
524 (and (eq_attr "type" "sdiv")
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525 (eq_attr "cpu" "power6"))
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526 "FPU_power6")
|
|
|
527
|
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528 (define_insn_reservation "power6-ddiv" 32
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529 (and (eq_attr "type" "ddiv")
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530 (eq_attr "cpu" "power6"))
|
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531 "FPU_power6")
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532
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533 (define_insn_reservation "power6-sqrt" 30
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534 (and (eq_attr "type" "ssqrt")
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|
535 (eq_attr "cpu" "power6"))
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|
536 "FPU_power6")
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537
|
|
|
538 (define_insn_reservation "power6-dsqrt" 42
|
|
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539 (and (eq_attr "type" "dsqrt")
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|
|
540 (eq_attr "cpu" "power6"))
|
|
|
541 "FPU_power6")
|
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|
542
|
|
|
543 (define_insn_reservation "power6-isync" 2 ; N/A
|
|
|
544 (and (eq_attr "type" "isync")
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|
|
545 (eq_attr "cpu" "power6"))
|
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|
546 "FXU_power6")
|
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|
547
|
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548 (define_insn_reservation "power6-vecload" 1
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|
549 (and (eq_attr "type" "vecload")
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550 (eq_attr "cpu" "power6"))
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|
|
551 "LSU_power6")
|
|
|
552
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|
553 (define_insn_reservation "power6-vecstore" 1
|
|
|
554 (and (eq_attr "type" "vecstore")
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|
555 (eq_attr "cpu" "power6"))
|
|
|
556 "LSF_power6")
|
|
|
557
|
|
|
558 (define_insn_reservation "power6-vecsimple" 3
|
|
|
559 (and (eq_attr "type" "vecsimple,veclogical,vecmove")
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|
|
560 (eq_attr "cpu" "power6"))
|
|
|
561 "FPU_power6")
|
|
|
562
|
|
|
563 (define_bypass 6 "power6-vecsimple" "power6-veccomplex,\
|
|
|
564 power6-vecperm")
|
|
|
565
|
|
|
566 (define_bypass 5 "power6-vecsimple" "power6-vecfloat")
|
|
|
567
|
|
|
568 (define_bypass 4 "power6-vecsimple" "power6-vecstore" )
|
|
|
569
|
|
|
570 (define_insn_reservation "power6-veccmp" 1
|
|
|
571 (and (eq_attr "type" "veccmp,veccmpfx")
|
|
|
572 (eq_attr "cpu" "power6"))
|
|
|
573 "FPU_power6")
|
|
|
574
|
|
|
575 (define_bypass 10 "power6-veccmp" "power6-branch")
|
|
|
576
|
|
|
577 (define_insn_reservation "power6-vecfloat" 7
|
|
|
578 (and (eq_attr "type" "vecfloat")
|
|
|
579 (eq_attr "cpu" "power6"))
|
|
|
580 "FPU_power6")
|
|
|
581
|
|
|
582 (define_bypass 10 "power6-vecfloat" "power6-vecsimple")
|
|
|
583
|
|
|
584 (define_bypass 11 "power6-vecfloat" "power6-veccomplex,\
|
|
|
585 power6-vecperm")
|
|
|
586
|
|
|
587 (define_bypass 9 "power6-vecfloat" "power6-vecstore" )
|
|
|
588
|
|
|
589 (define_insn_reservation "power6-veccomplex" 7
|
|
|
590 (and (eq_attr "type" "vecsimple")
|
|
|
591 (eq_attr "cpu" "power6"))
|
|
|
592 "FPU_power6")
|
|
|
593
|
|
|
594 (define_bypass 10 "power6-veccomplex" "power6-vecsimple,\
|
|
|
595 power6-vecfloat" )
|
|
|
596
|
|
|
597 (define_bypass 9 "power6-veccomplex" "power6-vecperm" )
|
|
|
598
|
|
|
599 (define_bypass 8 "power6-veccomplex" "power6-vecstore" )
|
|
|
600
|
|
|
601 (define_insn_reservation "power6-vecperm" 4
|
|
|
602 (and (eq_attr "type" "vecperm")
|
|
|
603 (eq_attr "cpu" "power6"))
|
|
|
604 "FPU_power6")
|
|
|
605
|
|
|
606 (define_bypass 7 "power6-vecperm" "power6-vecsimple,\
|
|
|
607 power6-vecfloat" )
|
|
|
608
|
|
|
609 (define_bypass 6 "power6-vecperm" "power6-veccomplex" )
|
|
|
610
|
|
|
611 (define_bypass 5 "power6-vecperm" "power6-vecstore" )
|
|
|
612
|
|
|
613 (define_insn_reservation "power6-mftgpr" 8
|
|
|
614 (and (eq_attr "type" "mftgpr")
|
|
|
615 (eq_attr "cpu" "power6"))
|
|
|
616 "X2F_power6")
|
|
|
617
|
|
|
618 (define_insn_reservation "power6-mffgpr" 14
|
|
|
619 (and (eq_attr "type" "mffgpr")
|
|
|
620 (eq_attr "cpu" "power6"))
|
|
|
621 "LX2_power6")
|
|
|
622
|
|
|
623 (define_bypass 4 "power6-mftgpr" "power6-imul,\
|
|
|
624 power6-lmul,\
|
|
|
625 power6-imul-cmp,\
|
|
|
626 power6-lmul-cmp,\
|
|
|
627 power6-imul3,\
|
|
|
628 power6-idiv,\
|
|
|
629 power6-ldiv" )
|
