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annotate gcc/config/powerpcspe/power8.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 ;; Scheduling description for IBM POWER8 processor.
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84e7813d76e9 gcc-8.2
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2 ;; Copyright (C) 2013-2018 Free Software Foundation, Inc.
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3 ;;
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4 ;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
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5
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6 ;; This file is part of GCC.
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7 ;;
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8 ;; GCC is free software; you can redistribute it and/or modify it
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9 ;; under the terms of the GNU General Public License as published
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10 ;; by the Free Software Foundation; either version 3, or (at your
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11 ;; option) any later version.
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12 ;;
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13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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16 ;; License for more details.
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17 ;;
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 (define_automaton "power8fxu,power8lsu,power8vsu,power8misc")
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23
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24 (define_cpu_unit "fxu0_power8,fxu1_power8" "power8fxu")
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25 (define_cpu_unit "lu0_power8,lu1_power8" "power8lsu")
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26 (define_cpu_unit "lsu0_power8,lsu1_power8" "power8lsu")
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27 (define_cpu_unit "vsu0_power8,vsu1_power8" "power8vsu")
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28 (define_cpu_unit "bpu_power8,cru_power8" "power8misc")
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29 (define_cpu_unit "du0_power8,du1_power8,du2_power8,du3_power8,du4_power8,\
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30 du5_power8,du6_power8" "power8misc")
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31
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32
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33 ; Dispatch group reservations
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34 (define_reservation "DU_any_power8"
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35 "du0_power8|du1_power8|du2_power8|du3_power8|du4_power8|\
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36 du5_power8")
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37
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38 ; 2-way Cracked instructions go in slots 0-1
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39 ; (can also have a second in slots 3-4 if insns are adjacent)
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40 (define_reservation "DU_cracked_power8"
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41 "du0_power8+du1_power8")
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42
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43 ; Insns that are first in group
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44 (define_reservation "DU_first_power8"
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45 "du0_power8")
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46
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47 ; Insns that are first and last in group
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48 (define_reservation "DU_both_power8"
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49 "du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+\
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50 du5_power8+du6_power8")
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51
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52 ; Dispatch slots are allocated in order conforming to program order.
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53 (absence_set "du0_power8" "du1_power8,du2_power8,du3_power8,du4_power8,\
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54 du5_power8,du6_power8")
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55 (absence_set "du1_power8" "du2_power8,du3_power8,du4_power8,du5_power8,\
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56 du6_power8")
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57 (absence_set "du2_power8" "du3_power8,du4_power8,du5_power8,du6_power8")
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58 (absence_set "du3_power8" "du4_power8,du5_power8,du6_power8")
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59 (absence_set "du4_power8" "du5_power8,du6_power8")
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60 (absence_set "du5_power8" "du6_power8")
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61
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62
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63 ; Execution unit reservations
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64 (define_reservation "FXU_power8"
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65 "fxu0_power8|fxu1_power8")
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66
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67 (define_reservation "LU_power8"
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68 "lu0_power8|lu1_power8")
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69
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70 (define_reservation "LSU_power8"
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71 "lsu0_power8|lsu1_power8")
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72
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73 (define_reservation "LU_or_LSU_power8"
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74 "lu0_power8|lu1_power8|lsu0_power8|lsu1_power8")
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75
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76 (define_reservation "VSU_power8"
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77 "vsu0_power8|vsu1_power8")
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78
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79
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80 ; LS Unit
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81 (define_insn_reservation "power8-load" 3
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82 (and (eq_attr "type" "load")
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83 (eq_attr "sign_extend" "no")
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84 (eq_attr "update" "no")
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85 (eq_attr "cpu" "power8"))
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86 "DU_any_power8,LU_or_LSU_power8")
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87
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88 (define_insn_reservation "power8-load-update" 3
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89 (and (eq_attr "type" "load")
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90 (eq_attr "sign_extend" "no")
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91 (eq_attr "update" "yes")
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92 (eq_attr "cpu" "power8"))
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93 "DU_cracked_power8,LU_or_LSU_power8+FXU_power8")
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94
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95 (define_insn_reservation "power8-load-ext" 3
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96 (and (eq_attr "type" "load")
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97 (eq_attr "sign_extend" "yes")
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98 (eq_attr "update" "no")
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99 (eq_attr "cpu" "power8"))
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100 "DU_cracked_power8,LU_or_LSU_power8,FXU_power8")
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101
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102 (define_insn_reservation "power8-load-ext-update" 3
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103 (and (eq_attr "type" "load")
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104 (eq_attr "sign_extend" "yes")
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105 (eq_attr "update" "yes")
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106 (eq_attr "cpu" "power8"))
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107 "DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8")
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108
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109 (define_insn_reservation "power8-fpload" 5
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110 (and (ior (eq_attr "type" "vecload")
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111 (and (eq_attr "type" "fpload")
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112 (eq_attr "update" "no")))
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113 (eq_attr "cpu" "power8"))
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114 "DU_any_power8,LU_power8")
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115
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116 (define_insn_reservation "power8-fpload-update" 5
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117 (and (eq_attr "type" "fpload")
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118 (eq_attr "update" "yes")
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119 (eq_attr "cpu" "power8"))
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120 "DU_cracked_power8,LU_power8+FXU_power8")
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121
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122 (define_insn_reservation "power8-store" 5 ; store-forwarding latency
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123 (and (eq_attr "type" "store")
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124 (not (and (eq_attr "update" "yes")
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125 (eq_attr "indexed" "yes")))
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126 (eq_attr "cpu" "power8"))
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127 "DU_any_power8,LSU_power8+LU_power8")
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128
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129 (define_insn_reservation "power8-store-update-indexed" 5
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130 (and (eq_attr "type" "store")
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131 (eq_attr "update" "yes")
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132 (eq_attr "indexed" "yes")
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133 (eq_attr "cpu" "power8"))
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134 "DU_cracked_power8,LSU_power8+LU_power8")
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135
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136 (define_insn_reservation "power8-fpstore" 5
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137 (and (eq_attr "type" "fpstore")
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138 (eq_attr "update" "no")
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139 (eq_attr "cpu" "power8"))
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140 "DU_any_power8,LSU_power8+VSU_power8")
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141
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142 (define_insn_reservation "power8-fpstore-update" 5
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143 (and (eq_attr "type" "fpstore")
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144 (eq_attr "update" "yes")
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145 (eq_attr "cpu" "power8"))
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146 "DU_any_power8,LSU_power8+VSU_power8")
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147
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148 (define_insn_reservation "power8-vecstore" 5
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149 (and (eq_attr "type" "vecstore")
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150 (eq_attr "cpu" "power8"))
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151 "DU_cracked_power8,LSU_power8+VSU_power8")
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152
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153 (define_insn_reservation "power8-larx" 3
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154 (and (eq_attr "type" "load_l")
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155 (eq_attr "cpu" "power8"))
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156 "DU_both_power8,LU_or_LSU_power8")
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157
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158 (define_insn_reservation "power8-stcx" 10
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159 (and (eq_attr "type" "store_c")
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160 (eq_attr "cpu" "power8"))
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161 "DU_both_power8,LSU_power8+LU_power8")
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162
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163 (define_insn_reservation "power8-sync" 1
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164 (and (eq_attr "type" "sync,isync")
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165 (eq_attr "cpu" "power8"))
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166 "DU_both_power8,LSU_power8")
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167
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168
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169 ; FX Unit
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170 (define_insn_reservation "power8-1cyc" 1
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171 (and (ior (eq_attr "type" "integer,insert,trap,isel")
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172 (and (eq_attr "type" "add,logical,shift,exts")
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173 (eq_attr "dot" "no")))
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174 (eq_attr "cpu" "power8"))
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175 "DU_any_power8,FXU_power8")
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176
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177 ; Extra cycle to LU/LSU
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178 (define_bypass 2 "power8-1cyc"
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179 "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\
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180 power8-vecstore,power8-larx,power8-stcx")
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181 ; "power8-load,power8-load-update,power8-load-ext,\
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182 ; power8-load-ext-update,power8-fpload,power8-fpload-update,\
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183 ; power8-store,power8-store-update,power8-store-update-indexed,\
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184 ; power8-fpstore,power8-fpstore-update,power8-vecstore,\
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185 ; power8-larx,power8-stcx")
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186
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187 (define_insn_reservation "power8-2cyc" 2
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188 (and (eq_attr "type" "cntlz,popcnt")
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189 (eq_attr "cpu" "power8"))
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190 "DU_any_power8,FXU_power8")
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191
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192 (define_insn_reservation "power8-two" 2
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193 (and (eq_attr "type" "two")
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194 (eq_attr "cpu" "power8"))
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195 "DU_any_power8+DU_any_power8,FXU_power8,FXU_power8")
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196
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197 (define_insn_reservation "power8-three" 3
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198 (and (eq_attr "type" "three")
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199 (eq_attr "cpu" "power8"))
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200 "DU_any_power8+DU_any_power8+DU_any_power8,FXU_power8,FXU_power8,FXU_power8")
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201
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202 ; cmp - Normal compare insns
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203 (define_insn_reservation "power8-cmp" 2
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204 (and (eq_attr "type" "cmp")
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205 (eq_attr "cpu" "power8"))
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206 "DU_any_power8,FXU_power8")
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207
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208 ; add/logical with dot : add./and./nor./etc
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209 (define_insn_reservation "power8-fast-compare" 2
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210 (and (eq_attr "type" "add,logical")
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211 (eq_attr "dot" "yes")
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212 (eq_attr "cpu" "power8"))
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213 "DU_any_power8,FXU_power8")
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214
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215 ; exts/shift with dot : rldicl./exts./rlwinm./slwi./rlwnm./slw./etc
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216 (define_insn_reservation "power8-compare" 2
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217 (and (eq_attr "type" "shift,exts")
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218 (eq_attr "dot" "yes")
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219 (eq_attr "cpu" "power8"))
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220 "DU_cracked_power8,FXU_power8,FXU_power8")
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221
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222 ; Extra cycle to LU/LSU
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223 (define_bypass 3 "power8-fast-compare,power8-compare"
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224 "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\
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225 power8-vecstore,power8-larx,power8-stcx")
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226
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227 ; 5 cycle CR latency
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228 (define_bypass 5 "power8-fast-compare,power8-compare"
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229 "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch")
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230
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231 (define_insn_reservation "power8-mul" 4
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232 (and (eq_attr "type" "mul")
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233 (eq_attr "dot" "no")
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234 (eq_attr "cpu" "power8"))
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235 "DU_any_power8,FXU_power8")
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236
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237 (define_insn_reservation "power8-mul-compare" 4
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238 (and (eq_attr "type" "mul")
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239 (eq_attr "dot" "yes")
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240 (eq_attr "cpu" "power8"))
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241 "DU_cracked_power8,FXU_power8")
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242
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243 ; Extra cycle to LU/LSU
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244 (define_bypass 5 "power8-mul,power8-mul-compare"
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245 "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\
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246 power8-vecstore,power8-larx,power8-stcx")
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247
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248 ; 7 cycle CR latency
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249 (define_bypass 7 "power8-mul,power8-mul-compare"
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250 "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch")
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251
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252 ; FXU divides are not pipelined
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253 (define_insn_reservation "power8-idiv" 37
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254 (and (eq_attr "type" "div")
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255 (eq_attr "size" "32")
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256 (eq_attr "cpu" "power8"))
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257 "DU_any_power8,fxu0_power8*37|fxu1_power8*37")
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258
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259 (define_insn_reservation "power8-ldiv" 68
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260 (and (eq_attr "type" "div")
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261 (eq_attr "size" "64")
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262 (eq_attr "cpu" "power8"))
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263 "DU_any_power8,fxu0_power8*68|fxu1_power8*68")
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264
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265 (define_insn_reservation "power8-mtjmpr" 5
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266 (and (eq_attr "type" "mtjmpr")
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267 (eq_attr "cpu" "power8"))
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268 "DU_first_power8,FXU_power8")
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269
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270 ; Should differentiate between 1 cr field and > 1 since mtocrf is not microcode
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271 (define_insn_reservation "power8-mtcr" 3
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272 (and (eq_attr "type" "mtcr")
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273 (eq_attr "cpu" "power8"))
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274 "DU_both_power8,FXU_power8")
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275
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276
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277 ; CR Unit
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278 (define_insn_reservation "power8-mfjmpr" 5
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279 (and (eq_attr "type" "mfjmpr")
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280 (eq_attr "cpu" "power8"))
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281 "DU_first_power8,cru_power8+FXU_power8")
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282
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283 (define_insn_reservation "power8-crlogical" 3
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parents:
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284 (and (eq_attr "type" "cr_logical,delayed_cr")
kono
parents:
diff changeset
285 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
286 "DU_first_power8,cru_power8")
kono
parents:
diff changeset
287
kono
parents:
diff changeset
288 (define_insn_reservation "power8-mfcr" 5
kono
parents:
diff changeset
289 (and (eq_attr "type" "mfcr")
kono
parents:
diff changeset
290 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
291 "DU_both_power8,cru_power8")
kono
parents:
diff changeset
292
kono
parents:
diff changeset
293 (define_insn_reservation "power8-mfcrf" 3
kono
parents:
diff changeset
294 (and (eq_attr "type" "mfcrf")
kono
parents:
diff changeset
295 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
296 "DU_first_power8,cru_power8")
kono
parents:
diff changeset
297
kono
parents:
diff changeset
298
kono
parents:
diff changeset
299 ; BR Unit
kono
parents:
diff changeset
300 ; Branches take dispatch slot 7, but reserve any remaining prior slots to
kono
parents:
diff changeset
301 ; prevent other insns from grabbing them once this is assigned.
kono
parents:
diff changeset
302 (define_insn_reservation "power8-branch" 3
kono
parents:
diff changeset
303 (and (eq_attr "type" "jmpreg,branch")
kono
parents:
diff changeset
304 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
305 "(du6_power8\
kono
parents:
diff changeset
306 |du5_power8+du6_power8\
kono
parents:
diff changeset
307 |du4_power8+du5_power8+du6_power8\
kono
parents:
diff changeset
308 |du3_power8+du4_power8+du5_power8+du6_power8\
kono
parents:
diff changeset
309 |du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\
kono
parents:
diff changeset
310 |du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\
kono
parents:
diff changeset
311 |du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+\
kono
parents:
diff changeset
312 du6_power8),bpu_power8")
kono
parents:
diff changeset
313
kono
parents:
diff changeset
314 ; Branch updating LR/CTR feeding mf[lr|ctr]
kono
parents:
diff changeset
315 (define_bypass 4 "power8-branch" "power8-mfjmpr")
kono
parents:
diff changeset
316
kono
parents:
diff changeset
317
kono
parents:
diff changeset
318 ; VS Unit (includes FP/VSX/VMX/DFP/Crypto)
kono
parents:
diff changeset
319 (define_insn_reservation "power8-fp" 6
kono
parents:
diff changeset
320 (and (eq_attr "type" "fp,fpsimple,dmul,dfp")
kono
parents:
diff changeset
321 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
322 "DU_any_power8,VSU_power8")
kono
parents:
diff changeset
323
kono
parents:
diff changeset
324 ; Additional 3 cycles for any CR result
kono
parents:
diff changeset
325 (define_bypass 9 "power8-fp" "power8-crlogical,power8-mfcr*,power8-branch")
kono
parents:
diff changeset
326
kono
parents:
diff changeset
327 (define_insn_reservation "power8-fpcompare" 8
kono
parents:
diff changeset
328 (and (eq_attr "type" "fpcompare")
kono
parents:
diff changeset
329 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
330 "DU_any_power8,VSU_power8")
kono
parents:
diff changeset
331
kono
parents:
diff changeset
332 (define_insn_reservation "power8-sdiv" 27
kono
parents:
diff changeset
333 (and (eq_attr "type" "sdiv")
kono
parents:
diff changeset
334 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
335 "DU_any_power8,VSU_power8")
kono
parents:
diff changeset
336
kono
parents:
diff changeset
337 (define_insn_reservation "power8-ddiv" 33
kono
parents:
diff changeset
338 (and (eq_attr "type" "ddiv")
kono
parents:
diff changeset
339 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
340 "DU_any_power8,VSU_power8")
kono
parents:
diff changeset
341
kono
parents:
diff changeset
342 (define_insn_reservation "power8-sqrt" 32
kono
parents:
diff changeset
343 (and (eq_attr "type" "ssqrt")
kono
parents:
diff changeset
344 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
345 "DU_any_power8,VSU_power8")
kono
parents:
diff changeset
346
kono
parents:
diff changeset
347 (define_insn_reservation "power8-dsqrt" 44
kono
parents:
diff changeset
348 (and (eq_attr "type" "dsqrt")
kono
parents:
diff changeset
349 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
350 "DU_any_power8,VSU_power8")
kono
parents:
diff changeset
351
kono
parents:
diff changeset
352 (define_insn_reservation "power8-vecsimple" 2
kono
parents:
diff changeset
353 (and (eq_attr "type" "vecperm,vecsimple,veclogical,vecmove,veccmp,
kono
parents:
diff changeset
354 veccmpfx")
kono
parents:
diff changeset
355 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
356 "DU_any_power8,VSU_power8")
kono
parents:
diff changeset
357
kono
parents:
diff changeset
358 (define_insn_reservation "power8-vecnormal" 6
kono
parents:
diff changeset
359 (and (eq_attr "type" "vecfloat,vecdouble")
kono
parents:
diff changeset
360 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
361 "DU_any_power8,VSU_power8")
kono
parents:
diff changeset
362
kono
parents:
diff changeset
363 (define_bypass 7 "power8-vecnormal"
kono
parents:
diff changeset
364 "power8-vecsimple,power8-veccomplex,power8-fpstore*,\
kono
parents:
diff changeset
365 power8-vecstore")
kono
parents:
diff changeset
366
kono
parents:
diff changeset
367 (define_insn_reservation "power8-veccomplex" 7
kono
parents:
diff changeset
368 (and (eq_attr "type" "veccomplex")
kono
parents:
diff changeset
369 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
370 "DU_any_power8,VSU_power8")
kono
parents:
diff changeset
371
kono
parents:
diff changeset
372 (define_insn_reservation "power8-vecfdiv" 25
kono
parents:
diff changeset
373 (and (eq_attr "type" "vecfdiv")
kono
parents:
diff changeset
374 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
375 "DU_any_power8,VSU_power8")
kono
parents:
diff changeset
376
kono
parents:
diff changeset
377 (define_insn_reservation "power8-vecdiv" 31
kono
parents:
diff changeset
378 (and (eq_attr "type" "vecdiv")
kono
parents:
diff changeset
379 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
380 "DU_any_power8,VSU_power8")
kono
parents:
diff changeset
381
kono
parents:
diff changeset
382 (define_insn_reservation "power8-mffgpr" 5
kono
parents:
diff changeset
383 (and (eq_attr "type" "mffgpr")
kono
parents:
diff changeset
384 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
385 "DU_any_power8,VSU_power8")
kono
parents:
diff changeset
386
kono
parents:
diff changeset
387 (define_insn_reservation "power8-mftgpr" 6
kono
parents:
diff changeset
388 (and (eq_attr "type" "mftgpr")
kono
parents:
diff changeset
389 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
390 "DU_any_power8,VSU_power8")
kono
parents:
diff changeset
391
kono
parents:
diff changeset
392 (define_insn_reservation "power8-crypto" 7
kono
parents:
diff changeset
393 (and (eq_attr "type" "crypto")
kono
parents:
diff changeset
394 (eq_attr "cpu" "power8"))
kono
parents:
diff changeset
395 "DU_any_power8,VSU_power8")
kono
parents:
diff changeset
396