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1 ;; Scheduling description for the Xilinx PowerPC 405 APU Floating Point Unit.
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2 ;; Copyright (C) 2008-2018 Free Software Foundation, Inc.
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3 ;; Contributed by Michael Eager (eager@eagercon.com).
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify
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8 ;; it under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful,
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13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 ;; GNU General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;;----------------------------------------------------
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22 ;; Xilinx APU FPU Pipeline Description
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23 ;;
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24 ;; - attr 'type' and 'fp_type' should definitely
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25 ;; be cleaned up at some point in the future.
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26 ;; ddiv,sdiv,dmul,smul etc are quite confusing.
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27 ;; Should use consistent fp* attrs. 'fp_type'
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28 ;; should also go away, leaving us only with 'fp'
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29 ;;
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30 ;;----------------------------------------------------
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31
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32 ;; -------------------------------------------------------------------------
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33 ;; Latencies
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34 ;; Latest latency figures (all in FCB cycles). PowerPC to FPU frequency ratio
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35 ;; assumed to be 1/2. (most common deployment)
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36 ;; Add 2 PPC cycles for (register file access + wb) and 2 PPC cycles
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37 ;; for issue (from PPC)
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38 ;; SP DP
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39 ;; Loads: 4 6
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40 ;; Stores: 1 2 (from availability of data)
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41 ;; Move/Abs/Neg: 1 1
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42 ;; Add/Subtract: 5 7
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43 ;; Multiply: 4 11
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44 ;; Multiply-add: 10 19
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45 ;; Convert (any): 4 6
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46 ;; Divide/Sqrt: 27 56
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47 ;; Compares: 1 2
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48 ;;
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49 ;; bypasses needed for forwarding capability of the FPU.
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50 ;; Add this at some future time.
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51 ;; -------------------------------------------------------------------------
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52 (define_automaton "Xfpu")
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53 (define_cpu_unit "Xfpu_issue,Xfpu_addsub,Xfpu_mul,Xfpu_div,Xfpu_sqrt" "Xfpu")
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54
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55
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56 (define_insn_reservation "fp-default" 2
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57 (and (and
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58 (eq_attr "type" "fp,fpsimple")
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59 (eq_attr "fp_type" "fp_default"))
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60 (eq_attr "cpu" "ppc405"))
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61 "Xfpu_issue*2")
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62
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63 (define_insn_reservation "fp-compare" 6
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64 (and (eq_attr "type" "fpcompare") ;; Inconsistent naming
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65 (eq_attr "cpu" "ppc405"))
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66 "Xfpu_issue*2,Xfpu_addsub")
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67
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68 (define_insn_reservation "fp-addsub-s" 14
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69 (and (and
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70 (eq_attr "type" "fp,fpsimple")
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71 (eq_attr "fp_type" "fp_addsub_s"))
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72 (eq_attr "cpu" "ppc405"))
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73 "Xfpu_issue*2,Xfpu_addsub")
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74
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75 (define_insn_reservation "fp-addsub-d" 18
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76 (and (and
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77 (eq_attr "type" "fp,fpsimple")
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78 (eq_attr "fp_type" "fp_addsub_d"))
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79 (eq_attr "cpu" "ppc405"))
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80 "Xfpu_issue*2,Xfpu_addsub")
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81
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82 (define_insn_reservation "fp-mul-s" 12
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83 (and (and
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84 (eq_attr "type" "fp")
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85 (eq_attr "fp_type" "fp_mul_s"))
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86 (eq_attr "cpu" "ppc405"))
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87 "Xfpu_issue*2,Xfpu_mul")
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88
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89 (define_insn_reservation "fp-mul-d" 16 ;; Actually 28. Long latencies are killing the automaton formation. Need to figure out why.
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90 (and (and
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91 (eq_attr "type" "fp")
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92 (eq_attr "fp_type" "fp_mul_d"))
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93 (eq_attr "cpu" "ppc405"))
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94 "Xfpu_issue*2,Xfpu_mul")
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95
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96 (define_insn_reservation "fp-div-s" 24 ;; Actually 34
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97 (and (eq_attr "type" "sdiv") ;; Inconsistent attr naming
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98 (eq_attr "cpu" "ppc405"))
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99 "Xfpu_issue*2,Xfpu_div*10") ;; Unpipelined
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100
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101 (define_insn_reservation "fp-div-d" 34 ;; Actually 116
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102 (and (eq_attr "type" "ddiv")
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103 (eq_attr "cpu" "ppc405")) ;; Inconsistent attr naming
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104 "Xfpu_issue*2,Xfpu_div*10") ;; Unpipelined
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105
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106 (define_insn_reservation "fp-maddsub-s" 24
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107 (and (and
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108 (eq_attr "type" "fp")
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109 (eq_attr "fp_type" "fp_maddsub_s"))
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110 (eq_attr "cpu" "ppc405"))
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111 "Xfpu_issue*2,Xfpu_mul,nothing*7,Xfpu_addsub")
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112
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113 (define_insn_reservation "fp-maddsub-d" 34 ;; Actually 42
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114 (and (and
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115 (eq_attr "type" "dmul") ;; Inconsistent attr naming
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116 (eq_attr "fp_type" "fp_maddsub_d"))
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117 (eq_attr "cpu" "ppc405"))
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118 "Xfpu_issue*2,Xfpu_mul,nothing*7,Xfpu_addsub")
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119
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120 (define_insn_reservation "fp-load" 10 ;; FIXME. Is double/single precision the same ?
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121 (and (eq_attr "type" "fpload")
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122 (eq_attr "cpu" "ppc405"))
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123 "Xfpu_issue*10")
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124
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125 (define_insn_reservation "fp-store" 4
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126 (and (eq_attr "type" "fpstore")
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127 (eq_attr "cpu" "ppc405"))
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128 "Xfpu_issue*4")
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129
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130 (define_insn_reservation "fp-sqrt-s" 24 ;; Actually 56
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131 (and (eq_attr "type" "ssqrt")
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132 (eq_attr "cpu" "ppc405"))
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133 "Xfpu_issue*2,Xfpu_sqrt*10") ;; Unpipelined
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134
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135
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136 (define_insn_reservation "fp-sqrt-d" 34 ;; Actually 116
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137 (and (eq_attr "type" "dsqrt")
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138 (eq_attr "cpu" "ppc405"))
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139 "Xfpu_issue*2,Xfpu_sqrt*10") ;; Unpipelined
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140
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