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1 /* RISC-V-specific code for C family languages.
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2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
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3 Contributed by Andrew Waterman (andrew@sifive.com).
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify
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8 it under the terms of the GNU General Public License as published by
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9 the Free Software Foundation; either version 3, or (at your option)
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10 any later version.
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11
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12 GCC is distributed in the hope that it will be useful,
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13 but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 GNU General Public License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21 #define IN_TARGET_CODE 1
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22
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23 #include "config.h"
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24 #include "system.h"
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25 #include "coretypes.h"
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26 #include "tm.h"
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27 #include "c-family/c-common.h"
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28 #include "cpplib.h"
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29
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30 #define builtin_define(TXT) cpp_define (pfile, TXT)
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31
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32 /* Implement TARGET_CPU_CPP_BUILTINS. */
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33
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34 void
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35 riscv_cpu_cpp_builtins (cpp_reader *pfile)
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36 {
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37 builtin_define ("__riscv");
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38
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39 if (TARGET_RVC)
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40 builtin_define ("__riscv_compressed");
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41
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42 if (TARGET_RVE)
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43 builtin_define ("__riscv_32e");
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44
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45 if (TARGET_ATOMIC)
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46 builtin_define ("__riscv_atomic");
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47
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48 if (TARGET_MUL)
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49 builtin_define ("__riscv_mul");
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50 if (TARGET_DIV)
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51 builtin_define ("__riscv_div");
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52 if (TARGET_DIV && TARGET_MUL)
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53 builtin_define ("__riscv_muldiv");
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54
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55 builtin_define_with_int_value ("__riscv_xlen", UNITS_PER_WORD * 8);
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56 if (TARGET_HARD_FLOAT)
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57 builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
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58
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59 if (TARGET_HARD_FLOAT && TARGET_FDIV)
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60 {
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61 builtin_define ("__riscv_fdiv");
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62 builtin_define ("__riscv_fsqrt");
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63 }
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64
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65 switch (riscv_abi)
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66 {
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67 case ABI_ILP32E:
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68 builtin_define ("__riscv_abi_rve");
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69 gcc_fallthrough ();
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70
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71 case ABI_ILP32:
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72 case ABI_LP64:
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73 builtin_define ("__riscv_float_abi_soft");
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74 break;
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75
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76 case ABI_ILP32F:
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77 case ABI_LP64F:
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78 builtin_define ("__riscv_float_abi_single");
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79 break;
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80
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81 case ABI_ILP32D:
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82 case ABI_LP64D:
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83 builtin_define ("__riscv_float_abi_double");
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84 break;
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85 }
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86
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87 switch (riscv_cmodel)
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88 {
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89 case CM_MEDLOW:
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90 builtin_define ("__riscv_cmodel_medlow");
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91 break;
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92
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93 case CM_MEDANY:
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94 builtin_define ("__riscv_cmodel_medany");
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95 break;
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96
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97 case CM_PIC:
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98 builtin_define ("__riscv_cmodel_pic");
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99 break;
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100 }
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101 }
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