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1 /* Definition of RISC-V target for GNU compiler.
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2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
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3 Contributed by Andrew Waterman (andrew@sifive.com).
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4 Based on MIPS target for GNU compiler.
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5
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6 This file is part of GCC.
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7
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8 GCC is free software; you can redistribute it and/or modify
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9 it under the terms of the GNU General Public License as published by
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10 the Free Software Foundation; either version 3, or (at your option)
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11 any later version.
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12
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13 GCC is distributed in the hope that it will be useful,
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14 but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 GNU General Public License for more details.
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17
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18 You should have received a copy of the GNU General Public License
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19 along with GCC; see the file COPYING3. If not see
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20 <http://www.gnu.org/licenses/>. */
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21
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22 #ifndef GCC_RISCV_PROTOS_H
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23 #define GCC_RISCV_PROTOS_H
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24
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25 /* Symbol types we understand. The order of this list must match that of
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26 the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */
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27 enum riscv_symbol_type {
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28 SYMBOL_ABSOLUTE,
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29 SYMBOL_PCREL,
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30 SYMBOL_GOT_DISP,
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31 SYMBOL_TLS,
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32 SYMBOL_TLS_LE,
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33 SYMBOL_TLS_IE,
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34 SYMBOL_TLS_GD
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35 };
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36 #define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
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37
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38 /* Routines implemented in riscv.c. */
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39 extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
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40 extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
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41 extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool);
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42 extern int riscv_address_insns (rtx, machine_mode, bool);
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43 extern int riscv_const_insns (rtx);
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44 extern int riscv_split_const_insns (rtx);
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45 extern int riscv_load_store_insns (rtx, rtx_insn *);
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46 extern rtx riscv_emit_move (rtx, rtx);
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47 extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *);
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48 extern bool riscv_split_symbol_type (enum riscv_symbol_type);
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49 extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
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50 extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT);
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51 extern bool riscv_legitimize_move (machine_mode, rtx, rtx);
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52 extern rtx riscv_subword (rtx, bool);
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53 extern bool riscv_split_64bit_move_p (rtx, rtx);
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54 extern void riscv_split_doubleword_move (rtx, rtx);
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55 extern const char *riscv_output_move (rtx, rtx);
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56 extern const char *riscv_output_gpr_save (unsigned);
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57 extern const char *riscv_output_return ();
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58 #ifdef RTX_CODE
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59 extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx);
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60 extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
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61 extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
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62 #endif
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63 extern rtx riscv_legitimize_call_address (rtx);
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64 extern void riscv_set_return_address (rtx, rtx);
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65 extern bool riscv_expand_block_move (rtx, rtx, rtx);
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66 extern rtx riscv_return_addr (int, rtx);
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67 extern HOST_WIDE_INT riscv_initial_elimination_offset (int, int);
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68 extern void riscv_expand_prologue (void);
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69 extern void riscv_expand_epilogue (int);
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70 extern bool riscv_epilogue_uses (unsigned int);
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71 extern bool riscv_can_use_return_insn (void);
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72 extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
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73 extern bool riscv_expand_block_move (rtx, rtx, rtx);
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74
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75 /* Routines implemented in riscv-c.c. */
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76 void riscv_cpu_cpp_builtins (cpp_reader *);
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77
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78 /* Routines implemented in riscv-builtins.c. */
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79 extern void riscv_atomic_assign_expand_fenv (tree *, tree *, tree *);
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80 extern rtx riscv_expand_builtin (tree, rtx, rtx, machine_mode, int);
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81 extern tree riscv_builtin_decl (unsigned int, bool);
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82 extern void riscv_init_builtins (void);
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83
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84 #endif /* ! GCC_RISCV_PROTOS_H */
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