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1 /* Copyright (C) 2003-2018 Free Software Foundation, Inc.
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2
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3 This file is part of GCC.
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4
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5 GCC is free software; you can redistribute it and/or modify
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6 it under the terms of the GNU General Public License as published by
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7 the Free Software Foundation; either version 3, or (at your option)
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8 any later version.
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9
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10 GCC is distributed in the hope that it will be useful,
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11 but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 GNU General Public License for more details.
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14
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15 Under Section 7 of GPL version 3, you are granted additional
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16 permissions described in the GCC Runtime Library Exception, version
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17 3.1, as published by the Free Software Foundation.
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18
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19 You should have received a copy of the GNU General Public License and
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20 a copy of the GCC Runtime Library Exception along with this program;
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21 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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22 <http://www.gnu.org/licenses/>. */
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23
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24 /* Implemented from the specification included in the Intel C++ Compiler
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25 User Guide and Reference, version 9.0. */
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26
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27 #ifndef NO_WARN_X86_INTRINSICS
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28 /* This header is distributed to simplify porting x86_64 code that
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29 makes explicit use of Intel intrinsics to powerpc64le.
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30 It is the user's responsibility to determine if the results are
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31 acceptable and make additional changes as necessary.
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32 Note that much code that uses Intel intrinsics can be rewritten in
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33 standard C or GNU C extensions, which are more portable and better
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34 optimized across multiple targets.
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35
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36 In the specific case of X86 SSE3 intrinsics, the PowerPC VMX/VSX ISA
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37 is a good match for most SIMD operations. However the Horizontal
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38 add/sub requires the data pairs be permuted into a separate
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39 registers with vertical even/odd alignment for the operation.
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40 And the addsub operation requires the sign of only the even numbered
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41 elements be flipped (xored with -0.0).
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42 For larger blocks of code using these intrinsic implementations,
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43 the compiler be should be able to schedule instructions to avoid
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44 additional latency.
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45
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46 In the specific case of the monitor and mwait instructions there are
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47 no direct equivalent in the PowerISA at this time. So those
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48 intrinsics are not implemented. */
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49 #error "Please read comment above. Use -DNO_WARN_X86_INTRINSICS to disable this warning."
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50 #endif
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51
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52 #ifndef _PMMINTRIN_H_INCLUDED
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53 #define _PMMINTRIN_H_INCLUDED
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54
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55 /* We need definitions from the SSE2 and SSE header files*/
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56 #include <emmintrin.h>
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57
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58 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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59 _mm_addsub_ps (__m128 __X, __m128 __Y)
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60 {
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61 const __v4sf even_n0 = {-0.0, 0.0, -0.0, 0.0};
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62 __v4sf even_neg_Y = vec_xor(__Y, even_n0);
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63 return (__m128) vec_add (__X, even_neg_Y);
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64 }
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65
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66 extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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67 _mm_addsub_pd (__m128d __X, __m128d __Y)
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68 {
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69 const __v2df even_n0 = {-0.0, 0.0};
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70 __v2df even_neg_Y = vec_xor(__Y, even_n0);
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71 return (__m128d) vec_add (__X, even_neg_Y);
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72 }
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73
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74 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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75 _mm_hadd_ps (__m128 __X, __m128 __Y)
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76 {
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77 __vector unsigned char xform2 = {
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78 #ifdef __LITTLE_ENDIAN__
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79 0x00, 0x01, 0x02, 0x03, 0x08, 0x09, 0x0A, 0x0B, 0x10, 0x11, 0x12, 0x13, 0x18, 0x19, 0x1A, 0x1B
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80 #elif __BIG_ENDIAN__
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81 0x14, 0x15, 0x16, 0x17, 0x1C, 0x1D, 0x1E, 0x1F, 0x04, 0x05, 0x06, 0x07, 0x0C, 0x0D, 0x0E, 0x0F
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82 #endif
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83 };
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84 __vector unsigned char xform1 = {
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85 #ifdef __LITTLE_ENDIAN__
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86 0x04, 0x05, 0x06, 0x07, 0x0C, 0x0D, 0x0E, 0x0F, 0x14, 0x15, 0x16, 0x17, 0x1C, 0x1D, 0x1E, 0x1F
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87 #elif __BIG_ENDIAN__
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88 0x10, 0x11, 0x12, 0x13, 0x18, 0x19, 0x1A, 0x1B, 0x00, 0x01, 0x02, 0x03, 0x08, 0x09, 0x0A, 0x0B
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89 #endif
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90 };
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91 return (__m128) vec_add (vec_perm ((__v4sf) __X, (__v4sf) __Y, xform2),
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92 vec_perm ((__v4sf) __X, (__v4sf) __Y, xform1));
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93 }
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94
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95 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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96 _mm_hsub_ps (__m128 __X, __m128 __Y)
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97 {
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98 __vector unsigned char xform2 = {
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99 #ifdef __LITTLE_ENDIAN__
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100 0x00, 0x01, 0x02, 0x03, 0x08, 0x09, 0x0A, 0x0B, 0x10, 0x11, 0x12, 0x13, 0x18, 0x19, 0x1A, 0x1B
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101 #elif __BIG_ENDIAN__
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102 0x14, 0x15, 0x16, 0x17, 0x1C, 0x1D, 0x1E, 0x1F, 0x04, 0x05, 0x06, 0x07, 0x0C, 0x0D, 0x0E, 0x0F
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103 #endif
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104 };
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105 __vector unsigned char xform1 = {
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106 #ifdef __LITTLE_ENDIAN__
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107 0x04, 0x05, 0x06, 0x07, 0x0C, 0x0D, 0x0E, 0x0F, 0x14, 0x15, 0x16, 0x17, 0x1C, 0x1D, 0x1E, 0x1F
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108 #elif __BIG_ENDIAN__
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109 0x10, 0x11, 0x12, 0x13, 0x18, 0x19, 0x1A, 0x1B, 0x00, 0x01, 0x02, 0x03, 0x08, 0x09, 0x0A, 0x0B
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110 #endif
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111 };
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112 return (__m128) vec_sub (vec_perm ((__v4sf) __X, (__v4sf) __Y, xform2),
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113 vec_perm ((__v4sf) __X, (__v4sf) __Y, xform1));
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114 }
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115
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116 extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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117 _mm_hadd_pd (__m128d __X, __m128d __Y)
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118 {
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119 return (__m128d) vec_add (vec_mergeh ((__v2df) __X, (__v2df)__Y),
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120 vec_mergel ((__v2df) __X, (__v2df)__Y));
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121 }
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122
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123 extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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124 _mm_hsub_pd (__m128d __X, __m128d __Y)
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125 {
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126 return (__m128d) vec_sub (vec_mergeh ((__v2df) __X, (__v2df)__Y),
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127 vec_mergel ((__v2df) __X, (__v2df)__Y));
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128 }
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129
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130 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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131 _mm_movehdup_ps (__m128 __X)
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132 {
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133 return (__m128)vec_mergeo ((__v4su)__X, (__v4su)__X);
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134 }
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135
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136 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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137 _mm_moveldup_ps (__m128 __X)
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138 {
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139 return (__m128)vec_mergee ((__v4su)__X, (__v4su)__X);
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140 }
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141
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142 extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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143 _mm_loaddup_pd (double const *__P)
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144 {
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145 return (__m128d) vec_splats (*__P);
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146 }
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147
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148 extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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149 _mm_movedup_pd (__m128d __X)
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150 {
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151 return _mm_shuffle_pd (__X, __X, _MM_SHUFFLE2 (0,0));
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152 }
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153
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154 extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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155 _mm_lddqu_si128 (__m128i const *__P)
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156 {
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157 return (__m128i) (vec_vsx_ld(0, (signed int const *)__P));
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158 }
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159
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160 /* POWER8 / POWER9 have no equivalent for _mm_monitor nor _mm_wait. */
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161
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162 #endif /* _PMMINTRIN_H_INCLUDED */
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