Mercurial > hg > CbC > CbC_gcc

annotate gcc/config/rs6000/power4.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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1 ;; Scheduling description for IBM Power4 and PowerPC 970 processors.
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2 ;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published
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8 ;; by the Free Software Foundation; either version 3, or (at your
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9 ;; option) any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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14 ;; License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; Sources: IBM Red Book and White Paper on POWER4
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21
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22 ;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
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23 ;; Instructions that update more than one register get broken into two
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24 ;; (split) or more internal ops. The chip can issue up to 5
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25 ;; internal ops per cycle.
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27 (define_automaton "power4iu,power4fpu,power4vec,power4misc")
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29 (define_cpu_unit "iu1_power4,iu2_power4" "power4iu")
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30 (define_cpu_unit "lsu1_power4,lsu2_power4" "power4misc")
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31 (define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu")
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32 (define_cpu_unit "bpu_power4,cru_power4" "power4misc")
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33 (define_cpu_unit "vec_power4,vecperm_power4" "power4vec")
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34 (define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4"
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35 "power4misc")
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37 (define_reservation "lsq_power4"
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38 "(du1_power4,lsu1_power4)\
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39 |(du2_power4,lsu2_power4)\
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40 |(du3_power4,lsu2_power4)\
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41 |(du4_power4,lsu1_power4)")
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43 (define_reservation "lsuq_power4"
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44 "((du1_power4+du2_power4,lsu1_power4)\
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45 |(du2_power4+du3_power4,lsu2_power4)\
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46 |(du3_power4+du4_power4,lsu2_power4))\
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47 +(nothing,iu2_power4|nothing,iu1_power4)")
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49 (define_reservation "iq_power4"
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50 "(du1_power4|du2_power4|du3_power4|du4_power4),\
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51 (iu1_power4|iu2_power4)")
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53 (define_reservation "fpq_power4"
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54 "(du1_power4|du2_power4|du3_power4|du4_power4),\
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55 (fpu1_power4|fpu2_power4)")
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57 (define_reservation "vq_power4"
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58 "(du1_power4,vec_power4)\
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59 |(du2_power4,vec_power4)\
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60 |(du3_power4,vec_power4)\
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61 |(du4_power4,vec_power4)")
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63 (define_reservation "vpq_power4"
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64 "(du1_power4,vecperm_power4)\
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65 |(du2_power4,vecperm_power4)\
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66 |(du3_power4,vecperm_power4)\
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67 |(du4_power4,vecperm_power4)")
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69
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70 ; Dispatch slots are allocated in order conforming to program order.
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71 (absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4")
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72 (absence_set "du2_power4" "du3_power4,du4_power4,du5_power4")
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73 (absence_set "du3_power4" "du4_power4,du5_power4")
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74 (absence_set "du4_power4" "du5_power4")
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76
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77 ; Load/store
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78 (define_insn_reservation "power4-load" 4 ; 3
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79 (and (eq_attr "type" "load")
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80 (eq_attr "sign_extend" "no")
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81 (eq_attr "update" "no")
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82 (eq_attr "cpu" "power4"))
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83 "lsq_power4")
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84
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85 (define_insn_reservation "power4-load-ext" 5
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86 (and (eq_attr "type" "load")
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87 (eq_attr "sign_extend" "yes")
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88 (eq_attr "update" "no")
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89 (eq_attr "cpu" "power4"))
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90 "(du1_power4+du2_power4,lsu1_power4\
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91 |du2_power4+du3_power4,lsu2_power4\
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92 |du3_power4+du4_power4,lsu2_power4),\
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93 nothing,nothing,\
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94 (iu2_power4|iu1_power4)")
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95
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96 (define_insn_reservation "power4-load-ext-update" 5
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97 (and (eq_attr "type" "load")
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98 (eq_attr "sign_extend" "yes")
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99 (eq_attr "update" "yes")
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100 (eq_attr "indexed" "no")
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101 (eq_attr "cpu" "power4"))
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102 "du1_power4+du2_power4+du3_power4+du4_power4,\
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103 lsu1_power4+iu2_power4,nothing,nothing,iu2_power4")
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104
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105 (define_insn_reservation "power4-load-ext-update-indexed" 5
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106 (and (eq_attr "type" "load")
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107 (eq_attr "sign_extend" "yes")
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108 (eq_attr "update" "yes")
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109 (eq_attr "indexed" "yes")
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110 (eq_attr "cpu" "power4"))
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111 "du1_power4+du2_power4+du3_power4+du4_power4,\
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112 iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4")
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113
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114 (define_insn_reservation "power4-load-update-indexed" 3
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115 (and (eq_attr "type" "load")
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116 (eq_attr "sign_extend" "no")
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117 (eq_attr "update" "yes")
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118 (eq_attr "indexed" "yes")
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119 (eq_attr "cpu" "power4"))
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120 "du1_power4+du2_power4+du3_power4+du4_power4,\
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121 iu1_power4,lsu2_power4+iu2_power4")
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122
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123 (define_insn_reservation "power4-load-update" 4 ; 3
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124 (and (eq_attr "type" "load")
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125 (eq_attr "sign_extend" "no")
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126 (eq_attr "update" "yes")
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127 (eq_attr "indexed" "no")
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128 (eq_attr "cpu" "power4"))
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129 "lsuq_power4")
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130
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131 (define_insn_reservation "power4-fpload" 6 ; 5
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132 (and (eq_attr "type" "fpload")
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133 (eq_attr "update" "no")
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134 (eq_attr "cpu" "power4"))
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135 "lsq_power4")
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136
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137 (define_insn_reservation "power4-fpload-update" 6 ; 5
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138 (and (eq_attr "type" "fpload")
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139 (eq_attr "update" "yes")
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140 (eq_attr "cpu" "power4"))
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141 "lsuq_power4")
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142
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143 (define_insn_reservation "power4-vecload" 6 ; 5
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144 (and (eq_attr "type" "vecload")
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145 (eq_attr "cpu" "power4"))
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146 "lsq_power4")
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147
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148 (define_insn_reservation "power4-store" 12
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149 (and (eq_attr "type" "store")
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150 (eq_attr "update" "no")
0
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151 (eq_attr "cpu" "power4"))
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152 "((du1_power4,lsu1_power4)\
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153 |(du2_power4,lsu2_power4)\
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154 |(du3_power4,lsu2_power4)\
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155 |(du4_power4,lsu1_power4)),\
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156 (iu1_power4|iu2_power4)")
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157
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158 (define_insn_reservation "power4-store-update" 12
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159 (and (eq_attr "type" "store")
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160 (eq_attr "update" "yes")
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161 (eq_attr "indexed" "no")
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162 (eq_attr "cpu" "power4"))
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163 "((du1_power4+du2_power4,lsu1_power4)\
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164 |(du2_power4+du3_power4,lsu2_power4)\
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165 |(du3_power4+du4_power4,lsu2_power4))+\
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166 ((nothing,iu1_power4,iu2_power4)\
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167 |(nothing,iu2_power4,iu2_power4)\
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168 |(nothing,iu2_power4,iu1_power4))")
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169
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170 (define_insn_reservation "power4-store-update-indexed" 12
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171 (and (eq_attr "type" "store")
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172 (eq_attr "update" "yes")
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173 (eq_attr "indexed" "yes")
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174 (eq_attr "cpu" "power4"))
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175 "du1_power4+du2_power4+du3_power4+du4_power4,\
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176 iu1_power4,lsu2_power4+iu2_power4,iu2_power4")
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177
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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178 (define_insn_reservation "power4-fpstore" 12
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179 (and (eq_attr "type" "fpstore")
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180 (eq_attr "update" "no")
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181 (eq_attr "cpu" "power4"))
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182 "((du1_power4,lsu1_power4)\
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183 |(du2_power4,lsu2_power4)\
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184 |(du3_power4,lsu2_power4)\
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185 |(du4_power4,lsu1_power4)),\
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186 (fpu1_power4|fpu2_power4)")
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187
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188 (define_insn_reservation "power4-fpstore-update" 12
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189 (and (eq_attr "type" "fpstore")
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190 (eq_attr "update" "yes")
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191 (eq_attr "cpu" "power4"))
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192 "((du1_power4+du2_power4,lsu1_power4)\
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193 |(du2_power4+du3_power4,lsu2_power4)\
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194 |(du3_power4+du4_power4,lsu2_power4))\
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195 +(nothing,(iu1_power4|iu2_power4),(fpu1_power4|fpu2_power4))")
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196
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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197 (define_insn_reservation "power4-vecstore" 12
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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198 (and (eq_attr "type" "vecstore")
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199 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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200 "(du1_power4,lsu1_power4,vec_power4)\
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201 |(du2_power4,lsu2_power4,vec_power4)\
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202 |(du3_power4,lsu2_power4,vec_power4)\
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203 |(du4_power4,lsu1_power4,vec_power4)")
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204
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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205 (define_insn_reservation "power4-llsc" 11
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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206 (and (eq_attr "type" "load_l,store_c,sync")
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207 (eq_attr "cpu" "power4"))
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208 "du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4")
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209
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210
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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211 ; Integer latency is 2 cycles
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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212 (define_insn_reservation "power4-integer" 2
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213 (and (ior (eq_attr "type" "integer,trap,cntlz,isel")
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214 (and (eq_attr "type" "add,logical,shift,exts")
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215 (eq_attr "dot" "no"))
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216 (and (eq_attr "type" "insert")
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217 (eq_attr "size" "64")))
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218 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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219 "iq_power4")
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220
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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221 (define_insn_reservation "power4-two" 2
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222 (and (eq_attr "type" "two")
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223 (eq_attr "cpu" "power4"))
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224 "((du1_power4+du2_power4)\
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225 |(du2_power4+du3_power4)\
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226 |(du3_power4+du4_power4)\
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227 |(du4_power4+du1_power4)),\
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228 ((iu1_power4,nothing,iu2_power4)\
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229 |(iu2_power4,nothing,iu2_power4)\
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230 |(iu2_power4,nothing,iu1_power4)\
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231 |(iu1_power4,nothing,iu1_power4))")
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232
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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233 (define_insn_reservation "power4-three" 2
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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234 (and (eq_attr "type" "three")
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235 (eq_attr "cpu" "power4"))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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236 "(du1_power4+du2_power4+du3_power4|du2_power4+du3_power4+du4_power4\
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237 |du3_power4+du4_power4+du1_power4|du4_power4+du1_power4+du2_power4),\
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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238 ((iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\
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239 |(iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\
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240 |(iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\
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241 |(iu1_power4,nothing,iu1_power4,nothing,iu2_power4))")
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242
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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243 (define_insn_reservation "power4-insert" 4
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kono
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244 (and (eq_attr "type" "insert")
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245 (eq_attr "size" "32")
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246 (eq_attr "cpu" "power4"))
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247 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
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248 ((iu1_power4,nothing,iu2_power4)\
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249 |(iu2_power4,nothing,iu2_power4)\
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250 |(iu2_power4,nothing,iu1_power4))")
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251
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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252 (define_insn_reservation "power4-cmp" 3
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kono
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253 (and (ior (eq_attr "type" "cmp")
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254 (and (eq_attr "type" "add,logical")
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255 (eq_attr "dot" "yes")))
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256 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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257 "iq_power4")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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258
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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259 (define_insn_reservation "power4-compare" 2
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kono
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260 (and (eq_attr "type" "shift,exts")
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261 (eq_attr "dot" "yes")
0
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262 (eq_attr "cpu" "power4"))
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263 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
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264 ((iu1_power4,iu2_power4)\
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265 |(iu2_power4,iu2_power4)\
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266 |(iu2_power4,iu1_power4))")
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267
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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268 (define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
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269
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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270 (define_insn_reservation "power4-lmul-cmp" 7
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kono
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271 (and (eq_attr "type" "mul")
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272 (eq_attr "dot" "yes")
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273 (eq_attr "size" "64")
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274 (eq_attr "cpu" "power4"))
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275 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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276 ((iu1_power4*6,iu2_power4)\
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277 |(iu2_power4*6,iu2_power4)\
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278 |(iu2_power4*6,iu1_power4))")
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279
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280 (define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
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281
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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282 (define_insn_reservation "power4-imul-cmp" 5
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283 (and (eq_attr "type" "mul")
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284 (eq_attr "dot" "yes")
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285 (eq_attr "size" "32")
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286 (eq_attr "cpu" "power4"))
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287 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
288 ((iu1_power4*4,iu2_power4)\
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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289 |(iu2_power4*4,iu2_power4)\
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
290 |(iu2_power4*4,iu1_power4))")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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291
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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292 (define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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293
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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294 (define_insn_reservation "power4-lmul" 7
111
kono
parents: 55
diff changeset
295 (and (eq_attr "type" "mul")
kono
parents: 55
diff changeset
296 (eq_attr "dot" "no")
kono
parents: 55
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297 (eq_attr "size" "64")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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298 (eq_attr "cpu" "power4"))
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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299 "(du1_power4|du2_power4|du3_power4|du4_power4),\
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
300 (iu1_power4*6|iu2_power4*6)")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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301
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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302 (define_insn_reservation "power4-imul" 5
111
kono
parents: 55
diff changeset
303 (and (eq_attr "type" "mul")
kono
parents: 55
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304 (eq_attr "dot" "no")
kono
parents: 55
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305 (eq_attr "size" "32")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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306 (eq_attr "cpu" "power4"))
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
307 "(du1_power4|du2_power4|du3_power4|du4_power4),\
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
308 (iu1_power4*4|iu2_power4*4)")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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309
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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310 (define_insn_reservation "power4-imul3" 4
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kono
parents: 55
diff changeset
311 (and (eq_attr "type" "mul")
kono
parents: 55
diff changeset
312 (eq_attr "size" "8,16")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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313 (eq_attr "cpu" "power4"))
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
314 "(du1_power4|du2_power4|du3_power4|du4_power4),\
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
315 (iu1_power4*3|iu2_power4*3)")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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316
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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317
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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318 ; SPR move only executes in first IU.
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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319 ; Integer division only executes in second IU.
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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320 (define_insn_reservation "power4-idiv" 36
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kono
parents: 55
diff changeset
321 (and (eq_attr "type" "div")
kono
parents: 55
diff changeset
322 (eq_attr "size" "32")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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323 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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324 "du1_power4+du2_power4,iu2_power4*35")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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325
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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326 (define_insn_reservation "power4-ldiv" 68
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kono
parents: 55
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327 (and (eq_attr "type" "div")
kono
parents: 55
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328 (eq_attr "size" "64")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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329 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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330 "du1_power4+du2_power4,iu2_power4*67")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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331
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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332
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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333 (define_insn_reservation "power4-mtjmpr" 3
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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334 (and (eq_attr "type" "mtjmpr,mfjmpr")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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335 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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336 "du1_power4,bpu_power4")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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337
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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338
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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339 ; Branches take dispatch Slot 4. The presence_sets prevent other insn from
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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340 ; grabbing previous dispatch slots once this is assigned.
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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341 (define_insn_reservation "power4-branch" 2
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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342 (and (eq_attr "type" "jmpreg,branch")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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343 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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344 "(du5_power4\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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345 |du4_power4+du5_power4\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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346 |du3_power4+du4_power4+du5_power4\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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347 |du2_power4+du3_power4+du4_power4+du5_power4\
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348 |du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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349
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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350
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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351 ; Condition Register logical ops are split if non-destructive (RT != RB)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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352 (define_insn_reservation "power4-crlogical" 2
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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353 (and (eq_attr "type" "cr_logical")
131
84e7813d76e9 gcc-8.2
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diff changeset
354 (eq_attr "cr_logical_3op" "no")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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355 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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356 "du1_power4,cru_power4")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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357
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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358 (define_insn_reservation "power4-delayedcr" 4
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359 (and (eq_attr "type" "cr_logical")
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diff changeset
360 (eq_attr "cr_logical_3op" "yes")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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361 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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362 "du1_power4+du2_power4,cru_power4,cru_power4")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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363
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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364 ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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365 (define_insn_reservation "power4-mfcr" 6
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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366 (and (eq_attr "type" "mfcr")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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367 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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368 "du1_power4+du2_power4+du3_power4+du4_power4,\
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369 du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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370 cru_power4,cru_power4,cru_power4")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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371
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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372 ; mfcrf (1 field)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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373 (define_insn_reservation "power4-mfcrf" 3
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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374 (and (eq_attr "type" "mfcrf")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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375 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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376 "du1_power4,cru_power4")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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377
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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378 ; mtcrf (1 field)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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379 (define_insn_reservation "power4-mtcr" 4
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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380 (and (eq_attr "type" "mtcr")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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381 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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382 "du1_power4,iu1_power4")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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383
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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384 ; Basic FP latency is 6 cycles
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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385 (define_insn_reservation "power4-fp" 6
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kono
parents: 55
diff changeset
386 (and (eq_attr "type" "fp,fpsimple,dmul")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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387 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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388 "fpq_power4")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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389
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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390 (define_insn_reservation "power4-fpcompare" 5
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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391 (and (eq_attr "type" "fpcompare")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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392 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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393 "fpq_power4")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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394
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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395 (define_insn_reservation "power4-sdiv" 33
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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396 (and (eq_attr "type" "sdiv,ddiv")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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397 (eq_attr "cpu" "power4"))
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parents: 0
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398 "(du1_power4|du2_power4|du3_power4|du4_power4),\
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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399 (fpu1_power4*28|fpu2_power4*28)")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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400
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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401 (define_insn_reservation "power4-sqrt" 40
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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402 (and (eq_attr "type" "ssqrt,dsqrt")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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403 (eq_attr "cpu" "power4"))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
404 "(du1_power4|du2_power4|du3_power4|du4_power4),\
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
405 (fpu1_power4*35|fpu2_power4*35)")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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406
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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407 (define_insn_reservation "power4-isync" 2
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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408 (and (eq_attr "type" "isync")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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409 (eq_attr "cpu" "power4"))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
410 "du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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411
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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412
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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413 ; VMX
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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414 (define_insn_reservation "power4-vecsimple" 2
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kono
parents: 55
diff changeset
415 (and (eq_attr "type" "vecsimple,veclogical,vecmove")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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416 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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417 "vq_power4")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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418
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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419 (define_insn_reservation "power4-veccomplex" 5
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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420 (and (eq_attr "type" "veccomplex")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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421 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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422 "vq_power4")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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423
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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424 ; vecfp compare
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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425 (define_insn_reservation "power4-veccmp" 8
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kono
parents: 55
diff changeset
426 (and (eq_attr "type" "veccmp,veccmpfx")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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427 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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428 "vq_power4")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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429
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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430 (define_insn_reservation "power4-vecfloat" 8
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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431 (and (eq_attr "type" "vecfloat")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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432 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
433 "vq_power4")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
434
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
435 (define_insn_reservation "power4-vecperm" 2
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
436 (and (eq_attr "type" "vecperm")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
437 (eq_attr "cpu" "power4"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
438 "vpq_power4")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
439
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
440 (define_bypass 4 "power4-vecload" "power4-vecperm")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
441
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
442 (define_bypass 3 "power4-vecsimple" "power4-vecperm")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
443 (define_bypass 6 "power4-veccomplex" "power4-vecperm")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
444 (define_bypass 3 "power4-vecperm"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
445 "power4-vecsimple,power4-veccomplex,power4-vecfloat")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
446 (define_bypass 9 "power4-vecfloat" "power4-vecperm")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
447
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
448 (define_bypass 5 "power4-vecsimple,power4-veccomplex"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
449 "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
450
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
451 (define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
452 (define_bypass 7 "power4-veccomplex" "power4-vecstore")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
453 (define_bypass 10 "power4-vecfloat" "power4-vecstore")