annotate gcc/config/s390/subst.md @ 131:84e7813d76e9

gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
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2 ;; Subst patterns.
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84e7813d76e9 gcc-8.2
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3 ;; Copyright (C) 2016-2018 Free Software Foundation, Inc.
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4 ;; Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
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5
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6 ;; This file is part of GCC.
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7
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8 ;; GCC is free software; you can redistribute it and/or modify it under
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9 ;; the terms of the GNU General Public License as published by the Free
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10 ;; Software Foundation; either version 3, or (at your option) any later
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11 ;; version.
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12
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13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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14 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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15 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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16 ;; for more details.
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17
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 (define_code_iterator SUBST [rotate ashift lshiftrt ashiftrt])
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23 (define_mode_iterator DSI_VI [SI DI V2QI V4QI V8QI V16QI V2HI V4HI V8HI V2SI V4SI V2DI])
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24
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25 ; This expands an register/immediate operand to a register+immediate
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26 ; operand to draw advantage of the address style operand format
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27 ; providing a addition for free.
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28 (define_subst "addr_style_op_subst"
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29 [(set (match_operand:DSI_VI 0 "" "")
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30 (SUBST:DSI_VI (match_operand:DSI_VI 1 "" "")
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31 (match_operand:SI 2 "" "")))]
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32 ""
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33 [(set (match_dup 0)
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34 (SUBST:DSI_VI (match_dup 1)
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35 (plus:SI (match_operand:SI 2 "register_operand" "a")
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36 (match_operand 3 "const_int_operand" "n"))))])
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37
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38 ; Use this in the insn name.
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39 (define_subst_attr "addr_style_op" "addr_style_op_subst" "" "_plus")
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40
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41 ; In the subst pattern the additional const int operand will be used
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42 ; as displacement. In the normal version %Y is able to print the
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43 ; operand either as displacement or as base register.
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44 (define_subst_attr "addr_style_op_ops" "addr_style_op_subst" "%Y2" "%Y3(%2)")
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45
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46
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47 ; This substitution adds an explicit AND operation to the second
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48 ; operand. This way previous operations on the now masked out bits
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49 ; might get optimized away.
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50 (define_subst "masked_op_subst"
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51 [(set (match_operand:DSI 0 "" "")
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52 (SUBST:DSI (match_operand:DSI 1 "" "")
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53 (match_operand:SI 2 "" "")))]
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54 ""
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55 [(set (match_dup 0)
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56 (SUBST:DSI (match_dup 1)
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57 (and:SI (match_dup 2)
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58 (match_operand:SI 3 "const_int_6bitset_operand" "jm6"))))])
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59
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60 ; Use this in the insn name.
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61 (define_subst_attr "masked_op" "masked_op_subst" "" "_and")
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62
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63
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64
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65 ; This is like the addr_style_op substitution above but with a CC clobber.
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66 (define_subst "addr_style_op_cc_subst"
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67 [(set (match_operand:DSI 0 "" "")
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68 (ashiftrt:DSI (match_operand:DSI 1 "" "")
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69 (match_operand:SI 2 "" "")))
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70 (clobber (reg:CC CC_REGNUM))]
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71 "REG_P (operands[2])"
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72 [(set (match_dup 0)
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73 (ashiftrt:DSI (match_dup 1)
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74 (plus:SI (match_dup 2)
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75 (match_operand 3 "const_int_operand" "n"))))
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76 (clobber (reg:CC CC_REGNUM))])
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77
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78 (define_subst_attr "addr_style_op_cc" "addr_style_op_cc_subst" "" "_plus")
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79 (define_subst_attr "addr_style_op_cc_ops" "addr_style_op_cc_subst" "%Y2" "%Y3(%2)")
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80
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81
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82 ; This is like the masked_op substitution but with a CC clobber.
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83 (define_subst "masked_op_cc_subst"
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84 [(set (match_operand:DSI 0 "" "")
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85 (ashiftrt:DSI (match_operand:DSI 1 "" "")
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86 (match_operand:SI 2 "" "")))
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87 (clobber (reg:CC CC_REGNUM))]
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88 ""
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89 [(set (match_dup 0)
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90 (ashiftrt:DSI (match_dup 1)
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91 (and:SI (match_dup 2)
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92 (match_operand:SI 3 "const_int_6bitset_operand" ""))))
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93 (clobber (reg:CC CC_REGNUM))])
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94 (define_subst_attr "masked_op_cc" "masked_op_cc_subst" "" "_and")
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95
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96
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97 ; This adds an explicit CC reg set to an operation while keeping the
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98 ; set for the operation result as well.
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99 (define_subst "setcc_subst"
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100 [(set (match_operand:DSI 0 "" "")
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101 (match_operand:DSI 1 "" ""))
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102 (clobber (reg:CC CC_REGNUM))]
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103 "s390_match_ccmode(insn, CCSmode)"
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104 [(set (reg CC_REGNUM)
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105 (compare (match_dup 1) (const_int 0)))
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106 (set (match_dup 0) (match_dup 1))])
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107
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108 ; Use this in the insn name.
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109 (define_subst_attr "setcc" "setcc_subst" "" "_cc")
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110
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111 ; This adds an explicit CC reg set to an operation while dropping the
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112 ; result of the operation.
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113 (define_subst "cconly_subst"
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114 [(set (match_operand:DSI 0 "" "")
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115 (match_operand:DSI 1 "" ""))
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116 (clobber (reg:CC CC_REGNUM))]
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117 "s390_match_ccmode(insn, CCSmode)"
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118 [(set (reg CC_REGNUM)
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119 (compare (match_dup 1) (const_int 0)))
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120 (clobber (match_scratch:DSI 0 "=d,d"))])
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121
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122 (define_subst_attr "cconly" "cconly_subst" "" "_cconly")
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123
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124
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125 ; Does transformations to switch between patterns unsing risbg +
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126 ; clobber CC (z10) and risbgn without clobber (zEC12).
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127 (define_subst "clobbercc_or_nocc_subst"
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128 [(set (match_operand 0 "" "") (match_operand 1 "" ""))]
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129 ""
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130 [(set (match_dup 0) (match_dup 1))
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131 (clobber (reg:CC CC_REGNUM))])
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132
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133 ; Use this in the insn name to add the target suffix.
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134 (define_subst_attr "clobbercc_or_nocc" "clobbercc_or_nocc_subst"
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135 "_nocc" "_clobbercc")
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136
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137 ; Use this in the condition.
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138 (define_subst_attr "z10_or_zEC12_cond" "clobbercc_or_nocc_subst"
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139 "TARGET_ZEC12" "TARGET_Z10 && ! TARGET_ZEC12")
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140
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141 ; Use this instead of the risbg instruction.
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142 (define_subst_attr "risbg_n" "clobbercc_or_nocc_subst"
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143 "risbgn" "risbg")