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1 ;; Scheduling description for Niagara-7
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2 ;; Copyright (C) 2016-2018 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_automaton "niagara7_0")
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21
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22 ;; The S4 core has a dual-issue queue. This queue is divided into two
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23 ;; slots. One instruction can be issued each cycle to each slot, and
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24 ;; up to 2 instructions are committed each cycle. Each slot serves
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25 ;; several execution units, as depicted below:
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26 ;;
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27 ;;
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28 ;; m7_slot0 - Integer unit.
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29 ;; - Load/Store unit.
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30 ;; === QUEUE ==>
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31 ;;
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32 ;; m7_slot1 - Integer unit.
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33 ;; - Branch unit.
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34 ;; - Floating-point and graphics unit.
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35 ;; - 3-cycles crypto unit.
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36
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37 (define_cpu_unit "n7_slot0,n7_slot1" "niagara7_0")
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38
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39 ;; Some instructions stall the pipeline and avoid any other
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40 ;; instruction to be issued in the same cycle. We assume the same for
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41 ;; multi-instruction insns.
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42
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43 (define_reservation "n7_single_issue" "n7_slot0 + n7_slot1")
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44
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45 (define_insn_reservation "n7_single" 1
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46 (and (eq_attr "cpu" "niagara7")
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47 (eq_attr "type" "multi,savew,flushw,trap"))
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48 "n7_single_issue")
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49
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50 ;; Most of the instructions executing in the integer unit have a
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51 ;; latency of 1.
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52
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53 (define_insn_reservation "n7_integer" 1
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54 (and (eq_attr "cpu" "niagara7")
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55 (eq_attr "type" "ialu,ialuX,shift,cmove,compare"))
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56 "(n7_slot0 | n7_slot1)")
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57
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58 ;; Flushing the instruction memory takes 27 cycles.
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59
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60 (define_insn_reservation "n7_iflush" 27
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61 (and (eq_attr "cpu" "niagara7")
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62 (eq_attr "type" "iflush"))
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63 "(n7_slot0 | n7_slot1), nothing*26")
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64
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65 ;; The integer multiplication instructions have a latency of 12 cycles
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66 ;; and execute in the integer unit.
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67 ;;
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68 ;; Likewise for array*, edge* and pdistn instructions.
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69
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70 (define_insn_reservation "n7_imul" 12
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71 (and (eq_attr "cpu" "niagara7")
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72 (eq_attr "type" "imul,array,edge,edgen,pdistn"))
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73 "(n7_slot0 | n7_slot1), nothing*11")
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74
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75 ;; The integer division instructions have a latency of 35 cycles and
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76 ;; execute in the integer unit.
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77
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78 (define_insn_reservation "n7_idiv" 35
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79 (and (eq_attr "cpu" "niagara7")
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80 (eq_attr "type" "idiv"))
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81 "(n7_slot0 | n7_slot1), nothing*34")
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82
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83 ;; Both integer and floating-point load instructions have a latency of
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84 ;; 5 cycles, and execute in the slot0.
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85 ;;
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86 ;; The prefetch instruction also executes in the load/store unit, but
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87 ;; its latency is only 1 cycle.
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88
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89 (define_insn_reservation "n7_load" 5
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90 (and (eq_attr "cpu" "niagara7")
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91 (ior (eq_attr "type" "fpload,sload")
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92 (and (eq_attr "type" "load")
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93 (eq_attr "subtype" "regular"))))
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94 "n7_slot0, nothing*4")
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95
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96 (define_insn_reservation "n7_prefetch" 1
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97 (and (eq_attr "cpu" "niagara7")
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98 (eq_attr "type" "load")
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99 (eq_attr "subtype" "prefetch"))
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100 "n7_slot0")
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101
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102 ;; Both integer and floating-point store instructions have a latency
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103 ;; of 1 cycle, and execute in the load/store unit in slot0.
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104
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105 (define_insn_reservation "n7_store" 1
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106 (and (eq_attr "cpu" "niagara7")
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107 (eq_attr "type" "store,fpstore"))
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108 "n7_slot0")
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109
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110 ;; Control-transfer instructions execute in the Branch Unit in the
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111 ;; slot1.
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112
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113 (define_insn_reservation "n7_cti" 1
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114 (and (eq_attr "cpu" "niagara7")
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115 (eq_attr "type" "cbcond,uncond_cbcond,branch,call,sibcall,call_no_delay_slot,uncond_branch,return"))
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116 "n7_slot1")
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117
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118 ;; Many instructions executing in the Floating-point and Graphics unit
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119 ;; in the slot1 feature a latency of 11 cycles.
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120
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121 (define_insn_reservation "n7_fp" 11
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122 (and (eq_attr "cpu" "niagara7")
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123 (ior (eq_attr "type" "fpmove,fpcmove,fpcrmove,fp,fpcmp,fpmul,fgm_pack,fgm_mul,pdist")
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124 (and (eq_attr "type" "fga")
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125 (eq_attr "subtype" "fpu,maxmin"))))
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126 "n7_slot1, nothing*10")
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127
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128 ;; Floating-point division and floating-point square-root instructions
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129 ;; have high latencies. They execute in the floating-point and
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130 ;; graphics unit in the slot1.
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131
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132
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133 (define_insn_reservation "n7_fpdivs" 24
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134 (and (eq_attr "cpu" "niagara7")
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135 (eq_attr "type" "fpdivs,fpsqrts"))
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136 "n7_slot1, nothing*23")
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137
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138 (define_insn_reservation "n7_fpdivd" 37
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139 (and (eq_attr "cpu" "niagara7")
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140 (eq_attr "type" "fpdivd,fpsqrtd"))
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141 "n7_slot1, nothing*36")
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142
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143 ;; SIMD VIS instructions executing in the Floating-point and graphics
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144 ;; unit (FPG) in slot1 usually have a latency of either 11 or 12
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145 ;; cycles.
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146 ;;
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147 ;; However, the latency for many instructions is only 3 cycles if the
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148 ;; consumer can also be executed in 3 cycles. We model this with a
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149 ;; bypass. In these cases the instructions are executed in the
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150 ;; 3-cycle crypto unit which also serves slot1.
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151
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152 (define_insn_reservation "n7_vis_11cycles" 11
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153 (and (eq_attr "cpu" "niagara7")
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154 (ior (and (eq_attr "type" "fga")
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155 (eq_attr "subtype" "addsub64,other"))
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156 (and (eq_attr "type" "vismv")
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157 (eq_attr "subtype" "double,single"))
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158 (and (eq_attr "type" "visl")
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159 (eq_attr "subtype" "double,single"))))
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160 "n7_slot1, nothing*10")
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161
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162 (define_insn_reservation "n7_vis_12cycles" 12
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163 (and (eq_attr "cpu" "niagara7")
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164 (ior (eq_attr "type" "bmask,viscmp")
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165 (and (eq_attr "type" "fga")
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166 (eq_attr "subtype" "cmask"))
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167 (and (eq_attr "type" "vismv")
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168 (eq_attr "subtype" "movstouw"))))
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169 "n7_slot1, nothing*11")
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170
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171 (define_bypass 3 "n7_vis_*" "n7_vis_*")
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172
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173 ;; Some other VIS instructions have a latency of 12 cycles, and won't
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174 ;; be executed in the 3-cycle crypto pipe.
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175
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176 (define_insn_reservation "n7_lzd" 12
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177 (and (eq_attr "cpu" "niagara7")
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178 (ior (eq_attr "type" "lzd,")
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179 (and (eq_attr "type" "gsr")
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180 (eq_attr "subtype" "alignaddr"))))
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181 "n7_slot1, nothing*11")
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182
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183 ;; A couple of VIS instructions feature very low latencies in the M7.
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184
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185 (define_insn_reservation "n7_single_vis" 1
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186 (and (eq_attr "cpu" "niagara7")
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187 (eq_attr "type" "vismv")
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188 (eq_attr "subtype" "movxtod"))
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189 "n7_slot1")
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190
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191 (define_insn_reservation "n7_double_vis" 2
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192 (and (eq_attr "cpu" "niagara7")
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193 (eq_attr "type" "vismv")
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194 (eq_attr "subtype" "movdtox"))
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195 "n7_slot1, nothing")
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196
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197 ;; Reading and writing to the gsr register takes a high number of
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198 ;; cycles that is not documented in the PRM. Let's use the same value
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199 ;; than the M8.
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200
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201 (define_insn_reservation "n7_gsr_reg" 70
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202 (and (eq_attr "cpu" "niagara7")
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203 (eq_attr "type" "gsr")
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204 (eq_attr "subtype" "reg"))
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205 "n7_slot1, nothing*70")
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