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131
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1 /* { dg-do run { target aarch64_sve_hw } } */
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2 /* { dg-options "-O3 -fopenmp-simd -fno-omit-frame-pointer" } */
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3
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4 /* Invoke X (P##n) for n in [0, 7]. */
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5 #define REPEAT8(X, P) \
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6 X (P##0) X (P##1) X (P##2) X (P##3) X (P##4) X (P##5) X (P##6) X (P##7)
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7
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8 /* Invoke X (n) for all octal n in [0, 39]. */
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9 #define REPEAT40(X) \
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10 REPEAT8 (X, 0) REPEAT8 (X, 1) REPEAT8 (X, 2) REPEAT8 (X, 3) REPEAT8 (X, 4)
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11
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12 volatile int testi;
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13
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14 /* Throw to f3. */
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15 void __attribute__ ((weak))
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16 f1 (int x[40][100], int *y)
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17 {
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18 /* A wild write to x and y. */
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19 asm volatile ("" ::: "memory");
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20 if (y[testi] == x[testi][testi])
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21 throw 100;
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22 }
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23
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24 /* Expect vector work to be done, with spilling of vector registers. */
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25 void __attribute__ ((weak))
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26 f2 (int x[40][100], int *y)
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27 {
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28 /* Try to force some spilling. */
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29 #define DECLARE(N) int y##N = y[N];
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30 REPEAT40 (DECLARE);
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31 for (int j = 0; j < 20; ++j)
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32 {
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33 f1 (x, y);
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34 #pragma omp simd
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35 for (int i = 0; i < 100; ++i)
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36 {
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37 #define INC(N) x[N][i] += y##N;
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38 REPEAT40 (INC);
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39 }
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40 }
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41 }
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42
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43 /* Catch an exception thrown from f1, via f2. */
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44 void __attribute__ ((weak))
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45 f3 (int x[40][100], int *y, int *z)
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46 {
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47 volatile int extra = 111;
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48 try
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49 {
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50 f2 (x, y);
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51 }
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52 catch (int val)
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53 {
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54 *z = val + extra;
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55 }
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56 }
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57
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58 static int x[40][100];
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59 static int y[40];
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60 static int z;
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61
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62 int
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63 main (void)
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64 {
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65 f3 (x, y, &z);
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66 if (z != 211)
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67 __builtin_abort ();
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68 return 0;
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69 }
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