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1 ;; GCC machine description for Alpha synchronization instructions.
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2 ;; Copyright (C) 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_code_iterator FETCHOP [plus minus ior xor and])
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21 (define_code_attr fetchop_name
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22 [(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
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23 (define_code_attr fetchop_pred
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24 [(plus "add_operand") (minus "reg_or_8bit_operand")
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25 (ior "or_operand") (xor "or_operand") (and "and_operand")])
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26 (define_code_attr fetchop_constr
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27 [(plus "rKL") (minus "rI") (ior "rIN") (xor "rIN") (and "riNHM")])
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28
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29
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30 (define_expand "memory_barrier"
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31 [(set (match_dup 0)
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32 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
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33 ""
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34 {
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35 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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36 MEM_VOLATILE_P (operands[0]) = 1;
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37 })
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38
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39 (define_insn "*memory_barrier"
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40 [(set (match_operand:BLK 0 "" "")
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41 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
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42 ""
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43 "mb"
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44 [(set_attr "type" "mb")])
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45
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46 (define_insn "load_locked_<mode>"
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47 [(set (match_operand:I48MODE 0 "register_operand" "=r")
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48 (unspec_volatile:I48MODE
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49 [(match_operand:I48MODE 1 "memory_operand" "m")]
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50 UNSPECV_LL))]
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51 ""
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52 "ld<modesuffix>_l %0,%1"
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53 [(set_attr "type" "ld_l")])
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54
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55 (define_insn "store_conditional_<mode>"
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56 [(set (match_operand:DI 0 "register_operand" "=r")
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57 (unspec_volatile:DI [(const_int 0)] UNSPECV_SC))
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58 (set (match_operand:I48MODE 1 "memory_operand" "=m")
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59 (match_operand:I48MODE 2 "reg_or_0_operand" "0"))]
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60 ""
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61 "st<modesuffix>_c %0,%1"
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62 [(set_attr "type" "st_c")])
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63
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64 ;; The Alpha Architecture Handbook says that it is UNPREDICTABLE whether
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65 ;; the lock is cleared by a TAKEN branch. This means that we can not
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66 ;; expand a ll/sc sequence until after the final basic-block reordering pass.
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0
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67
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68 (define_insn_and_split "sync_<fetchop_name><mode>"
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69 [(set (match_operand:I48MODE 0 "memory_operand" "+m")
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70 (unspec:I48MODE
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71 [(FETCHOP:I48MODE (match_dup 0)
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72 (match_operand:I48MODE 1 "<fetchop_pred>" "<fetchop_constr>"))]
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73 UNSPEC_ATOMIC))
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74 (clobber (match_scratch:I48MODE 2 "=&r"))]
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75 ""
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76 "#"
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36
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77 "epilogue_completed"
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78 [(const_int 0)]
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79 {
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80 alpha_split_atomic_op (<CODE>, operands[0], operands[1],
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81 NULL, NULL, operands[2]);
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82 DONE;
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83 }
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84 [(set_attr "type" "multi")])
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85
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86 (define_insn_and_split "sync_nand<mode>"
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87 [(set (match_operand:I48MODE 0 "memory_operand" "+m")
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88 (unspec:I48MODE
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89 [(not:I48MODE
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90 (and:I48MODE (match_dup 0)
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91 (match_operand:I48MODE 1 "register_operand" "r")))]
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92 UNSPEC_ATOMIC))
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93 (clobber (match_scratch:I48MODE 2 "=&r"))]
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94 ""
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95 "#"
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96 "epilogue_completed"
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0
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97 [(const_int 0)]
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98 {
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99 alpha_split_atomic_op (NOT, operands[0], operands[1],
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100 NULL, NULL, operands[2]);
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101 DONE;
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102 }
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103 [(set_attr "type" "multi")])
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104
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105 (define_insn_and_split "sync_old_<fetchop_name><mode>"
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106 [(set (match_operand:I48MODE 0 "register_operand" "=&r")
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107 (match_operand:I48MODE 1 "memory_operand" "+m"))
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108 (set (match_dup 1)
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109 (unspec:I48MODE
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110 [(FETCHOP:I48MODE (match_dup 1)
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111 (match_operand:I48MODE 2 "<fetchop_pred>" "<fetchop_constr>"))]
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112 UNSPEC_ATOMIC))
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113 (clobber (match_scratch:I48MODE 3 "=&r"))]
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114 ""
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115 "#"
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116 "epilogue_completed"
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117 [(const_int 0)]
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118 {
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119 alpha_split_atomic_op (<CODE>, operands[1], operands[2],
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120 operands[0], NULL, operands[3]);
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121 DONE;
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122 }
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123 [(set_attr "type" "multi")])
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124
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125 (define_insn_and_split "sync_old_nand<mode>"
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126 [(set (match_operand:I48MODE 0 "register_operand" "=&r")
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127 (match_operand:I48MODE 1 "memory_operand" "+m"))
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128 (set (match_dup 1)
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129 (unspec:I48MODE
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130 [(not:I48MODE
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131 (and:I48MODE (match_dup 1)
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132 (match_operand:I48MODE 2 "register_operand" "r")))]
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133 UNSPEC_ATOMIC))
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134 (clobber (match_scratch:I48MODE 3 "=&r"))]
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135 ""
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136 "#"
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137 "epilogue_completed"
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0
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138 [(const_int 0)]
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139 {
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140 alpha_split_atomic_op (NOT, operands[1], operands[2],
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141 operands[0], NULL, operands[3]);
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142 DONE;
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143 }
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144 [(set_attr "type" "multi")])
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145
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146 (define_insn_and_split "sync_new_<fetchop_name><mode>"
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147 [(set (match_operand:I48MODE 0 "register_operand" "=&r")
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148 (FETCHOP:I48MODE
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149 (match_operand:I48MODE 1 "memory_operand" "+m")
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150 (match_operand:I48MODE 2 "<fetchop_pred>" "<fetchop_constr>")))
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151 (set (match_dup 1)
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152 (unspec:I48MODE
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153 [(FETCHOP:I48MODE (match_dup 1) (match_dup 2))]
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154 UNSPEC_ATOMIC))
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155 (clobber (match_scratch:I48MODE 3 "=&r"))]
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156 ""
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157 "#"
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158 "epilogue_completed"
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159 [(const_int 0)]
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160 {
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161 alpha_split_atomic_op (<CODE>, operands[1], operands[2],
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162 NULL, operands[0], operands[3]);
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163 DONE;
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164 }
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165 [(set_attr "type" "multi")])
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166
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167 (define_insn_and_split "sync_new_nand<mode>"
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168 [(set (match_operand:I48MODE 0 "register_operand" "=&r")
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169 (not:I48MODE
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170 (and:I48MODE (match_operand:I48MODE 1 "memory_operand" "+m")
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171 (match_operand:I48MODE 2 "register_operand" "r"))))
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172 (set (match_dup 1)
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173 (unspec:I48MODE
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174 [(not:I48MODE (and:I48MODE (match_dup 1) (match_dup 2)))]
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175 UNSPEC_ATOMIC))
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176 (clobber (match_scratch:I48MODE 3 "=&r"))]
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177 ""
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178 "#"
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179 "epilogue_completed"
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180 [(const_int 0)]
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181 {
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182 alpha_split_atomic_op (NOT, operands[1], operands[2],
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183 NULL, operands[0], operands[3]);
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184 DONE;
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185 }
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186 [(set_attr "type" "multi")])
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187
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188 (define_expand "sync_compare_and_swap<mode>"
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189 [(match_operand:I12MODE 0 "register_operand" "")
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190 (match_operand:I12MODE 1 "memory_operand" "")
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191 (match_operand:I12MODE 2 "register_operand" "")
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192 (match_operand:I12MODE 3 "add_operand" "")]
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193 ""
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194 {
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195 alpha_expand_compare_and_swap_12 (operands[0], operands[1],
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196 operands[2], operands[3]);
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197 DONE;
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198 })
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199
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200 (define_insn_and_split "sync_compare_and_swap<mode>_1"
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201 [(set (match_operand:DI 0 "register_operand" "=&r,&r")
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202 (zero_extend:DI
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203 (mem:I12MODE (match_operand:DI 1 "register_operand" "r,r"))))
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204 (set (mem:I12MODE (match_dup 1))
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205 (unspec:I12MODE
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206 [(match_operand:DI 2 "reg_or_8bit_operand" "J,rI")
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207 (match_operand:DI 3 "register_operand" "r,r")
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208 (match_operand:DI 4 "register_operand" "r,r")]
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209 UNSPEC_CMPXCHG))
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210 (clobber (match_scratch:DI 5 "=&r,&r"))
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211 (clobber (match_scratch:DI 6 "=X,&r"))]
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212 ""
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213 "#"
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214 "epilogue_completed"
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0
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215 [(const_int 0)]
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216 {
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217 alpha_split_compare_and_swap_12 (<MODE>mode, operands[0], operands[1],
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218 operands[2], operands[3], operands[4],
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219 operands[5], operands[6]);
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220 DONE;
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221 }
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222 [(set_attr "type" "multi")])
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223
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224 (define_expand "sync_compare_and_swap<mode>"
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225 [(parallel
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226 [(set (match_operand:I48MODE 0 "register_operand" "")
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227 (match_operand:I48MODE 1 "memory_operand" ""))
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228 (set (match_dup 1)
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229 (unspec:I48MODE
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230 [(match_operand:I48MODE 2 "reg_or_8bit_operand" "")
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231 (match_operand:I48MODE 3 "add_operand" "rKL")]
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232 UNSPEC_CMPXCHG))
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233 (clobber (match_scratch:I48MODE 4 "=&r"))])]
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234 ""
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235 {
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236 if (<MODE>mode == SImode)
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237 operands[2] = convert_modes (DImode, SImode, operands[2], 0);
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238 })
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239
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240 (define_insn_and_split "*sync_compare_and_swap<mode>"
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241 [(set (match_operand:I48MODE 0 "register_operand" "=&r")
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242 (match_operand:I48MODE 1 "memory_operand" "+m"))
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243 (set (match_dup 1)
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244 (unspec:I48MODE
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245 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
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246 (match_operand:I48MODE 3 "add_operand" "rKL")]
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247 UNSPEC_CMPXCHG))
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248 (clobber (match_scratch:I48MODE 4 "=&r"))]
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249 ""
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250 "#"
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251 "epilogue_completed"
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252 [(const_int 0)]
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253 {
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254 alpha_split_compare_and_swap (operands[0], operands[1], operands[2],
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255 operands[3], operands[4]);
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256 DONE;
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257 }
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258 [(set_attr "type" "multi")])
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259
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260 (define_expand "sync_lock_test_and_set<mode>"
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261 [(match_operand:I12MODE 0 "register_operand" "")
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262 (match_operand:I12MODE 1 "memory_operand" "")
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263 (match_operand:I12MODE 2 "register_operand" "")]
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264 ""
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265 {
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266 alpha_expand_lock_test_and_set_12 (operands[0], operands[1], operands[2]);
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267 DONE;
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268 })
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269
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270 (define_insn_and_split "sync_lock_test_and_set<mode>_1"
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271 [(set (match_operand:DI 0 "register_operand" "=&r")
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272 (zero_extend:DI
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273 (mem:I12MODE (match_operand:DI 1 "register_operand" "r"))))
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274 (set (mem:I12MODE (match_dup 1))
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275 (unspec:I12MODE
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276 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
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277 (match_operand:DI 3 "register_operand" "r")]
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278 UNSPEC_XCHG))
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279 (clobber (match_scratch:DI 4 "=&r"))]
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280 ""
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281 "#"
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282 "epilogue_completed"
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283 [(const_int 0)]
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284 {
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285 alpha_split_lock_test_and_set_12 (<MODE>mode, operands[0], operands[1],
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286 operands[2], operands[3], operands[4]);
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287 DONE;
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288 }
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289 [(set_attr "type" "multi")])
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290
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291 (define_insn_and_split "sync_lock_test_and_set<mode>"
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292 [(set (match_operand:I48MODE 0 "register_operand" "=&r")
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293 (match_operand:I48MODE 1 "memory_operand" "+m"))
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294 (set (match_dup 1)
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295 (unspec:I48MODE
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296 [(match_operand:I48MODE 2 "add_operand" "rKL")]
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297 UNSPEC_XCHG))
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298 (clobber (match_scratch:I48MODE 3 "=&r"))]
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299 ""
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300 "#"
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301 "epilogue_completed"
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0
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302 [(const_int 0)]
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303 {
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304 alpha_split_lock_test_and_set (operands[0], operands[1],
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305 operands[2], operands[3]);
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306 DONE;
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307 }
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308 [(set_attr "type" "multi")])
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