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1 ;; Predicate definitions for ARM and Thumb
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2 ;; Copyright (C) 2004, 2007, 2008 Free Software Foundation, Inc.
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3 ;; Contributed by ARM Ltd.
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4
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_predicate "s_register_operand"
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22 (match_code "reg,subreg")
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23 {
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24 if (GET_CODE (op) == SUBREG)
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25 op = SUBREG_REG (op);
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26 /* We don't consider registers whose class is NO_REGS
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27 to be a register operand. */
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28 /* XXX might have to check for lo regs only for thumb ??? */
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29 return (GET_CODE (op) == REG
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30 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
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31 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
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32 })
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33
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34 ;; Any hard register.
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35 (define_predicate "arm_hard_register_operand"
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36 (match_code "reg")
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37 {
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38 return REGNO (op) < FIRST_PSEUDO_REGISTER;
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39 })
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40
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41 ;; A low register.
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42 (define_predicate "low_register_operand"
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43 (and (match_code "reg")
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44 (match_test "REGNO (op) <= LAST_LO_REGNUM")))
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45
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46 ;; A low register or const_int.
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47 (define_predicate "low_reg_or_int_operand"
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48 (ior (match_code "const_int")
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49 (match_operand 0 "low_register_operand")))
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50
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51 ;; Any core register, or any pseudo. */
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52 (define_predicate "arm_general_register_operand"
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53 (match_code "reg,subreg")
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54 {
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55 if (GET_CODE (op) == SUBREG)
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56 op = SUBREG_REG (op);
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57
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58 return (GET_CODE (op) == REG
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59 && (REGNO (op) <= LAST_ARM_REGNUM
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60 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
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61 })
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62
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63 (define_predicate "f_register_operand"
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64 (match_code "reg,subreg")
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65 {
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66 if (GET_CODE (op) == SUBREG)
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67 op = SUBREG_REG (op);
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68
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69 /* We don't consider registers whose class is NO_REGS
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70 to be a register operand. */
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71 return (GET_CODE (op) == REG
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72 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
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73 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
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74 })
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75
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76 ;; Reg, subreg(reg) or const_int.
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77 (define_predicate "reg_or_int_operand"
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78 (ior (match_code "const_int")
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79 (match_operand 0 "s_register_operand")))
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80
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81 (define_predicate "arm_immediate_operand"
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82 (and (match_code "const_int")
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83 (match_test "const_ok_for_arm (INTVAL (op))")))
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84
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85 (define_predicate "arm_neg_immediate_operand"
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86 (and (match_code "const_int")
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87 (match_test "const_ok_for_arm (-INTVAL (op))")))
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88
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89 (define_predicate "arm_not_immediate_operand"
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90 (and (match_code "const_int")
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91 (match_test "const_ok_for_arm (~INTVAL (op))")))
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92
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93 ;; Something valid on the RHS of an ARM data-processing instruction
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94 (define_predicate "arm_rhs_operand"
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95 (ior (match_operand 0 "s_register_operand")
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96 (match_operand 0 "arm_immediate_operand")))
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97
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98 (define_predicate "arm_rhsm_operand"
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99 (ior (match_operand 0 "arm_rhs_operand")
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100 (match_operand 0 "memory_operand")))
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101
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102 (define_predicate "arm_add_operand"
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103 (ior (match_operand 0 "arm_rhs_operand")
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104 (match_operand 0 "arm_neg_immediate_operand")))
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105
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106 (define_predicate "arm_addimm_operand"
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107 (ior (match_operand 0 "arm_immediate_operand")
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108 (match_operand 0 "arm_neg_immediate_operand")))
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109
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110 (define_predicate "arm_not_operand"
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111 (ior (match_operand 0 "arm_rhs_operand")
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112 (match_operand 0 "arm_not_immediate_operand")))
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113
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114 ;; True if the operand is a memory reference which contains an
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115 ;; offsettable address.
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116 (define_predicate "offsettable_memory_operand"
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117 (and (match_code "mem")
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118 (match_test
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119 "offsettable_address_p (reload_completed | reload_in_progress,
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120 mode, XEXP (op, 0))")))
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121
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122 ;; True if the operand is a memory operand that does not have an
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123 ;; automodified base register (and thus will not generate output reloads).
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124 (define_predicate "call_memory_operand"
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125 (and (match_code "mem")
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126 (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
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127 != RTX_AUTOINC")
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128 (match_operand 0 "memory_operand"))))
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129
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130 (define_predicate "arm_reload_memory_operand"
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131 (and (match_code "mem,reg,subreg")
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132 (match_test "(!CONSTANT_P (op)
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133 && (true_regnum(op) == -1
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134 || (GET_CODE (op) == REG
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135 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
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136
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137 ;; True for valid operands for the rhs of an floating point insns.
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138 ;; Allows regs or certain consts on FPA, just regs for everything else.
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139 (define_predicate "arm_float_rhs_operand"
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140 (ior (match_operand 0 "s_register_operand")
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141 (and (match_code "const_double")
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142 (match_test "TARGET_FPA && arm_const_double_rtx (op)"))))
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143
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144 (define_predicate "arm_float_add_operand"
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145 (ior (match_operand 0 "arm_float_rhs_operand")
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146 (and (match_code "const_double")
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147 (match_test "TARGET_FPA && neg_const_double_rtx_ok_for_fpa (op)"))))
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148
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149 (define_predicate "vfp_compare_operand"
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150 (ior (match_operand 0 "s_register_operand")
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151 (and (match_code "const_double")
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152 (match_test "arm_const_double_rtx (op)"))))
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153
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154 (define_predicate "arm_float_compare_operand"
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155 (if_then_else (match_test "TARGET_VFP")
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156 (match_operand 0 "vfp_compare_operand")
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157 (match_operand 0 "arm_float_rhs_operand")))
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158
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159 ;; True for valid index operands.
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160 (define_predicate "index_operand"
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161 (ior (match_operand 0 "s_register_operand")
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162 (and (match_operand 0 "immediate_operand")
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163 (match_test "(GET_CODE (op) != CONST_INT
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164 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
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165
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166 ;; True for operators that can be combined with a shift in ARM state.
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167 (define_special_predicate "shiftable_operator"
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168 (and (match_code "plus,minus,ior,xor,and")
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169 (match_test "mode == GET_MODE (op)")))
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170
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171 ;; True for logical binary operators.
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172 (define_special_predicate "logical_binary_operator"
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173 (and (match_code "ior,xor,and")
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174 (match_test "mode == GET_MODE (op)")))
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175
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176 ;; True for shift operators.
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177 (define_special_predicate "shift_operator"
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178 (and (ior (ior (and (match_code "mult")
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179 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
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180 (and (match_code "rotate")
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181 (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
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182 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
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183 (match_code "ashift,ashiftrt,lshiftrt,rotatert"))
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184 (match_test "mode == GET_MODE (op)")))
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185
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186 ;; True for operators that have 16-bit thumb variants. */
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187 (define_special_predicate "thumb_16bit_operator"
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188 (match_code "plus,minus,and,ior,xor"))
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189
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190 ;; True for EQ & NE
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191 (define_special_predicate "equality_operator"
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192 (match_code "eq,ne"))
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193
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194 ;; True for comparisons other than LTGT or UNEQ.
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195 (define_special_predicate "arm_comparison_operator"
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196 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt"))
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197
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198 (define_special_predicate "minmax_operator"
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199 (and (match_code "smin,smax,umin,umax")
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200 (match_test "mode == GET_MODE (op)")))
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201
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202 (define_special_predicate "cc_register"
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203 (and (match_code "reg")
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204 (and (match_test "REGNO (op) == CC_REGNUM")
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205 (ior (match_test "mode == GET_MODE (op)")
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206 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
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207
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208 (define_special_predicate "dominant_cc_register"
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209 (match_code "reg")
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210 {
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211 if (mode == VOIDmode)
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212 {
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213 mode = GET_MODE (op);
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214
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215 if (GET_MODE_CLASS (mode) != MODE_CC)
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216 return false;
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217 }
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218
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219 return (cc_register (op, mode)
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220 && (mode == CC_DNEmode
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221 || mode == CC_DEQmode
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222 || mode == CC_DLEmode
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223 || mode == CC_DLTmode
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224 || mode == CC_DGEmode
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225 || mode == CC_DGTmode
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226 || mode == CC_DLEUmode
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227 || mode == CC_DLTUmode
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228 || mode == CC_DGEUmode
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229 || mode == CC_DGTUmode));
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230 })
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231
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232 (define_special_predicate "arm_extendqisi_mem_op"
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233 (and (match_operand 0 "memory_operand")
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234 (match_test "arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND,
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235 0)")))
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236
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237 (define_special_predicate "arm_reg_or_extendqisi_mem_op"
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238 (ior (match_operand 0 "arm_extendqisi_mem_op")
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239 (match_operand 0 "s_register_operand")))
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240
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241 (define_predicate "power_of_two_operand"
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242 (match_code "const_int")
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243 {
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244 HOST_WIDE_INT value = INTVAL (op);
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245
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246 return value != 0 && (value & (value - 1)) == 0;
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247 })
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248
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249 (define_predicate "nonimmediate_di_operand"
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250 (match_code "reg,subreg,mem")
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251 {
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252 if (s_register_operand (op, mode))
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253 return true;
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254
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255 if (GET_CODE (op) == SUBREG)
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256 op = SUBREG_REG (op);
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257
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258 return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0));
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259 })
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260
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261 (define_predicate "di_operand"
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262 (ior (match_code "const_int,const_double")
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263 (and (match_code "reg,subreg,mem")
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264 (match_operand 0 "nonimmediate_di_operand"))))
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265
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266 (define_predicate "nonimmediate_soft_df_operand"
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267 (match_code "reg,subreg,mem")
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268 {
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269 if (s_register_operand (op, mode))
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270 return true;
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271
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272 if (GET_CODE (op) == SUBREG)
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273 op = SUBREG_REG (op);
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274
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275 return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0));
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276 })
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277
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278 (define_predicate "soft_df_operand"
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279 (ior (match_code "const_double")
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280 (and (match_code "reg,subreg,mem")
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281 (match_operand 0 "nonimmediate_soft_df_operand"))))
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282
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283 (define_predicate "const_shift_operand"
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284 (and (match_code "const_int")
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285 (ior (match_operand 0 "power_of_two_operand")
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286 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32"))))
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287
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288
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289 (define_special_predicate "load_multiple_operation"
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290 (match_code "parallel")
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291 {
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292 HOST_WIDE_INT count = XVECLEN (op, 0);
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293 int dest_regno;
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294 rtx src_addr;
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295 HOST_WIDE_INT i = 1, base = 0;
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296 rtx elt;
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297
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298 if (count <= 1
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299 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
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300 return false;
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301
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302 /* Check to see if this might be a write-back. */
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303 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
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304 {
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305 i++;
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306 base = 1;
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307
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308 /* Now check it more carefully. */
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309 if (GET_CODE (SET_DEST (elt)) != REG
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310 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
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311 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
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312 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
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313 return false;
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314 }
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315
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316 /* Perform a quick check so we don't blow up below. */
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317 if (count <= i
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318 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
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319 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
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320 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
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321 return false;
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322
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323 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
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324 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
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325
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326 for (; i < count; i++)
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327 {
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328 elt = XVECEXP (op, 0, i);
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329
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330 if (GET_CODE (elt) != SET
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331 || GET_CODE (SET_DEST (elt)) != REG
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332 || GET_MODE (SET_DEST (elt)) != SImode
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333 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
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334 || GET_CODE (SET_SRC (elt)) != MEM
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335 || GET_MODE (SET_SRC (elt)) != SImode
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336 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
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337 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
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338 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
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339 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
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340 return false;
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341 }
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342
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343 return true;
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344 })
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345
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346 (define_special_predicate "store_multiple_operation"
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347 (match_code "parallel")
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348 {
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349 HOST_WIDE_INT count = XVECLEN (op, 0);
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350 int src_regno;
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351 rtx dest_addr;
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352 HOST_WIDE_INT i = 1, base = 0;
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353 rtx elt;
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354
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355 if (count <= 1
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356 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
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357 return false;
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358
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359 /* Check to see if this might be a write-back. */
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360 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
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361 {
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362 i++;
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363 base = 1;
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364
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365 /* Now check it more carefully. */
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366 if (GET_CODE (SET_DEST (elt)) != REG
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367 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
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368 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
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369 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
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370 return false;
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371 }
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372
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373 /* Perform a quick check so we don't blow up below. */
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374 if (count <= i
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375 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
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376 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
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377 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
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378 return false;
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379
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380 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
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381 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
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382
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383 for (; i < count; i++)
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384 {
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385 elt = XVECEXP (op, 0, i);
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386
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387 if (GET_CODE (elt) != SET
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388 || GET_CODE (SET_SRC (elt)) != REG
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389 || GET_MODE (SET_SRC (elt)) != SImode
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390 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
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391 || GET_CODE (SET_DEST (elt)) != MEM
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392 || GET_MODE (SET_DEST (elt)) != SImode
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393 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
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394 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
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395 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
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396 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
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397 return false;
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398 }
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399
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400 return true;
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401 })
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402
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403 (define_special_predicate "multi_register_push"
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404 (match_code "parallel")
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405 {
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406 if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
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407 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
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408 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
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409 return false;
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410
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411 return true;
|
|
|
412 })
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|
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413
|
|
|
414 ;;-------------------------------------------------------------------------
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|
|
415 ;;
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|
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416 ;; Thumb predicates
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|
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417 ;;
|
|
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418
|
|
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419 (define_predicate "thumb1_cmp_operand"
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|
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420 (ior (and (match_code "reg,subreg")
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421 (match_operand 0 "s_register_operand"))
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|
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422 (and (match_code "const_int")
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|
|
423 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
|
|
|
424
|
|
|
425 (define_predicate "thumb1_cmpneg_operand"
|
|
|
426 (and (match_code "const_int")
|
|
|
427 (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
|
|
|
428
|
|
|
429 ;; Return TRUE if a result can be stored in OP without clobbering the
|
|
|
430 ;; condition code register. Prior to reload we only accept a
|
|
|
431 ;; register. After reload we have to be able to handle memory as
|
|
|
432 ;; well, since a pseudo may not get a hard reg and reload cannot
|
|
|
433 ;; handle output-reloads on jump insns.
|
|
|
434
|
|
|
435 ;; We could possibly handle mem before reload as well, but that might
|
|
|
436 ;; complicate things with the need to handle increment
|
|
|
437 ;; side-effects.
|
|
|
438 (define_predicate "thumb_cbrch_target_operand"
|
|
|
439 (and (match_code "reg,subreg,mem")
|
|
|
440 (ior (match_operand 0 "s_register_operand")
|
|
|
441 (and (match_test "reload_in_progress || reload_completed")
|
|
|
442 (match_operand 0 "memory_operand")))))
|
|
|
443
|
|
|
444 ;;-------------------------------------------------------------------------
|
|
|
445 ;;
|
|
|
446 ;; MAVERICK predicates
|
|
|
447 ;;
|
|
|
448
|
|
|
449 (define_predicate "cirrus_register_operand"
|
|
|
450 (match_code "reg,subreg")
|
|
|
451 {
|
|
|
452 if (GET_CODE (op) == SUBREG)
|
|
|
453 op = SUBREG_REG (op);
|
|
|
454
|
|
|
455 return (GET_CODE (op) == REG
|
|
|
456 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
|
|
|
457 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
|
|
|
458 })
|
|
|
459
|
|
|
460 (define_predicate "cirrus_fp_register"
|
|
|
461 (match_code "reg,subreg")
|
|
|
462 {
|
|
|
463 if (GET_CODE (op) == SUBREG)
|
|
|
464 op = SUBREG_REG (op);
|
|
|
465
|
|
|
466 return (GET_CODE (op) == REG
|
|
|
467 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
|
|
|
468 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
|
|
|
469 })
|
|
|
470
|
|
|
471 (define_predicate "cirrus_shift_const"
|
|
|
472 (and (match_code "const_int")
|
|
|
473 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64")))
|
|
|
474
|
|
|
475
|
|
|
476 ;; Neon predicates
|
|
|
477
|
|
|
478 (define_predicate "const_multiple_of_8_operand"
|
|
|
479 (match_code "const_int")
|
|
|
480 {
|
|
|
481 unsigned HOST_WIDE_INT val = INTVAL (op);
|
|
|
482 return (val & 7) == 0;
|
|
|
483 })
|
|
|
484
|
|
|
485 (define_predicate "imm_for_neon_mov_operand"
|
|
|
486 (match_code "const_vector")
|
|
|
487 {
|
|
|
488 return neon_immediate_valid_for_move (op, mode, NULL, NULL);
|
|
|
489 })
|
|
|
490
|
|
|
491 (define_predicate "imm_for_neon_logic_operand"
|
|
|
492 (match_code "const_vector")
|
|
|
493 {
|
|
|
494 return neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL);
|
|
|
495 })
|
|
|
496
|
|
|
497 (define_predicate "imm_for_neon_inv_logic_operand"
|
|
|
498 (match_code "const_vector")
|
|
|
499 {
|
|
|
500 return neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL);
|
|
|
501 })
|
|
|
502
|
|
|
503 (define_predicate "neon_logic_op2"
|
|
|
504 (ior (match_operand 0 "imm_for_neon_logic_operand")
|
|
|
505 (match_operand 0 "s_register_operand")))
|
|
|
506
|
|
|
507 (define_predicate "neon_inv_logic_op2"
|
|
|
508 (ior (match_operand 0 "imm_for_neon_inv_logic_operand")
|
|
|
509 (match_operand 0 "s_register_operand")))
|
|
|
510
|
|
|
511 ;; TODO: We could check lane numbers more precisely based on the mode.
|
|
|
512 (define_predicate "neon_lane_number"
|
|
|
513 (and (match_code "const_int")
|
|
|
514 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
|
|
|
515
|
