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0
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1 /* Definitions for the Blackfin port.
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2 Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
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3 Contributed by Analog Devices.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it
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8 under the terms of the GNU General Public License as published
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9 by the Free Software Foundation; either version 3, or (at your
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10 option) any later version.
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11
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12 GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21 #ifndef _BFIN_CONFIG
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22 #define _BFIN_CONFIG
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23
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24 #define OBJECT_FORMAT_ELF
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25
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26 #define BRT 1
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27 #define BRF 0
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28
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29 /* Print subsidiary information on the compiler version in use. */
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30 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)")
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31
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32 /* Run-time compilation parameters selecting different hardware subsets. */
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33
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34 extern int target_flags;
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35
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36 /* Predefinition in the preprocessor for this target machine */
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37 #ifndef TARGET_CPU_CPP_BUILTINS
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38 #define TARGET_CPU_CPP_BUILTINS() \
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39 do \
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40 { \
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41 builtin_define_std ("bfin"); \
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42 builtin_define_std ("BFIN"); \
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43 builtin_define ("__ADSPBLACKFIN__"); \
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44 builtin_define ("__ADSPLPBLACKFIN__"); \
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45 \
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46 switch (bfin_cpu_type) \
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47 { \
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48 case BFIN_CPU_BF512: \
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49 builtin_define ("__ADSPBF512__"); \
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50 builtin_define ("__ADSPBF51x__"); \
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51 break; \
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52 case BFIN_CPU_BF514: \
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53 builtin_define ("__ADSPBF514__"); \
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54 builtin_define ("__ADSPBF51x__"); \
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55 break; \
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56 case BFIN_CPU_BF516: \
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57 builtin_define ("__ADSPBF516__"); \
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58 builtin_define ("__ADSPBF51x__"); \
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59 break; \
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60 case BFIN_CPU_BF518: \
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61 builtin_define ("__ADSPBF518__"); \
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62 builtin_define ("__ADSPBF51x__"); \
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63 break; \
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64 case BFIN_CPU_BF522: \
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65 builtin_define ("__ADSPBF522__"); \
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66 builtin_define ("__ADSPBF52x__"); \
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67 break; \
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68 case BFIN_CPU_BF523: \
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69 builtin_define ("__ADSPBF523__"); \
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70 builtin_define ("__ADSPBF52x__"); \
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71 break; \
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72 case BFIN_CPU_BF524: \
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73 builtin_define ("__ADSPBF524__"); \
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74 builtin_define ("__ADSPBF52x__"); \
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75 break; \
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76 case BFIN_CPU_BF525: \
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77 builtin_define ("__ADSPBF525__"); \
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78 builtin_define ("__ADSPBF52x__"); \
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79 break; \
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80 case BFIN_CPU_BF526: \
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81 builtin_define ("__ADSPBF526__"); \
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82 builtin_define ("__ADSPBF52x__"); \
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83 break; \
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84 case BFIN_CPU_BF527: \
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85 builtin_define ("__ADSPBF527__"); \
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86 builtin_define ("__ADSPBF52x__"); \
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87 break; \
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88 case BFIN_CPU_BF531: \
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89 builtin_define ("__ADSPBF531__"); \
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90 break; \
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91 case BFIN_CPU_BF532: \
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92 builtin_define ("__ADSPBF532__"); \
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93 break; \
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94 case BFIN_CPU_BF533: \
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95 builtin_define ("__ADSPBF533__"); \
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96 break; \
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97 case BFIN_CPU_BF534: \
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98 builtin_define ("__ADSPBF534__"); \
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99 break; \
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100 case BFIN_CPU_BF536: \
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101 builtin_define ("__ADSPBF536__"); \
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102 break; \
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103 case BFIN_CPU_BF537: \
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104 builtin_define ("__ADSPBF537__"); \
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105 break; \
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106 case BFIN_CPU_BF538: \
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107 builtin_define ("__ADSPBF538__"); \
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108 break; \
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109 case BFIN_CPU_BF539: \
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110 builtin_define ("__ADSPBF539__"); \
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111 break; \
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112 case BFIN_CPU_BF542: \
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113 builtin_define ("__ADSPBF542__"); \
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114 builtin_define ("__ADSPBF54x__"); \
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115 break; \
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116 case BFIN_CPU_BF544: \
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117 builtin_define ("__ADSPBF544__"); \
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118 builtin_define ("__ADSPBF54x__"); \
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119 break; \
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120 case BFIN_CPU_BF548: \
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121 builtin_define ("__ADSPBF548__"); \
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122 builtin_define ("__ADSPBF54x__"); \
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123 break; \
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124 case BFIN_CPU_BF547: \
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125 builtin_define ("__ADSPBF547__"); \
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126 builtin_define ("__ADSPBF54x__"); \
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127 break; \
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128 case BFIN_CPU_BF549: \
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129 builtin_define ("__ADSPBF549__"); \
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130 builtin_define ("__ADSPBF54x__"); \
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131 break; \
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132 case BFIN_CPU_BF561: \
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133 builtin_define ("__ADSPBF561__"); \
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134 break; \
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135 } \
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136 \
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137 if (bfin_si_revision != -1) \
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138 { \
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139 /* space of 0xnnnn and a NUL */ \
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140 char *buf = XALLOCAVEC (char, 7); \
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141 \
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142 sprintf (buf, "0x%04x", bfin_si_revision); \
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143 builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \
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144 } \
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145 \
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146 if (bfin_workarounds) \
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147 builtin_define ("__WORKAROUNDS_ENABLED"); \
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148 if (ENABLE_WA_SPECULATIVE_LOADS) \
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149 builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \
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150 if (ENABLE_WA_SPECULATIVE_SYNCS) \
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151 builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \
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152 if (ENABLE_WA_INDIRECT_CALLS) \
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153 builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \
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154 if (ENABLE_WA_RETS) \
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155 builtin_define ("__WORKAROUND_RETS"); \
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156 \
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157 if (TARGET_FDPIC) \
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158 { \
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159 builtin_define ("__BFIN_FDPIC__"); \
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160 builtin_define ("__FDPIC__"); \
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161 } \
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162 if (TARGET_ID_SHARED_LIBRARY \
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163 && !TARGET_SEP_DATA) \
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164 builtin_define ("__ID_SHARED_LIB__"); \
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165 if (flag_no_builtin) \
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166 builtin_define ("__NO_BUILTIN"); \
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167 if (TARGET_MULTICORE) \
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168 builtin_define ("__BFIN_MULTICORE"); \
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169 if (TARGET_COREA) \
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170 builtin_define ("__BFIN_COREA"); \
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171 if (TARGET_COREB) \
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172 builtin_define ("__BFIN_COREB"); \
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173 if (TARGET_SDRAM) \
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174 builtin_define ("__BFIN_SDRAM"); \
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175 } \
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176 while (0)
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177 #endif
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178
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179 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
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180 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
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181 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
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182 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
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183 "
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184 #ifndef SUBTARGET_DRIVER_SELF_SPECS
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185 # define SUBTARGET_DRIVER_SELF_SPECS
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186 #endif
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187
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188 #define LINK_GCC_C_SEQUENCE_SPEC "\
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189 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \
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190 "
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191
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192 /* A C string constant that tells the GCC driver program options to pass to
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193 the assembler. It can also specify how to translate options you give to GNU
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194 CC into options for GCC to pass to the assembler. See the file `sun3.h'
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195 for an example of this.
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196
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197 Do not define this macro if it does not need to do anything.
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198
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199 Defined in svr4.h. */
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200 #undef ASM_SPEC
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201 #define ASM_SPEC "\
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202 %{G*} %{v} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \
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203 %{mno-fdpic:-mnopic} %{mfdpic}"
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204
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205 #define LINK_SPEC "\
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206 %{h*} %{v:-V} \
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207 %{b} \
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208 %{mfdpic:-melf32bfinfd -z text} \
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209 %{static:-dn -Bstatic} \
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210 %{shared:-G -Bdynamic} \
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211 %{symbolic:-Bsymbolic} \
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212 %{G*} \
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213 %{YP,*} \
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214 %{Qy:} %{!Qn:-Qy} \
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215 -init __init -fini __fini "
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216
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217 /* Generate DSP instructions, like DSP halfword loads */
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218 #define TARGET_DSP (1)
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219
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220 #define TARGET_DEFAULT 0
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221
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222 /* Maximum number of library ids we permit */
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223 #define MAX_LIBRARY_ID 255
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224
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225 extern const char *bfin_library_id_string;
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226
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227 /* Sometimes certain combinations of command options do not make
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228 sense on a particular target machine. You can define a macro
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229 `OVERRIDE_OPTIONS' to take account of this. This macro, if
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230 defined, is executed once just after all the command options have
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231 been parsed.
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232
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233 Don't use this macro to turn on various extra optimizations for
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234 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
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235
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236 #define OVERRIDE_OPTIONS override_options ()
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237
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238 #define FUNCTION_MODE SImode
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239 #define Pmode SImode
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240
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241 /* store-condition-codes instructions store 0 for false
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242 This is the value stored for true. */
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243 #define STORE_FLAG_VALUE 1
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244
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245 /* Define this if pushing a word on the stack
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246 makes the stack pointer a smaller address. */
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247 #define STACK_GROWS_DOWNWARD
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248
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249 #define STACK_PUSH_CODE PRE_DEC
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250
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251 /* Define this to nonzero if the nominal address of the stack frame
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252 is at the high-address end of the local variables;
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253 that is, each additional local variable allocated
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254 goes at a more negative offset in the frame. */
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255 #define FRAME_GROWS_DOWNWARD 1
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256
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257 /* We define a dummy ARGP register; the parameters start at offset 0 from
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258 it. */
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259 #define FIRST_PARM_OFFSET(DECL) 0
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260
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261 /* Offset within stack frame to start allocating local variables at.
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262 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
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263 first local allocated. Otherwise, it is the offset to the BEGINNING
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264 of the first local allocated. */
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265 #define STARTING_FRAME_OFFSET 0
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266
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267 /* Register to use for pushing function arguments. */
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268 #define STACK_POINTER_REGNUM REG_P6
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269
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270 /* Base register for access to local variables of the function. */
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271 #define FRAME_POINTER_REGNUM REG_P7
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272
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273 /* A dummy register that will be eliminated to either FP or SP. */
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274 #define ARG_POINTER_REGNUM REG_ARGP
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275
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276 /* `PIC_OFFSET_TABLE_REGNUM'
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277 The register number of the register used to address a table of
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278 static data addresses in memory. In some cases this register is
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279 defined by a processor's "application binary interface" (ABI).
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280 When this macro is defined, RTL is generated for this register
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281 once, as with the stack pointer and frame pointer registers. If
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282 this macro is not defined, it is up to the machine-dependent files
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283 to allocate such a register (if necessary). */
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284 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
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285
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286 #define FDPIC_FPTR_REGNO REG_P1
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287 #define FDPIC_REGNO REG_P3
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288 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
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289
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290 /* A static chain register for nested functions. We need to use a
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291 call-clobbered register for this. */
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292 #define STATIC_CHAIN_REGNUM REG_P2
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293
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294 /* Define this if functions should assume that stack space has been
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295 allocated for arguments even when their values are passed in
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296 registers.
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297
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298 The value of this macro is the size, in bytes, of the area reserved for
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299 arguments passed in registers.
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300
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301 This space can either be allocated by the caller or be a part of the
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302 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
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303 says which. */
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304 #define FIXED_STACK_AREA 12
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305 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
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306
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307 /* Define this if the above stack space is to be considered part of the
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308 * space allocated by the caller. */
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309 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
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310
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311 /* Define this if the maximum size of all the outgoing args is to be
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312 accumulated and pushed during the prologue. The amount can be
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313 found in the variable crtl->outgoing_args_size. */
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314 #define ACCUMULATE_OUTGOING_ARGS 1
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315
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316 /* Value should be nonzero if functions must have frame pointers.
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317 Zero means the frame pointer need not be set up (and parms
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318 may be accessed via the stack pointer) in functions that seem suitable.
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319 This is computed in `reload', in reload1.c.
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320 */
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321 #define FRAME_POINTER_REQUIRED (bfin_frame_pointer_required ())
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322
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323 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
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324
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325 /* If defined, a C expression to compute the alignment for a local
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326 variable. TYPE is the data type, and ALIGN is the alignment that
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327 the object would ordinarily have. The value of this macro is used
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328 instead of that alignment to align the object.
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329
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330 If this macro is not defined, then ALIGN is used.
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331
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332 One use of this macro is to increase alignment of medium-size
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333 data to make it all fit in fewer cache lines. */
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334
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335 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
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336
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337 /* Make strings word-aligned so strcpy from constants will be faster. */
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338 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
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339 (TREE_CODE (EXP) == STRING_CST \
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340 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
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341
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342 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
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343 #define TRAMPOLINE_TEMPLATE(FILE) \
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344 if (TARGET_FDPIC) \
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345 { \
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346 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \
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347 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \
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348 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
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349 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \
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350 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \
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351 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \
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352 fprintf(FILE, "\t.dw\t0xac4b\n"); /* p3 = [p1 + 4] */ \
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353 fprintf(FILE, "\t.dw\t0x9149\n"); /* p1 = [p1] */ \
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354 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \
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355 } \
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356 else \
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357 { \
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358 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
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359 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \
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360 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \
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361 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \
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362 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \
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363 }
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364
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365 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
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366 initialize_trampoline (TRAMP, FNADDR, CXT)
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367
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368 /* Definitions for register eliminations.
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369
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370 This is an array of structures. Each structure initializes one pair
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371 of eliminable registers. The "from" register number is given first,
|
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372 followed by "to". Eliminations of the same "from" register are listed
|
|
|
373 in order of preference.
|
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374
|
|
|
375 There are two registers that can always be eliminated on the i386.
|
|
|
376 The frame pointer and the arg pointer can be replaced by either the
|
|
|
377 hard frame pointer or to the stack pointer, depending upon the
|
|
|
378 circumstances. The hard frame pointer is not used before reload and
|
|
|
379 so it is not eligible for elimination. */
|
|
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380
|
|
|
381 #define ELIMINABLE_REGS \
|
|
|
382 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
|
|
383 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
|
|
|
384 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
|
|
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385
|
|
|
386 /* Given FROM and TO register numbers, say whether this elimination is
|
|
|
387 allowed. Frame pointer elimination is automatically handled.
|
|
|
388
|
|
|
389 All other eliminations are valid. */
|
|
|
390
|
|
|
391 #define CAN_ELIMINATE(FROM, TO) \
|
|
|
392 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
|
|
|
393
|
|
|
394 /* Define the offset between two registers, one to be eliminated, and the other
|
|
|
395 its replacement, at the start of a routine. */
|
|
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396
|
|
|
397 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
|
|
398 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
|
|
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399
|
|
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400 /* This processor has
|
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401 8 data register for doing arithmetic
|
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|
402 8 pointer register for doing addressing, including
|
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403 1 stack pointer P6
|
|
|
404 1 frame pointer P7
|
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405 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
|
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406 1 condition code flag register CC
|
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407 5 return address registers RETS/I/X/N/E
|
|
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408 1 arithmetic status register (ASTAT). */
|
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409
|
|
|
410 #define FIRST_PSEUDO_REGISTER 50
|
|
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411
|
|
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412 #define D_REGNO_P(X) ((X) <= REG_R7)
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413 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
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414 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
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415 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
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416 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
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|
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417 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
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|
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418 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
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|
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419 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
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|
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420 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
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421
|
|
|
422 #define REGISTER_NAMES { \
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423 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
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|
|
424 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
|
|
|
425 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
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|
|
426 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
|
|
|
427 "A0", "A1", \
|
|
|
428 "CC", \
|
|
|
429 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
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|
|
430 "ARGP", \
|
|
|
431 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
|
|
|
432 }
|
|
|
433
|
|
|
434 #define SHORT_REGISTER_NAMES { \
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|
|
435 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
|
|
|
436 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
|
|
|
437 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
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|
|
438 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
|
|
|
439
|
|
|
440 #define HIGH_REGISTER_NAMES { \
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|
|
441 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
|
|
|
442 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
|
|
|
443 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
|
|
|
444 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
|
|
|
445
|
|
|
446 #define DREGS_PAIR_NAMES { \
|
|
|
447 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
|
|
|
448
|
|
|
449 #define BYTE_REGISTER_NAMES { \
|
|
|
450 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
|
|
|
451
|
|
|
452
|
|
|
453 /* 1 for registers that have pervasive standard uses
|
|
|
454 and are not available for the register allocator. */
|
|
|
455
|
|
|
456 #define FIXED_REGISTERS \
|
|
|
457 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
|
|
|
458 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
|
|
459 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
|
|
|
460 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
|
|
|
461 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
|
|
|
462 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
|
|
463 /*lb0/1 */ \
|
|
|
464 1, 1 \
|
|
|
465 }
|
|
|
466
|
|
|
467 /* 1 for registers not available across function calls.
|
|
|
468 These must include the FIXED_REGISTERS and also any
|
|
|
469 registers that can be used without being saved.
|
|
|
470 The latter must include the registers where values are returned
|
|
|
471 and the register where structure-value addresses are passed.
|
|
|
472 Aside from that, you can include as many other registers as you like. */
|
|
|
473
|
|
|
474 #define CALL_USED_REGISTERS \
|
|
|
475 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
|
|
|
476 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
|
|
|
477 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
|
|
|
478 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
|
|
479 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
|
|
|
480 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
|
|
481 /*lb0/1 */ \
|
|
|
482 1, 1 \
|
|
|
483 }
|
|
|
484
|
|
|
485 /* Order in which to allocate registers. Each register must be
|
|
|
486 listed once, even those in FIXED_REGISTERS. List frame pointer
|
|
|
487 late and fixed registers last. Note that, in general, we prefer
|
|
|
488 registers listed in CALL_USED_REGISTERS, keeping the others
|
|
|
489 available for storage of persistent values. */
|
|
|
490
|
|
|
491 #define REG_ALLOC_ORDER \
|
|
|
492 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
|
|
|
493 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
|
|
|
494 REG_A0, REG_A1, \
|
|
|
495 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
|
|
|
496 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
|
|
|
497 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
|
|
|
498 REG_ASTAT, REG_SEQSTAT, REG_USP, \
|
|
|
499 REG_CC, REG_ARGP, \
|
|
|
500 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
|
|
|
501 }
|
|
|
502
|
|
|
503 /* Macro to conditionally modify fixed_regs/call_used_regs. */
|
|
|
504 #define CONDITIONAL_REGISTER_USAGE \
|
|
|
505 { \
|
|
|
506 conditional_register_usage(); \
|
|
|
507 if (TARGET_FDPIC) \
|
|
|
508 call_used_regs[FDPIC_REGNO] = 1; \
|
|
|
509 if (!TARGET_FDPIC && flag_pic) \
|
|
|
510 { \
|
|
|
511 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
|
|
|
512 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
|
|
|
513 } \
|
|
|
514 }
|
|
|
515
|
|
|
516 /* Define the classes of registers for register constraints in the
|
|
|
517 machine description. Also define ranges of constants.
|
|
|
518
|
|
|
519 One of the classes must always be named ALL_REGS and include all hard regs.
|
|
|
520 If there is more than one class, another class must be named NO_REGS
|
|
|
521 and contain no registers.
|
|
|
522
|
|
|
523 The name GENERAL_REGS must be the name of a class (or an alias for
|
|
|
524 another name such as ALL_REGS). This is the class of registers
|
|
|
525 that is allowed by "g" or "r" in a register constraint.
|
|
|
526 Also, registers outside this class are allocated only when
|
|
|
527 instructions express preferences for them.
|
|
|
528
|
|
|
529 The classes must be numbered in nondecreasing order; that is,
|
|
|
530 a larger-numbered class must never be contained completely
|
|
|
531 in a smaller-numbered class.
|
|
|
532
|
|
|
533 For any two classes, it is very desirable that there be another
|
|
|
534 class that represents their union. */
|
|
|
535
|
|
|
536
|
|
|
537 enum reg_class
|
|
|
538 {
|
|
|
539 NO_REGS,
|
|
|
540 IREGS,
|
|
|
541 BREGS,
|
|
|
542 LREGS,
|
|
|
543 MREGS,
|
|
|
544 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
|
|
|
545 DAGREGS,
|
|
|
546 EVEN_AREGS,
|
|
|
547 ODD_AREGS,
|
|
|
548 AREGS,
|
|
|
549 CCREGS,
|
|
|
550 EVEN_DREGS,
|
|
|
551 ODD_DREGS,
|
|
|
552 D0REGS,
|
|
|
553 D1REGS,
|
|
|
554 D2REGS,
|
|
|
555 D3REGS,
|
|
|
556 D4REGS,
|
|
|
557 D5REGS,
|
|
|
558 D6REGS,
|
|
|
559 D7REGS,
|
|
|
560 DREGS,
|
|
|
561 P0REGS,
|
|
|
562 FDPIC_REGS,
|
|
|
563 FDPIC_FPTR_REGS,
|
|
|
564 PREGS_CLOBBERED,
|
|
|
565 PREGS,
|
|
|
566 IPREGS,
|
|
|
567 DPREGS,
|
|
|
568 MOST_REGS,
|
|
|
569 LT_REGS,
|
|
|
570 LC_REGS,
|
|
|
571 LB_REGS,
|
|
|
572 PROLOGUE_REGS,
|
|
|
573 NON_A_CC_REGS,
|
|
|
574 ALL_REGS, LIM_REG_CLASSES
|
|
|
575 };
|
|
|
576
|
|
|
577 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
|
|
|
578
|
|
|
579 #define GENERAL_REGS DPREGS
|
|
|
580
|
|
|
581 /* Give names of register classes as strings for dump file. */
|
|
|
582
|
|
|
583 #define REG_CLASS_NAMES \
|
|
|
584 { "NO_REGS", \
|
|
|
585 "IREGS", \
|
|
|
586 "BREGS", \
|
|
|
587 "LREGS", \
|
|
|
588 "MREGS", \
|
|
|
589 "CIRCREGS", \
|
|
|
590 "DAGREGS", \
|
|
|
591 "EVEN_AREGS", \
|
|
|
592 "ODD_AREGS", \
|
|
|
593 "AREGS", \
|
|
|
594 "CCREGS", \
|
|
|
595 "EVEN_DREGS", \
|
|
|
596 "ODD_DREGS", \
|
|
|
597 "D0REGS", \
|
|
|
598 "D1REGS", \
|
|
|
599 "D2REGS", \
|
|
|
600 "D3REGS", \
|
|
|
601 "D4REGS", \
|
|
|
602 "D5REGS", \
|
|
|
603 "D6REGS", \
|
|
|
604 "D7REGS", \
|
|
|
605 "DREGS", \
|
|
|
606 "P0REGS", \
|
|
|
607 "FDPIC_REGS", \
|
|
|
608 "FDPIC_FPTR_REGS", \
|
|
|
609 "PREGS_CLOBBERED", \
|
|
|
610 "PREGS", \
|
|
|
611 "IPREGS", \
|
|
|
612 "DPREGS", \
|
|
|
613 "MOST_REGS", \
|
|
|
614 "LT_REGS", \
|
|
|
615 "LC_REGS", \
|
|
|
616 "LB_REGS", \
|
|
|
617 "PROLOGUE_REGS", \
|
|
|
618 "NON_A_CC_REGS", \
|
|
|
619 "ALL_REGS" }
|
|
|
620
|
|
|
621 /* An initializer containing the contents of the register classes, as integers
|
|
|
622 which are bit masks. The Nth integer specifies the contents of class N.
|
|
|
623 The way the integer MASK is interpreted is that register R is in the class
|
|
|
624 if `MASK & (1 << R)' is 1.
|
|
|
625
|
|
|
626 When the machine has more than 32 registers, an integer does not suffice.
|
|
|
627 Then the integers are replaced by sub-initializers, braced groupings
|
|
|
628 containing several integers. Each sub-initializer must be suitable as an
|
|
|
629 initializer for the type `HARD_REG_SET' which is defined in
|
|
|
630 `hard-reg-set.h'. */
|
|
|
631
|
|
|
632 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
|
|
|
633 MOST_REGS as the union of DPREGS and DAGREGS. */
|
|
|
634
|
|
|
635 #define REG_CLASS_CONTENTS \
|
|
|
636 /* 31 - 0 63-32 */ \
|
|
|
637 { { 0x00000000, 0 }, /* NO_REGS */ \
|
|
|
638 { 0x000f0000, 0 }, /* IREGS */ \
|
|
|
639 { 0x00f00000, 0 }, /* BREGS */ \
|
|
|
640 { 0x0f000000, 0 }, /* LREGS */ \
|
|
|
641 { 0xf0000000, 0 }, /* MREGS */ \
|
|
|
642 { 0x0fff0000, 0 }, /* CIRCREGS */ \
|
|
|
643 { 0xffff0000, 0 }, /* DAGREGS */ \
|
|
|
644 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
|
|
|
645 { 0x00000000, 0x2 }, /* ODD_AREGS */ \
|
|
|
646 { 0x00000000, 0x3 }, /* AREGS */ \
|
|
|
647 { 0x00000000, 0x4 }, /* CCREGS */ \
|
|
|
648 { 0x00000055, 0 }, /* EVEN_DREGS */ \
|
|
|
649 { 0x000000aa, 0 }, /* ODD_DREGS */ \
|
|
|
650 { 0x00000001, 0 }, /* D0REGS */ \
|
|
|
651 { 0x00000002, 0 }, /* D1REGS */ \
|
|
|
652 { 0x00000004, 0 }, /* D2REGS */ \
|
|
|
653 { 0x00000008, 0 }, /* D3REGS */ \
|
|
|
654 { 0x00000010, 0 }, /* D4REGS */ \
|
|
|
655 { 0x00000020, 0 }, /* D5REGS */ \
|
|
|
656 { 0x00000040, 0 }, /* D6REGS */ \
|
|
|
657 { 0x00000080, 0 }, /* D7REGS */ \
|
|
|
658 { 0x000000ff, 0 }, /* DREGS */ \
|
|
|
659 { 0x00000100, 0x000 }, /* P0REGS */ \
|
|
|
660 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \
|
|
|
661 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
|
|
|
662 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
|
|
|
663 { 0x0000ff00, 0x800 }, /* PREGS */ \
|
|
|
664 { 0x000fff00, 0x800 }, /* IPREGS */ \
|
|
|
665 { 0x0000ffff, 0x800 }, /* DPREGS */ \
|
|
|
666 { 0xffffffff, 0x800 }, /* MOST_REGS */\
|
|
|
667 { 0x00000000, 0x3000 }, /* LT_REGS */\
|
|
|
668 { 0x00000000, 0xc000 }, /* LC_REGS */\
|
|
|
669 { 0x00000000, 0x30000 }, /* LB_REGS */\
|
|
|
670 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\
|
|
|
671 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\
|
|
|
672 { 0xffffffff, 0x3ffff }} /* ALL_REGS */
|
|
|
673
|
|
|
674 #define IREG_POSSIBLE_P(OUTER) \
|
|
|
675 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
|
|
|
676 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
|
|
|
677 || (OUTER) == MEM || (OUTER) == ADDRESS)
|
|
|
678
|
|
|
679 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \
|
|
|
680 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
|
|
|
681
|
|
|
682 #define INDEX_REG_CLASS PREGS
|
|
|
683
|
|
|
684 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
|
|
|
685 (P_REGNO_P (X) || (X) == REG_ARGP \
|
|
|
686 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
|
|
|
687 && I_REGNO_P (X)))
|
|
|
688
|
|
|
689 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
|
|
|
690 ((X) >= FIRST_PSEUDO_REGISTER \
|
|
|
691 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
|
|
|
692
|
|
|
693 #ifdef REG_OK_STRICT
|
|
|
694 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
|
|
|
695 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
|
|
|
696 #else
|
|
|
697 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
|
|
|
698 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
|
|
|
699 #endif
|
|
|
700
|
|
|
701 #define REGNO_OK_FOR_INDEX_P(X) 0
|
|
|
702
|
|
|
703 /* The same information, inverted:
|
|
|
704 Return the class number of the smallest class containing
|
|
|
705 reg number REGNO. This could be a conditional expression
|
|
|
706 or could index an array. */
|
|
|
707
|
|
|
708 #define REGNO_REG_CLASS(REGNO) \
|
|
|
709 ((REGNO) == REG_R0 ? D0REGS \
|
|
|
710 : (REGNO) == REG_R1 ? D1REGS \
|
|
|
711 : (REGNO) == REG_R2 ? D2REGS \
|
|
|
712 : (REGNO) == REG_R3 ? D3REGS \
|
|
|
713 : (REGNO) == REG_R4 ? D4REGS \
|
|
|
714 : (REGNO) == REG_R5 ? D5REGS \
|
|
|
715 : (REGNO) == REG_R6 ? D6REGS \
|
|
|
716 : (REGNO) == REG_R7 ? D7REGS \
|
|
|
717 : (REGNO) == REG_P0 ? P0REGS \
|
|
|
718 : (REGNO) < REG_I0 ? PREGS \
|
|
|
719 : (REGNO) == REG_ARGP ? PREGS \
|
|
|
720 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
|
|
|
721 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
|
|
|
722 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
|
|
|
723 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
|
|
|
724 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
|
|
|
725 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
|
|
|
726 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
|
|
|
727 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
|
|
|
728 : (REGNO) == REG_CC ? CCREGS \
|
|
|
729 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
|
|
|
730 : NO_REGS)
|
|
|
731
|
|
|
732 /* The following macro defines cover classes for Integrated Register
|
|
|
733 Allocator. Cover classes is a set of non-intersected register
|
|
|
734 classes covering all hard registers used for register allocation
|
|
|
735 purpose. Any move between two registers of a cover class should be
|
|
|
736 cheaper than load or store of the registers. The macro value is
|
|
|
737 array of register classes with LIM_REG_CLASSES used as the end
|
|
|
738 marker. */
|
|
|
739
|
|
|
740 #define IRA_COVER_CLASSES \
|
|
|
741 { \
|
|
|
742 MOST_REGS, AREGS, CCREGS, LIM_REG_CLASSES \
|
|
|
743 }
|
|
|
744
|
|
|
745 /* When defined, the compiler allows registers explicitly used in the
|
|
|
746 rtl to be used as spill registers but prevents the compiler from
|
|
|
747 extending the lifetime of these registers. */
|
|
|
748 #define SMALL_REGISTER_CLASSES 1
|
|
|
749
|
|
|
750 #define CLASS_LIKELY_SPILLED_P(CLASS) \
|
|
|
751 ((CLASS) == PREGS_CLOBBERED \
|
|
|
752 || (CLASS) == PROLOGUE_REGS \
|
|
|
753 || (CLASS) == P0REGS \
|
|
|
754 || (CLASS) == D0REGS \
|
|
|
755 || (CLASS) == D1REGS \
|
|
|
756 || (CLASS) == D2REGS \
|
|
|
757 || (CLASS) == CCREGS)
|
|
|
758
|
|
|
759 /* Do not allow to store a value in REG_CC for any mode */
|
|
|
760 /* Do not allow to store value in pregs if mode is not SI*/
|
|
|
761 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
|
|
|
762
|
|
|
763 /* Return the maximum number of consecutive registers
|
|
|
764 needed to represent mode MODE in a register of class CLASS. */
|
|
|
765 #define CLASS_MAX_NREGS(CLASS, MODE) \
|
|
|
766 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
|
|
|
767 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
|
|
|
768
|
|
|
769 #define HARD_REGNO_NREGS(REGNO, MODE) \
|
|
|
770 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
|
|
|
771 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
|
|
|
772 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
|
|
|
773
|
|
|
774 /* A C expression that is nonzero if hard register TO can be
|
|
|
775 considered for use as a rename register for FROM register */
|
|
|
776 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
|
|
|
777
|
|
|
778 /* A C expression that is nonzero if it is desirable to choose
|
|
|
779 register allocation so as to avoid move instructions between a
|
|
|
780 value of mode MODE1 and a value of mode MODE2.
|
|
|
781
|
|
|
782 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
|
|
|
783 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
|
|
|
784 MODE2)' must be zero. */
|
|
|
785 #define MODES_TIEABLE_P(MODE1, MODE2) \
|
|
|
786 ((MODE1) == (MODE2) \
|
|
|
787 || ((GET_MODE_CLASS (MODE1) == MODE_INT \
|
|
|
788 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \
|
|
|
789 && (GET_MODE_CLASS (MODE2) == MODE_INT \
|
|
|
790 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \
|
|
|
791 && (MODE1) != BImode && (MODE2) != BImode \
|
|
|
792 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
|
|
|
793 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD))
|
|
|
794
|
|
|
795 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
|
|
|
796 A C expression that places additional restrictions on the register
|
|
|
797 class to use when it is necessary to copy value X into a register
|
|
|
798 in class CLASS. The value is a register class; perhaps CLASS, or
|
|
|
799 perhaps another, smaller class. */
|
|
|
800 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
|
|
|
801 (GET_CODE (X) == POST_INC \
|
|
|
802 || GET_CODE (X) == POST_DEC \
|
|
|
803 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS))
|
|
|
804
|
|
|
805 /* Function Calling Conventions. */
|
|
|
806
|
|
|
807 /* The type of the current function; normal functions are of type
|
|
|
808 SUBROUTINE. */
|
|
|
809 typedef enum {
|
|
|
810 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
|
|
|
811 } e_funkind;
|
|
|
812
|
|
|
813 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
|
|
|
814
|
|
|
815 /* Flags for the call/call_value rtl operations set up by function_arg */
|
|
|
816 #define CALL_NORMAL 0x00000000 /* no special processing */
|
|
|
817 #define CALL_LONG 0x00000001 /* always call indirect */
|
|
|
818 #define CALL_SHORT 0x00000002 /* always call by symbol */
|
|
|
819
|
|
|
820 typedef struct {
|
|
|
821 int words; /* # words passed so far */
|
|
|
822 int nregs; /* # registers available for passing */
|
|
|
823 int *arg_regs; /* array of register -1 terminated */
|
|
|
824 int call_cookie; /* Do special things for this call */
|
|
|
825 } CUMULATIVE_ARGS;
|
|
|
826
|
|
|
827 /* Define where to put the arguments to a function.
|
|
|
828 Value is zero to push the argument on the stack,
|
|
|
829 or a hard register in which to store the argument.
|
|
|
830
|
|
|
831 MODE is the argument's machine mode.
|
|
|
832 TYPE is the data type of the argument (as a tree).
|
|
|
833 This is null for libcalls where that information may
|
|
|
834 not be available.
|
|
|
835 CUM is a variable of type CUMULATIVE_ARGS which gives info about
|
|
|
836 the preceding args and about the function being called.
|
|
|
837 NAMED is nonzero if this argument is a named parameter
|
|
|
838 (otherwise it is an extra parameter matching an ellipsis). */
|
|
|
839
|
|
|
840 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
|
|
|
841 (function_arg (&CUM, MODE, TYPE, NAMED))
|
|
|
842
|
|
|
843 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
|
|
|
844
|
|
|
845
|
|
|
846 /* Initialize a variable CUM of type CUMULATIVE_ARGS
|
|
|
847 for a call to a function whose data type is FNTYPE.
|
|
|
848 For a library call, FNTYPE is 0. */
|
|
|
849 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
|
|
|
850 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
|
|
|
851
|
|
|
852 /* Update the data in CUM to advance over an argument
|
|
|
853 of mode MODE and data type TYPE.
|
|
|
854 (TYPE is null for libcalls where that information may not be available.) */
|
|
|
855 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
|
|
|
856 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
|
|
|
857
|
|
|
858 #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0
|
|
|
859
|
|
|
860 /* Define how to find the value returned by a function.
|
|
|
861 VALTYPE is the data type of the value (as a tree).
|
|
|
862 If the precise function being called is known, FUNC is its FUNCTION_DECL;
|
|
|
863 otherwise, FUNC is 0.
|
|
|
864 */
|
|
|
865
|
|
|
866 #define VALUE_REGNO(MODE) (REG_R0)
|
|
|
867
|
|
|
868 #define FUNCTION_VALUE(VALTYPE, FUNC) \
|
|
|
869 gen_rtx_REG (TYPE_MODE (VALTYPE), \
|
|
|
870 VALUE_REGNO(TYPE_MODE(VALTYPE)))
|
|
|
871
|
|
|
872 /* Define how to find the value returned by a library function
|
|
|
873 assuming the value has mode MODE. */
|
|
|
874
|
|
|
875 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
|
|
|
876
|
|
|
877 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
|
|
|
878
|
|
|
879 #define DEFAULT_PCC_STRUCT_RETURN 0
|
|
|
880
|
|
|
881 /* Before the prologue, the return address is in the RETS register. */
|
|
|
882 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
|
|
|
883
|
|
|
884 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
|
|
|
885
|
|
|
886 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
|
|
|
887
|
|
|
888 /* Call instructions don't modify the stack pointer on the Blackfin. */
|
|
|
889 #define INCOMING_FRAME_SP_OFFSET 0
|
|
|
890
|
|
|
891 /* Describe how we implement __builtin_eh_return. */
|
|
|
892 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
|
|
|
893 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
|
|
|
894 #define EH_RETURN_HANDLER_RTX \
|
|
|
895 gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
|
|
|
896
|
|
|
897 /* Addressing Modes */
|
|
|
898
|
|
|
899 /* Recognize any constant value that is a valid address. */
|
|
|
900 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
|
|
|
901
|
|
|
902 /* Nonzero if the constant value X is a legitimate general operand.
|
|
|
903 symbol_ref are not legitimate and will be put into constant pool.
|
|
|
904 See force_const_mem().
|
|
|
905 If -mno-pool, all constants are legitimate.
|
|
|
906 */
|
|
|
907 #define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X)
|
|
|
908
|
|
|
909 /* A number, the maximum number of registers that can appear in a
|
|
|
910 valid memory address. Note that it is up to you to specify a
|
|
|
911 value equal to the maximum number that `GO_IF_LEGITIMATE_ADDRESS'
|
|
|
912 would ever accept. */
|
|
|
913 #define MAX_REGS_PER_ADDRESS 1
|
|
|
914
|
|
|
915 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
|
|
|
916 that is a valid memory address for an instruction.
|
|
|
917 The MODE argument is the machine mode for the MEM expression
|
|
|
918 that wants to use this address.
|
|
|
919
|
|
|
920 Blackfin addressing modes are as follows:
|
|
|
921
|
|
|
922 [preg]
|
|
|
923 [preg + imm16]
|
|
|
924
|
|
|
925 B [ Preg + uimm15 ]
|
|
|
926 W [ Preg + uimm16m2 ]
|
|
|
927 [ Preg + uimm17m4 ]
|
|
|
928
|
|
|
929 [preg++]
|
|
|
930 [preg--]
|
|
|
931 [--sp]
|
|
|
932 */
|
|
|
933
|
|
|
934 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
|
|
|
935 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
|
|
|
936
|
|
|
937 #ifdef REG_OK_STRICT
|
|
|
938 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
|
|
|
939 do { \
|
|
|
940 if (bfin_legitimate_address_p (MODE, X, 1)) \
|
|
|
941 goto WIN; \
|
|
|
942 } while (0);
|
|
|
943 #else
|
|
|
944 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
|
|
|
945 do { \
|
|
|
946 if (bfin_legitimate_address_p (MODE, X, 0)) \
|
|
|
947 goto WIN; \
|
|
|
948 } while (0);
|
|
|
949 #endif
|
|
|
950
|
|
|
951 /* Try machine-dependent ways of modifying an illegitimate address
|
|
|
952 to be legitimate. If we find one, return the new, valid address.
|
|
|
953 This macro is used in only one place: `memory_address' in explow.c.
|
|
|
954
|
|
|
955 OLDX is the address as it was before break_out_memory_refs was called.
|
|
|
956 In some cases it is useful to look at this to decide what needs to be done.
|
|
|
957
|
|
|
958 MODE and WIN are passed so that this macro can use
|
|
|
959 GO_IF_LEGITIMATE_ADDRESS.
|
|
|
960
|
|
|
961 It is always safe for this macro to do nothing. It exists to recognize
|
|
|
962 opportunities to optimize the output.
|
|
|
963 */
|
|
|
964 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
|
|
|
965 do { \
|
|
|
966 rtx _q = legitimize_address(X, OLDX, MODE); \
|
|
|
967 if (_q) { X = _q; goto WIN; } \
|
|
|
968 } while (0)
|
|
|
969
|
|
|
970 #define HAVE_POST_INCREMENT 1
|
|
|
971 #define HAVE_POST_DECREMENT 1
|
|
|
972 #define HAVE_PRE_DECREMENT 1
|
|
|
973
|
|
|
974 /* `LEGITIMATE_PIC_OPERAND_P (X)'
|
|
|
975 A C expression that is nonzero if X is a legitimate immediate
|
|
|
976 operand on the target machine when generating position independent
|
|
|
977 code. You can assume that X satisfies `CONSTANT_P', so you need
|
|
|
978 not check this. You can also assume FLAG_PIC is true, so you need
|
|
|
979 not check it either. You need not define this macro if all
|
|
|
980 constants (including `SYMBOL_REF') can be immediate operands when
|
|
|
981 generating position independent code. */
|
|
|
982 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
|
|
|
983
|
|
|
984 #define SYMBOLIC_CONST(X) \
|
|
|
985 (GET_CODE (X) == SYMBOL_REF \
|
|
|
986 || GET_CODE (X) == LABEL_REF \
|
|
|
987 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
|
|
|
988
|
|
|
989 /*
|
|
|
990 A C statement or compound statement with a conditional `goto
|
|
|
991 LABEL;' executed if memory address X (an RTX) can have different
|
|
|
992 meanings depending on the machine mode of the memory reference it
|
|
|
993 is used for or if the address is valid for some modes but not
|
|
|
994 others.
|
|
|
995
|
|
|
996 Autoincrement and autodecrement addresses typically have
|
|
|
997 mode-dependent effects because the amount of the increment or
|
|
|
998 decrement is the size of the operand being addressed. Some
|
|
|
999 machines have other mode-dependent addresses. Many RISC machines
|
|
|
1000 have no mode-dependent addresses.
|
|
|
1001
|
|
|
1002 You may assume that ADDR is a valid address for the machine.
|
|
|
1003 */
|
|
|
1004 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
|
|
|
1005
|
|
|
1006 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
|
|
|
1007
|
|
|
1008 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
|
|
|
1009 is done just by pretending it is already truncated. */
|
|
|
1010 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
|
|
|
1011
|
|
|
1012 /* Max number of bytes we can move from memory to memory
|
|
|
1013 in one reasonably fast instruction. */
|
|
|
1014 #define MOVE_MAX UNITS_PER_WORD
|
|
|
1015
|
|
|
1016 /* If a memory-to-memory move would take MOVE_RATIO or more simple
|
|
|
1017 move-instruction pairs, we will do a movmem or libcall instead. */
|
|
|
1018
|
|
|
1019 #define MOVE_RATIO(speed) 5
|
|
|
1020
|
|
|
1021 /* STORAGE LAYOUT: target machine storage layout
|
|
|
1022 Define this macro as a C expression which is nonzero if accessing
|
|
|
1023 less than a word of memory (i.e. a `char' or a `short') is no
|
|
|
1024 faster than accessing a word of memory, i.e., if such access
|
|
|
1025 require more than one instruction or if there is no difference in
|
|
|
1026 cost between byte and (aligned) word loads.
|
|
|
1027
|
|
|
1028 When this macro is not defined, the compiler will access a field by
|
|
|
1029 finding the smallest containing object; when it is defined, a
|
|
|
1030 fullword load will be used if alignment permits. Unless bytes
|
|
|
1031 accesses are faster than word accesses, using word accesses is
|
|
|
1032 preferable since it may eliminate subsequent memory access if
|
|
|
1033 subsequent accesses occur to other fields in the same word of the
|
|
|
1034 structure, but to different bytes. */
|
|
|
1035 #define SLOW_BYTE_ACCESS 0
|
|
|
1036 #define SLOW_SHORT_ACCESS 0
|
|
|
1037
|
|
|
1038 /* Define this if most significant bit is lowest numbered
|
|
|
1039 in instructions that operate on numbered bit-fields. */
|
|
|
1040 #define BITS_BIG_ENDIAN 0
|
|
|
1041
|
|
|
1042 /* Define this if most significant byte of a word is the lowest numbered.
|
|
|
1043 We can't access bytes but if we could we would in the Big Endian order. */
|
|
|
1044 #define BYTES_BIG_ENDIAN 0
|
|
|
1045
|
|
|
1046 /* Define this if most significant word of a multiword number is numbered. */
|
|
|
1047 #define WORDS_BIG_ENDIAN 0
|
|
|
1048
|
|
|
1049 /* number of bits in an addressable storage unit */
|
|
|
1050 #define BITS_PER_UNIT 8
|
|
|
1051
|
|
|
1052 /* Width in bits of a "word", which is the contents of a machine register.
|
|
|
1053 Note that this is not necessarily the width of data type `int';
|
|
|
1054 if using 16-bit ints on a 68000, this would still be 32.
|
|
|
1055 But on a machine with 16-bit registers, this would be 16. */
|
|
|
1056 #define BITS_PER_WORD 32
|
|
|
1057
|
|
|
1058 /* Width of a word, in units (bytes). */
|
|
|
1059 #define UNITS_PER_WORD 4
|
|
|
1060
|
|
|
1061 /* Width in bits of a pointer.
|
|
|
1062 See also the macro `Pmode1' defined below. */
|
|
|
1063 #define POINTER_SIZE 32
|
|
|
1064
|
|
|
1065 /* Allocation boundary (in *bits*) for storing pointers in memory. */
|
|
|
1066 #define POINTER_BOUNDARY 32
|
|
|
1067
|
|
|
1068 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
|
|
|
1069 #define PARM_BOUNDARY 32
|
|
|
1070
|
|
|
1071 /* Boundary (in *bits*) on which stack pointer should be aligned. */
|
|
|
1072 #define STACK_BOUNDARY 32
|
|
|
1073
|
|
|
1074 /* Allocation boundary (in *bits*) for the code of a function. */
|
|
|
1075 #define FUNCTION_BOUNDARY 32
|
|
|
1076
|
|
|
1077 /* Alignment of field after `int : 0' in a structure. */
|
|
|
1078 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
|
|
|
1079
|
|
|
1080 /* No data type wants to be aligned rounder than this. */
|
|
|
1081 #define BIGGEST_ALIGNMENT 32
|
|
|
1082
|
|
|
1083 /* Define this if move instructions will actually fail to work
|
|
|
1084 when given unaligned data. */
|
|
|
1085 #define STRICT_ALIGNMENT 1
|
|
|
1086
|
|
|
1087 /* (shell-command "rm c-decl.o stor-layout.o")
|
|
|
1088 * never define PCC_BITFIELD_TYPE_MATTERS
|
|
|
1089 * really cause some alignment problem
|
|
|
1090 */
|
|
|
1091
|
|
|
1092 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
|
|
|
1093 BITS_PER_UNIT)
|
|
|
1094
|
|
|
1095 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
|
|
|
1096 BITS_PER_UNIT)
|
|
|
1097
|
|
|
1098
|
|
|
1099 /* what is the 'type' of size_t */
|
|
|
1100 #define SIZE_TYPE "long unsigned int"
|
|
|
1101
|
|
|
1102 /* Define this as 1 if `char' should by default be signed; else as 0. */
|
|
|
1103 #define DEFAULT_SIGNED_CHAR 1
|
|
|
1104 #define FLOAT_TYPE_SIZE BITS_PER_WORD
|
|
|
1105 #define SHORT_TYPE_SIZE 16
|
|
|
1106 #define CHAR_TYPE_SIZE 8
|
|
|
1107 #define INT_TYPE_SIZE 32
|
|
|
1108 #define LONG_TYPE_SIZE 32
|
|
|
1109 #define LONG_LONG_TYPE_SIZE 64
|
|
|
1110
|
|
|
1111 /* Note: Fix this to depend on target switch. -- lev */
|
|
|
1112
|
|
|
1113 /* Note: Try to implement double and force long double. -- tonyko
|
|
|
1114 * #define __DOUBLES_ARE_FLOATS__
|
|
|
1115 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
|
|
|
1116 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
|
|
|
1117 * #define DOUBLES_ARE_FLOATS 1
|
|
|
1118 */
|
|
|
1119
|
|
|
1120 #define DOUBLE_TYPE_SIZE 64
|
|
|
1121 #define LONG_DOUBLE_TYPE_SIZE 64
|
|
|
1122
|
|
|
1123 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
|
|
|
1124 A macro to update M and UNSIGNEDP when an object whose type is
|
|
|
1125 TYPE and which has the specified mode and signedness is to be
|
|
|
1126 stored in a register. This macro is only called when TYPE is a
|
|
|
1127 scalar type.
|
|
|
1128
|
|
|
1129 On most RISC machines, which only have operations that operate on
|
|
|
1130 a full register, define this macro to set M to `word_mode' if M is
|
|
|
1131 an integer mode narrower than `BITS_PER_WORD'. In most cases,
|
|
|
1132 only integer modes should be widened because wider-precision
|
|
|
1133 floating-point operations are usually more expensive than their
|
|
|
1134 narrower counterparts.
|
|
|
1135
|
|
|
1136 For most machines, the macro definition does not change UNSIGNEDP.
|
|
|
1137 However, some machines, have instructions that preferentially
|
|
|
1138 handle either signed or unsigned quantities of certain modes. For
|
|
|
1139 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
|
|
|
1140 instructions sign-extend the result to 64 bits. On such machines,
|
|
|
1141 set UNSIGNEDP according to which kind of extension is more
|
|
|
1142 efficient.
|
|
|
1143
|
|
|
1144 Do not define this macro if it would never modify M.*/
|
|
|
1145
|
|
|
1146 #define BFIN_PROMOTE_MODE_P(MODE) \
|
|
|
1147 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
|
|
|
1148 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
|
|
|
1149
|
|
|
1150 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
|
|
|
1151 if (BFIN_PROMOTE_MODE_P(MODE)) \
|
|
|
1152 { \
|
|
|
1153 if (MODE == QImode) \
|
|
|
1154 UNSIGNEDP = 1; \
|
|
|
1155 else if (MODE == HImode) \
|
|
|
1156 UNSIGNEDP = 0; \
|
|
|
1157 (MODE) = SImode; \
|
|
|
1158 }
|
|
|
1159
|
|
|
1160 /* Describing Relative Costs of Operations */
|
|
|
1161
|
|
|
1162 /* Do not put function addr into constant pool */
|
|
|
1163 #define NO_FUNCTION_CSE 1
|
|
|
1164
|
|
|
1165 /* A C expression for the cost of moving data from a register in class FROM to
|
|
|
1166 one in class TO. The classes are expressed using the enumeration values
|
|
|
1167 such as `GENERAL_REGS'. A value of 2 is the default; other values are
|
|
|
1168 interpreted relative to that.
|
|
|
1169
|
|
|
1170 It is not required that the cost always equal 2 when FROM is the same as TO;
|
|
|
1171 on some machines it is expensive to move between registers if they are not
|
|
|
1172 general registers. */
|
|
|
1173
|
|
|
1174 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
|
|
|
1175 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
|
|
|
1176
|
|
|
1177 /* A C expression for the cost of moving data of mode M between a
|
|
|
1178 register and memory. A value of 2 is the default; this cost is
|
|
|
1179 relative to those in `REGISTER_MOVE_COST'.
|
|
|
1180
|
|
|
1181 If moving between registers and memory is more expensive than
|
|
|
1182 between two registers, you should define this macro to express the
|
|
|
1183 relative cost. */
|
|
|
1184
|
|
|
1185 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
|
|
|
1186 bfin_memory_move_cost ((MODE), (CLASS), (IN))
|
|
|
1187
|
|
|
1188 /* Specify the machine mode that this machine uses
|
|
|
1189 for the index in the tablejump instruction. */
|
|
|
1190 #define CASE_VECTOR_MODE SImode
|
|
|
1191
|
|
|
1192 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
|
|
|
1193
|
|
|
1194 /* Define if operations between registers always perform the operation
|
|
|
1195 on the full register even if a narrower mode is specified.
|
|
|
1196 #define WORD_REGISTER_OPERATIONS
|
|
|
1197 */
|
|
|
1198
|
|
|
1199 /* Evaluates to true if A and B are mac flags that can be used
|
|
|
1200 together in a single multiply insn. That is the case if they are
|
|
|
1201 both the same flag not involving M, or if one is a combination of
|
|
|
1202 the other with M. */
|
|
|
1203 #define MACFLAGS_MATCH_P(A, B) \
|
|
|
1204 ((A) == (B) \
|
|
|
1205 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
|
|
|
1206 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
|
|
|
1207 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
|
|
|
1208 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
|
|
|
1209
|
|
|
1210 /* Switch into a generic section. */
|
|
|
1211 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
|
|
|
1212
|
|
|
1213 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
|
|
|
1214 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
|
|
|
1215
|
|
|
1216 typedef enum sections {
|
|
|
1217 CODE_DIR,
|
|
|
1218 DATA_DIR,
|
|
|
1219 LAST_SECT_NM
|
|
|
1220 } SECT_ENUM_T;
|
|
|
1221
|
|
|
1222 typedef enum directives {
|
|
|
1223 LONG_CONST_DIR,
|
|
|
1224 SHORT_CONST_DIR,
|
|
|
1225 BYTE_CONST_DIR,
|
|
|
1226 SPACE_DIR,
|
|
|
1227 INIT_DIR,
|
|
|
1228 LAST_DIR_NM
|
|
|
1229 } DIR_ENUM_T;
|
|
|
1230
|
|
|
1231 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \
|
|
|
1232 ((C) == ';' \
|
|
|
1233 || ((C) == '|' && (STR)[1] == '|'))
|
|
|
1234
|
|
|
1235 #define TEXT_SECTION_ASM_OP ".text;"
|
|
|
1236 #define DATA_SECTION_ASM_OP ".data;"
|
|
|
1237
|
|
|
1238 #define ASM_APP_ON ""
|
|
|
1239 #define ASM_APP_OFF ""
|
|
|
1240
|
|
|
1241 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
|
|
|
1242 do { fputs (".global ", FILE); \
|
|
|
1243 assemble_name (FILE, NAME); \
|
|
|
1244 fputc (';',FILE); \
|
|
|
1245 fputc ('\n',FILE); \
|
|
|
1246 } while (0)
|
|
|
1247
|
|
|
1248 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
|
|
|
1249 do { \
|
|
|
1250 fputs (".type ", FILE); \
|
|
|
1251 assemble_name (FILE, NAME); \
|
|
|
1252 fputs (", STT_FUNC", FILE); \
|
|
|
1253 fputc (';',FILE); \
|
|
|
1254 fputc ('\n',FILE); \
|
|
|
1255 ASM_OUTPUT_LABEL(FILE, NAME); \
|
|
|
1256 } while (0)
|
|
|
1257
|
|
|
1258 #define ASM_OUTPUT_LABEL(FILE, NAME) \
|
|
|
1259 do { assemble_name (FILE, NAME); \
|
|
|
1260 fputs (":\n",FILE); \
|
|
|
1261 } while (0)
|
|
|
1262
|
|
|
1263 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
|
|
|
1264 do { fprintf (FILE, "_%s", NAME); \
|
|
|
1265 } while (0)
|
|
|
1266
|
|
|
1267 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
|
|
|
1268 do { char __buf[256]; \
|
|
|
1269 fprintf (FILE, "\t.dd\t"); \
|
|
|
1270 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
|
|
|
1271 assemble_name (FILE, __buf); \
|
|
|
1272 fputc (';', FILE); \
|
|
|
1273 fputc ('\n', FILE); \
|
|
|
1274 } while (0)
|
|
|
1275
|
|
|
1276 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
|
|
|
1277 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
|
|
|
1278
|
|
|
1279 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
|
|
|
1280 do { \
|
|
|
1281 char __buf[256]; \
|
|
|
1282 fprintf (FILE, "\t.dd\t"); \
|
|
|
1283 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
|
|
|
1284 assemble_name (FILE, __buf); \
|
|
|
1285 fputs (" - ", FILE); \
|
|
|
1286 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
|
|
|
1287 assemble_name (FILE, __buf); \
|
|
|
1288 fputc (';', FILE); \
|
|
|
1289 fputc ('\n', FILE); \
|
|
|
1290 } while (0)
|
|
|
1291
|
|
|
1292 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
|
|
|
1293 do { \
|
|
|
1294 if ((LOG) != 0) \
|
|
|
1295 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
|
|
|
1296 } while (0)
|
|
|
1297
|
|
|
1298 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
|
|
|
1299 do { \
|
|
|
1300 asm_output_skip (FILE, SIZE); \
|
|
|
1301 } while (0)
|
|
|
1302
|
|
|
1303 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
|
|
|
1304 do { \
|
|
|
1305 switch_to_section (data_section); \
|
|
|
1306 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
|
|
|
1307 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
|
|
|
1308 ASM_OUTPUT_LABEL (FILE, NAME); \
|
|
|
1309 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
|
|
|
1310 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
|
|
|
1311 } while (0)
|
|
|
1312
|
|
|
1313 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
|
|
|
1314 do { \
|
|
|
1315 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
|
|
|
1316 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
|
|
|
1317
|
|
|
1318 #define ASM_COMMENT_START "//"
|
|
|
1319
|
|
|
1320 #define FUNCTION_PROFILER(FILE, LABELNO) \
|
|
|
1321 do { \
|
|
|
1322 fprintf (FILE, "\tCALL __mcount;\n"); \
|
|
|
1323 } while(0)
|
|
|
1324
|
|
|
1325 #undef NO_PROFILE_COUNTERS
|
|
|
1326 #define NO_PROFILE_COUNTERS 1
|
|
|
1327
|
|
|
1328 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO])
|
|
|
1329 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO])
|
|
|
1330
|
|
|
1331 extern struct rtx_def *bfin_compare_op0, *bfin_compare_op1;
|
|
|
1332 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx;
|
|
|
1333
|
|
|
1334 /* This works for GAS and some other assemblers. */
|
|
|
1335 #define SET_ASM_OP ".set "
|
|
|
1336
|
|
|
1337 /* DBX register number for a given compiler register number */
|
|
|
1338 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
|
|
|
1339
|
|
|
1340 #define SIZE_ASM_OP "\t.size\t"
|
|
|
1341
|
|
|
1342 extern int splitting_for_sched;
|
|
|
1343
|
|
|
1344 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
|
|
|
1345
|
|
|
1346 #endif /* _BFIN_CONFIG */
|
