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1 ;; Predicate definitions for the Blackfin.
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2 ;; Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
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3 ;; Contributed by Analog Devices.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify
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8 ;; it under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful,
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13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 ;; GNU General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; Return nonzero iff OP is one of the integer constants 1 or 2.
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22 (define_predicate "pos_scale_operand"
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23 (and (match_code "const_int")
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24 (match_test "INTVAL (op) == 1 || INTVAL (op) == 2")))
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25
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26 ;; Return nonzero iff OP is one of the integer constants 2 or 4.
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27 (define_predicate "scale_by_operand"
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28 (and (match_code "const_int")
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29 (match_test "INTVAL (op) == 2 || INTVAL (op) == 4")))
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30
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31 ;; Return nonzero if OP is a constant that consists of two parts; lower
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32 ;; bits all zero and upper bits all ones. In this case, we can perform
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33 ;; an AND operation with a sequence of two shifts. Don't return nonzero
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34 ;; if the constant would be cheap to load.
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35 (define_predicate "highbits_operand"
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36 (and (match_code "const_int")
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37 (match_test "log2constp (-INTVAL (op)) && !satisfies_constraint_Ks7 (op)")))
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38
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39 ;; Return nonzero if OP is suitable as a right-hand side operand for an
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40 ;; andsi3 operation.
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41 (define_predicate "rhs_andsi3_operand"
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42 (ior (match_operand 0 "register_operand")
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43 (and (match_code "const_int")
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44 (match_test "log2constp (~INTVAL (op)) || INTVAL (op) == 255 || INTVAL (op) == 65535"))))
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45
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46 ;; Return nonzero if OP is a register or a constant with exactly one bit
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47 ;; set.
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48 (define_predicate "regorlog2_operand"
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49 (ior (match_operand 0 "register_operand")
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50 (and (match_code "const_int")
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51 (match_test "log2constp (INTVAL (op))"))))
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52
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53 ;; Return nonzero if OP is a register or an integer constant.
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54 (define_predicate "reg_or_const_int_operand"
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55 (ior (match_operand 0 "register_operand")
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56 (match_code "const_int")))
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57
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58 (define_predicate "const01_operand"
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59 (and (match_code "const_int")
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60 (match_test "op == const0_rtx || op == const1_rtx")))
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61
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62 (define_predicate "vec_shift_operand"
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63 (ior (and (match_code "const_int")
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64 (match_test "INTVAL (op) >= -16 && INTVAL (op) < 15"))
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65 (match_operand 0 "register_operand")))
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66
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67 ;; Like register_operand, but make sure that hard regs have a valid mode.
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68 (define_predicate "valid_reg_operand"
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69 (match_operand 0 "register_operand")
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70 {
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71 if (GET_CODE (op) == SUBREG)
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72 op = SUBREG_REG (op);
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73 if (REGNO (op) < FIRST_PSEUDO_REGISTER)
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74 return HARD_REGNO_MODE_OK (REGNO (op), mode);
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75 return 1;
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76 })
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77
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78 ;; Return nonzero if OP is a D register.
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79 (define_predicate "d_register_operand"
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80 (and (match_code "reg")
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81 (match_test "D_REGNO_P (REGNO (op))")))
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82
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83 ;; Return nonzero if OP is a LC register.
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84 (define_predicate "lc_register_operand"
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85 (and (match_code "reg")
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86 (match_test "REGNO (op) == REG_LC0 || REGNO (op) == REG_LC1")))
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87
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88 ;; Return nonzero if OP is a LT register.
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89 (define_predicate "lt_register_operand"
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90 (and (match_code "reg")
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91 (match_test "REGNO (op) == REG_LT0 || REGNO (op) == REG_LT1")))
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92
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93 ;; Return nonzero if OP is a LB register.
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94 (define_predicate "lb_register_operand"
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95 (and (match_code "reg")
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96 (match_test "REGNO (op) == REG_LB0 || REGNO (op) == REG_LB1")))
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97
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98 ;; Return nonzero if OP is a register or a 7-bit signed constant.
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99 (define_predicate "reg_or_7bit_operand"
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100 (ior (match_operand 0 "register_operand")
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101 (and (match_code "const_int")
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102 (match_test "satisfies_constraint_Ks7 (op)"))))
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103
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104 ;; Return nonzero if OP is a register other than DREG and PREG.
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105 (define_predicate "nondp_register_operand"
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106 (match_operand 0 "register_operand")
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107 {
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108 unsigned int regno;
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109 if (GET_CODE (op) == SUBREG)
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110 op = SUBREG_REG (op);
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111
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112 regno = REGNO (op);
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113 return (regno >= FIRST_PSEUDO_REGISTER || !DP_REGNO_P (regno));
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114 })
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115
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116 ;; Return nonzero if OP is a register other than DREG and PREG, or MEM.
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117 (define_predicate "nondp_reg_or_memory_operand"
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118 (ior (match_operand 0 "nondp_register_operand")
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119 (match_operand 0 "memory_operand")))
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120
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121 ;; Return nonzero if OP is a register or, when negated, a 7-bit signed
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122 ;; constant.
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123 (define_predicate "reg_or_neg7bit_operand"
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124 (ior (match_operand 0 "register_operand")
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125 (and (match_code "const_int")
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126 (match_test "satisfies_constraint_KN7 (op)"))))
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127
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128 ;; Used for secondary reloads, this function returns 1 if OP is of the
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129 ;; form (plus (fp) (const_int)).
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130 (define_predicate "fp_plus_const_operand"
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131 (match_code "plus")
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132 {
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133 rtx op1, op2;
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134
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135 op1 = XEXP (op, 0);
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136 op2 = XEXP (op, 1);
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137 return (REG_P (op1)
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138 && (REGNO (op1) == FRAME_POINTER_REGNUM
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139 || REGNO (op1) == STACK_POINTER_REGNUM)
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140 && GET_CODE (op2) == CONST_INT);
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141 })
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142
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143 ;; Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
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144 ;; possibly with an offset.
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145 (define_predicate "symbolic_operand"
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146 (ior (match_code "symbol_ref,label_ref")
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147 (and (match_code "const")
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148 (match_test "GET_CODE (XEXP (op,0)) == PLUS
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149 && (GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
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150 || GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF)
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151 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT"))))
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152
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153 ;; Returns 1 if OP is a plain constant or matched by symbolic_operand.
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154 (define_predicate "symbolic_or_const_operand"
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155 (ior (match_code "const_int,const_double")
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156 (match_operand 0 "symbolic_operand")))
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157
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158 ;; Returns 1 if OP is a SYMBOL_REF.
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159 (define_predicate "symbol_ref_operand"
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160 (match_code "symbol_ref"))
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161
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162 ;; True for any non-virtual or eliminable register. Used in places where
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163 ;; instantiation of such a register may cause the pattern to not be recognized.
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164 (define_predicate "register_no_elim_operand"
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165 (match_operand 0 "register_operand")
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166 {
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167 if (GET_CODE (op) == SUBREG)
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168 op = SUBREG_REG (op);
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169 return !(op == arg_pointer_rtx
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170 || op == frame_pointer_rtx
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171 || (REGNO (op) >= FIRST_PSEUDO_REGISTER
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172 && REGNO (op) <= LAST_VIRTUAL_REGISTER));
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173 })
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174
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175 ;; Test for an operator valid in a conditional branch
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176 (define_predicate "bfin_cbranch_operator"
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177 (match_code "eq,ne"))
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178
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179 ;; The following two are used to compute the addrtype attribute. They return
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180 ;; true if passed a memory address usable for a 16-bit load or store using a
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181 ;; P or I register, respectively. If neither matches, we know we have a
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182 ;; 32-bit instruction.
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183 (define_predicate "mem_p_address_operand"
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184 (match_code "mem")
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185 {
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186 if (effective_address_32bit_p (op, mode))
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187 return 0;
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188 op = XEXP (op, 0);
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189 if (GET_CODE (op) == PLUS || GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
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190 op = XEXP (op, 0);
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191 gcc_assert (REG_P (op));
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192 return PREG_P (op);
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193 })
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194
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195 (define_predicate "mem_i_address_operand"
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196 (match_code "mem")
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197 {
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198 if (effective_address_32bit_p (op, mode))
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199 return 0;
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200 op = XEXP (op, 0);
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201 if (GET_CODE (op) == PLUS || GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
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202 op = XEXP (op, 0);
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203 gcc_assert (REG_P (op));
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204 return IREG_P (op);
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205 })
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