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1 ;; Predicate definitions for Renesas H8/300.
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2 ;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; Return true if OP is a valid source operand for an integer move
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21 ;; instruction.
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22
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23 (define_predicate "general_operand_src"
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24 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")
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25 {
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26 if (GET_MODE (op) == mode
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27 && GET_CODE (op) == MEM
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28 && GET_CODE (XEXP (op, 0)) == POST_INC)
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29 return 1;
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30 return general_operand (op, mode);
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31 })
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32
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33 ;; Return true if OP is a valid destination operand for an integer
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34 ;; move instruction.
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35
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36 (define_predicate "general_operand_dst"
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37 (match_code "subreg,reg,mem")
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38 {
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39 if (GET_MODE (op) == mode
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40 && GET_CODE (op) == MEM
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41 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
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42 return 1;
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43 return general_operand (op, mode);
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44 })
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45
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46 ;; Likewise the second operand.
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47
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48 (define_predicate "h8300_src_operand"
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49 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")
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50 {
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51 if (TARGET_H8300SX)
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52 return general_operand (op, mode);
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53 return nonmemory_operand (op, mode);
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54 })
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55
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56 ;; Return true if OP is a suitable first operand for a general
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57 ;; arithmetic insn such as "add".
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58
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59 (define_predicate "h8300_dst_operand"
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60 (match_code "subreg,reg,mem")
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61 {
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62 if (TARGET_H8300SX)
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63 return nonimmediate_operand (op, mode);
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64 return register_operand (op, mode);
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65 })
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66
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67 ;; Check that an operand is either a register or an unsigned 4-bit
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68 ;; constant.
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69
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70 (define_predicate "nibble_operand"
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71 (match_code "const_int")
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72 {
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73 return (GET_CODE (op) == CONST_INT && TARGET_H8300SX
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74 && INTVAL (op) >= 0 && INTVAL (op) <= 15);
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75 })
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76
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77 ;; Check that an operand is either a register or an unsigned 4-bit
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78 ;; constant.
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79
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80 (define_predicate "reg_or_nibble_operand"
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81 (match_code "const_int,subreg,reg")
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82 {
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83 return (nibble_operand (op, mode) || register_operand (op, mode));
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84 })
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85
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86 ;; Return true if X is a shift operation of type H8SX_SHIFT_UNARY.
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87
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88 (define_predicate "h8sx_unary_shift_operator"
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89 (match_code "ashiftrt,lshiftrt,ashift,rotate")
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90 {
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91 return (BINARY_P (op) && NON_COMMUTATIVE_P (op)
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92 && (h8sx_classify_shift (GET_MODE (op), GET_CODE (op), XEXP (op, 1))
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93 == H8SX_SHIFT_UNARY));
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94 })
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95
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96 ;; Likewise H8SX_SHIFT_BINARY.
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97
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98 (define_predicate "h8sx_binary_shift_operator"
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99 (match_code "ashiftrt,lshiftrt,ashift")
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100 {
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101 return (BINARY_P (op) && NON_COMMUTATIVE_P (op)
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102 && (h8sx_classify_shift (GET_MODE (op), GET_CODE (op), XEXP (op, 1))
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103 == H8SX_SHIFT_BINARY));
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104 })
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105
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106 ;; Return true if OP is a binary operator in which it would be safe to
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107 ;; replace register operands with memory operands.
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108
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109 (define_predicate "h8sx_binary_memory_operator"
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110 (match_code "plus,minus,and,ior,xor,ashift,ashiftrt,lshiftrt,rotate")
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111 {
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112 if (!TARGET_H8300SX)
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113 return false;
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114
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115 if (GET_MODE (op) != QImode
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116 && GET_MODE (op) != HImode
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117 && GET_MODE (op) != SImode)
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118 return false;
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119
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120 switch (GET_CODE (op))
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121 {
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122 case PLUS:
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123 case MINUS:
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124 case AND:
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125 case IOR:
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126 case XOR:
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127 return true;
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128
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129 default:
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130 return h8sx_unary_shift_operator (op, mode);
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131 }
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132 })
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133
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134 ;; Like h8sx_binary_memory_operator, but applies to unary operators.
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135
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136 (define_predicate "h8sx_unary_memory_operator"
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137 (match_code "neg,not")
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138 {
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139 if (!TARGET_H8300SX)
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140 return false;
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141
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142 if (GET_MODE (op) != QImode
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143 && GET_MODE (op) != HImode
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144 && GET_MODE (op) != SImode)
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145 return false;
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146
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147 switch (GET_CODE (op))
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148 {
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149 case NEG:
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150 case NOT:
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151 return true;
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152
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153 default:
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154 return false;
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155 }
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156 })
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157
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158 ;; Return true if X is an ldm.l pattern. X is known to be parallel.
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159
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160 (define_predicate "h8300_ldm_parallel"
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161 (match_code "parallel")
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162 {
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163 return h8300_ldm_stm_parallel (XVEC (op, 0), 1, 0);
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164 })
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165
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166 ;; Likewise stm.l.
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167
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168 (define_predicate "h8300_stm_parallel"
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169 (match_code "parallel")
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170 {
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171 return h8300_ldm_stm_parallel (XVEC (op, 0), 0, 0);
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172 })
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173
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174 ;; Likewise rts/l and rte/l. Note that the .md pattern will check for
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175 ;; the return so there's no need to do that here.
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176
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177 (define_predicate "h8300_return_parallel"
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178 (match_code "parallel")
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179 {
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180 return h8300_ldm_stm_parallel (XVEC (op, 0), 1, 1);
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181 })
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182
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183 ;; Return true if OP is a constant that contains only one 1 in its
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184 ;; binary representation.
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185
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186 (define_predicate "single_one_operand"
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187 (match_code "const_int")
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188 {
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189 if (GET_CODE (op) == CONST_INT)
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190 {
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191 /* We really need to do this masking because 0x80 in QImode is
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192 represented as -128 for example. */
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193 if (exact_log2 (INTVAL (op) & GET_MODE_MASK (mode)) >= 0)
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194 return 1;
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195 }
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196
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197 return 0;
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198 })
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199
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200 ;; Return true if OP is a constant that contains only one 0 in its
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201 ;; binary representation.
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202
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203 (define_predicate "single_zero_operand"
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204 (match_code "const_int")
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205 {
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206 if (GET_CODE (op) == CONST_INT)
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207 {
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208 /* We really need to do this masking because 0x80 in QImode is
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209 represented as -128 for example. */
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210 if (exact_log2 (~INTVAL (op) & GET_MODE_MASK (mode)) >= 0)
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211 return 1;
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212 }
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213
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214 return 0;
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215 })
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216
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217 ;; Return true if OP is a valid call operand.
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218
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219 (define_predicate "call_insn_operand"
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220 (match_code "mem")
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221 {
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222 if (GET_CODE (op) == MEM)
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223 {
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224 rtx inside = XEXP (op, 0);
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225 if (register_operand (inside, Pmode))
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226 return 1;
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227 if (CONSTANT_ADDRESS_P (inside))
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228 return 1;
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229 }
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230 return 0;
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231 })
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232
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233 ;; Return true if OP is a valid call operand, and OP represents an
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234 ;; operand for a small call (4 bytes instead of 6 bytes).
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235
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236 (define_predicate "small_call_insn_operand"
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237 (match_code "mem")
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238 {
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239 if (GET_CODE (op) == MEM)
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240 {
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241 rtx inside = XEXP (op, 0);
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242
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243 /* Register indirect is a small call. */
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244 if (register_operand (inside, Pmode))
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245 return 1;
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246
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247 /* A call through the function vector is a small call too. */
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248 if (GET_CODE (inside) == SYMBOL_REF
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249 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
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250 return 1;
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251 }
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252 /* Otherwise it's a large call. */
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253 return 0;
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254 })
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255
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256 ;; Return true if OP is a valid jump operand.
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257
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258 (define_predicate "jump_address_operand"
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259 (match_code "reg,mem")
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260 {
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261 if (GET_CODE (op) == REG)
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262 return mode == Pmode;
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263
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264 if (GET_CODE (op) == MEM)
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265 {
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266 rtx inside = XEXP (op, 0);
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267 if (register_operand (inside, Pmode))
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268 return 1;
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269 if (CONSTANT_ADDRESS_P (inside))
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270 return 1;
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271 }
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272 return 0;
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273 })
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274
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275 ;; Return 1 if an addition/subtraction of a constant integer can be
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276 ;; transformed into two consecutive adds/subs that are faster than the
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277 ;; straightforward way. Otherwise, return 0.
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278
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279 (define_predicate "two_insn_adds_subs_operand"
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280 (match_code "const_int")
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281 {
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282 if (TARGET_H8300SX)
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283 return 0;
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284
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285 if (GET_CODE (op) == CONST_INT)
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286 {
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287 HOST_WIDE_INT value = INTVAL (op);
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288
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289 /* Force VALUE to be positive so that we do not have to consider
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290 the negative case. */
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291 if (value < 0)
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292 value = -value;
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293 if (TARGET_H8300H || TARGET_H8300S)
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294 {
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295 /* A constant addition/subtraction takes 2 states in QImode,
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296 4 states in HImode, and 6 states in SImode. Thus, the
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297 only case we can win is when SImode is used, in which
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298 case, two adds/subs are used, taking 4 states. */
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299 if (mode == SImode
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300 && (value == 2 + 1
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301 || value == 4 + 1
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302 || value == 4 + 2
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303 || value == 4 + 4))
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304 return 1;
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305 }
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306 else
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307 {
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308 /* We do not profit directly by splitting addition or
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309 subtraction of 3 and 4. However, since these are
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310 implemented as a sequence of adds or subs, they do not
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311 clobber (cc0) unlike a sequence of add.b and add.x. */
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312 if (mode == HImode
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313 && (value == 2 + 1
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314 || value == 2 + 2))
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315 return 1;
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316 }
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317 }
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318
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319 return 0;
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320 })
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321
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322 ;; Recognize valid operands for bit-field instructions.
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323
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324 (define_predicate "bit_operand"
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325 (match_code "reg,subreg,mem")
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326 {
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327 /* We can accept any nonimmediate operand, except that MEM operands must
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328 be limited to those that use addresses valid for the 'U' constraint. */
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329 if (!nonimmediate_operand (op, mode))
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330 return 0;
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331
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332 /* H8SX accepts pretty much anything here. */
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333 if (TARGET_H8300SX)
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334 return 1;
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335
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336 /* Accept any mem during RTL generation. Otherwise, the code that does
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337 insv and extzv will think that we cannot handle memory. However,
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338 to avoid reload problems, we only accept 'U' MEM operands after RTL
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339 generation. This means that any named pattern which uses this predicate
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340 must force its operands to match 'U' before emitting RTL. */
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341
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342 if (GET_CODE (op) == REG)
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343 return 1;
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344 if (GET_CODE (op) == SUBREG)
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345 return 1;
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346 return (GET_CODE (op) == MEM
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347 && OK_FOR_U (op));
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348 })
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349
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350 ;; Return nonzero if OP is a MEM suitable for bit manipulation insns.
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351
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352 (define_predicate "bit_memory_operand"
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353 (match_code "mem")
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354 {
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355 return (GET_CODE (op) == MEM
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356 && OK_FOR_U (op));
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357 })
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358
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359 ;; Return nonzero if X is a stack pointer.
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360
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361 (define_predicate "stack_pointer_operand"
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362 (match_code "reg")
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363 {
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364 return op == stack_pointer_rtx;
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365 })
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366
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367 ;; Return nonzero if X is a constant whose absolute value is greater
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368 ;; than 2.
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369
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370 (define_predicate "const_int_gt_2_operand"
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371 (match_code "const_int")
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372 {
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373 return (GET_CODE (op) == CONST_INT
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374 && abs (INTVAL (op)) > 2);
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375 })
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376
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377 ;; Return nonzero if X is a constant whose absolute value is no
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378 ;; smaller than 8.
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379
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380 (define_predicate "const_int_ge_8_operand"
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381 (match_code "const_int")
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382 {
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383 return (GET_CODE (op) == CONST_INT
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384 && abs (INTVAL (op)) >= 8);
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385 })
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386
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387 ;; Return nonzero if X is a constant expressible in QImode.
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388
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389 (define_predicate "const_int_qi_operand"
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390 (match_code "const_int")
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391 {
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392 return (GET_CODE (op) == CONST_INT
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393 && (INTVAL (op) & 0xff) == INTVAL (op));
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394 })
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395
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396 ;; Return nonzero if X is a constant expressible in HImode.
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397
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398 (define_predicate "const_int_hi_operand"
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399 (match_code "const_int")
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400 {
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401 return (GET_CODE (op) == CONST_INT
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402 && (INTVAL (op) & 0xffff) == INTVAL (op));
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403 })
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404
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405 ;; Return nonzero if X is a constant suitable for inc/dec.
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406
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407 (define_predicate "incdec_operand"
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408 (match_code "const_int")
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409 {
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410 return (GET_CODE (op) == CONST_INT
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411 && (CONST_OK_FOR_M (INTVAL (op))
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412 || CONST_OK_FOR_O (INTVAL (op))));
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413 })
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414
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415 ;; Recognize valid operators for bit instructions.
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416
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417 (define_predicate "bit_operator"
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418 (match_code "xor,and,ior")
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419 {
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420 enum rtx_code code = GET_CODE (op);
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421
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422 return (code == XOR
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423 || code == AND
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424 || code == IOR);
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425 })
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426
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427 ;; Return nonzero if OP is a shift operator.
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428
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429 (define_predicate "nshift_operator"
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430 (match_code "ashiftrt,lshiftrt,ashift")
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431 {
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432 switch (GET_CODE (op))
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433 {
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434 case ASHIFTRT:
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435 case LSHIFTRT:
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436 case ASHIFT:
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437 return 1;
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438
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439 default:
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440 return 0;
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441 }
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442 })
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443
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444 ;; Return nonzero if X is either EQ or NE.
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445
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446 (define_predicate "eqne_operator"
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447 (match_code "eq,ne")
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448 {
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449 enum rtx_code code = GET_CODE (op);
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450
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451 return (code == EQ || code == NE);
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452 })
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453
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454 ;; Return nonzero if X is either GT or LE.
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455
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456 (define_predicate "gtle_operator"
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457 (match_code "gt,le,gtu,leu")
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458 {
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459 enum rtx_code code = GET_CODE (op);
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460
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461 return (code == GT || code == LE);
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462 })
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463
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464 ;; Return nonzero if X is either GTU or LEU.
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465
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466 (define_predicate "gtuleu_operator"
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467 (match_code "gtu,leu")
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468 {
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469 enum rtx_code code = GET_CODE (op);
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470
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471 return (code == GTU || code == LEU);
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472 })
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473
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474 ;; Return nonzero if X is either IOR or XOR.
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475
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|
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476 (define_predicate "iorxor_operator"
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477 (match_code "ior,xor")
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|
|
478 {
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|
|
479 enum rtx_code code = GET_CODE (op);
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480
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481 return (code == IOR || code == XOR);
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|
482 })
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