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1 ;; GCC machine description for i386 synchronization instructions.
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2 ;; Copyright (C) 2005, 2006, 2007, 2008, 2009
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3 ;; Free Software Foundation, Inc.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify
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8 ;; it under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful,
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13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 ;; GNU General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_mode_iterator IMODE [QI HI SI (DI "TARGET_64BIT")])
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22 (define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
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23 (define_mode_attr modeconstraint [(QI "q") (HI "r") (SI "r") (DI "r")])
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24 (define_mode_attr immconstraint [(QI "i") (HI "i") (SI "i") (DI "e")])
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25
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26 (define_mode_iterator CASMODE [QI HI SI (DI "TARGET_64BIT || TARGET_CMPXCHG8B")
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27 (TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
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28 (define_mode_iterator DCASMODE
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29 [(DI "!TARGET_64BIT && TARGET_CMPXCHG8B && !flag_pic")
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30 (TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
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31 (define_mode_attr doublemodesuffix [(DI "8") (TI "16")])
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32 (define_mode_attr DCASHMODE [(DI "SI") (TI "DI")])
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33
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34 (define_expand "memory_barrier"
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35 [(set (match_dup 0)
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36 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
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37 ""
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38 {
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39 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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40 MEM_VOLATILE_P (operands[0]) = 1;
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41
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42 if (!(TARGET_64BIT || TARGET_SSE2))
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43 {
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44 emit_insn (gen_memory_barrier_nosse (operands[0]));
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45 DONE;
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46 }
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47 })
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48
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49 (define_insn "memory_barrier_nosse"
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50 [(set (match_operand:BLK 0 "" "")
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51 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))
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52 (clobber (reg:CC FLAGS_REG))]
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53 "!(TARGET_64BIT || TARGET_SSE2)"
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54 "lock{%;| }or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}"
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55 [(set_attr "memory" "unknown")])
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56
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57 ;; ??? It would be possible to use cmpxchg8b on pentium for DImode
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58 ;; changes. It's complicated because the insn uses ecx:ebx as the
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59 ;; new value; note that the registers are reversed from the order
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60 ;; that they'd be in with (reg:DI 2 ecx). Similarly for TImode
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61 ;; data in 64-bit mode.
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62
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63 (define_expand "sync_compare_and_swap<mode>"
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64 [(parallel
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65 [(set (match_operand:CASMODE 0 "register_operand" "")
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66 (match_operand:CASMODE 1 "memory_operand" ""))
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67 (set (match_dup 1)
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68 (unspec_volatile:CASMODE
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69 [(match_dup 1)
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70 (match_operand:CASMODE 2 "register_operand" "")
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71 (match_operand:CASMODE 3 "register_operand" "")]
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72 UNSPECV_CMPXCHG))
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73 (clobber (reg:CC FLAGS_REG))])]
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74 "TARGET_CMPXCHG"
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75 {
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76 if ((<MODE>mode == DImode && !TARGET_64BIT) || <MODE>mode == TImode)
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77 {
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78 enum machine_mode hmode = <MODE>mode == DImode ? SImode : DImode;
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79 rtx low = simplify_gen_subreg (hmode, operands[3], <MODE>mode, 0);
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80 rtx high = simplify_gen_subreg (hmode, operands[3], <MODE>mode,
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81 GET_MODE_SIZE (hmode));
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82 low = force_reg (hmode, low);
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83 high = force_reg (hmode, high);
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84 if (<MODE>mode == DImode)
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85 {
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86 if (flag_pic && !cmpxchg8b_pic_memory_operand (operands[1], DImode))
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87 operands[1] = replace_equiv_address (operands[1],
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88 force_reg (Pmode,
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89 XEXP (operands[1],
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90 0)));
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91 emit_insn (gen_sync_double_compare_and_swapdi
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92 (operands[0], operands[1], operands[2], low, high));
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93 }
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94 else if (<MODE>mode == TImode)
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95 emit_insn (gen_sync_double_compare_and_swapti
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96 (operands[0], operands[1], operands[2], low, high));
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97 else
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98 gcc_unreachable ();
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99 DONE;
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100 }
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101 })
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102
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103 (define_insn "*sync_compare_and_swap<mode>"
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104 [(set (match_operand:IMODE 0 "register_operand" "=a")
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105 (match_operand:IMODE 1 "memory_operand" "+m"))
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106 (set (match_dup 1)
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107 (unspec_volatile:IMODE
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108 [(match_dup 1)
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109 (match_operand:IMODE 2 "register_operand" "a")
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110 (match_operand:IMODE 3 "register_operand" "<modeconstraint>")]
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111 UNSPECV_CMPXCHG))
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112 (clobber (reg:CC FLAGS_REG))]
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113 "TARGET_CMPXCHG"
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114 "lock{%;| }cmpxchg{<modesuffix>}\t{%3, %1|%1, %3}")
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115
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116 (define_insn "sync_double_compare_and_swap<mode>"
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117 [(set (match_operand:DCASMODE 0 "register_operand" "=A")
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118 (match_operand:DCASMODE 1 "memory_operand" "+m"))
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119 (set (match_dup 1)
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120 (unspec_volatile:DCASMODE
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121 [(match_dup 1)
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122 (match_operand:DCASMODE 2 "register_operand" "A")
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123 (match_operand:<DCASHMODE> 3 "register_operand" "b")
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124 (match_operand:<DCASHMODE> 4 "register_operand" "c")]
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125 UNSPECV_CMPXCHG))
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126 (clobber (reg:CC FLAGS_REG))]
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127 ""
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128 "lock{%;| }cmpxchg<doublemodesuffix>b\t%1")
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129
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130 ;; Theoretically we'd like to use constraint "r" (any reg) for operand
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131 ;; 3, but that includes ecx. If operand 3 and 4 are the same (like when
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132 ;; the input is -1LL) GCC might chose to allocate operand 3 to ecx, like
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133 ;; operand 4. This breaks, as the xchg will move the PIC register contents
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134 ;; to %ecx then --> boom. Operands 3 and 4 really need to be different
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135 ;; registers, which in this case means operand 3 must not be ecx.
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136 ;; Instead of playing tricks with fake early clobbers or the like we
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137 ;; just enumerate all regs possible here, which (as this is !TARGET_64BIT)
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138 ;; are just esi and edi.
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139 (define_insn "*sync_double_compare_and_swapdi_pic"
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140 [(set (match_operand:DI 0 "register_operand" "=A")
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141 (match_operand:DI 1 "cmpxchg8b_pic_memory_operand" "+m"))
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142 (set (match_dup 1)
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143 (unspec_volatile:DI
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144 [(match_dup 1)
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145 (match_operand:DI 2 "register_operand" "A")
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146 (match_operand:SI 3 "register_operand" "SD")
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147 (match_operand:SI 4 "register_operand" "c")]
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148 UNSPECV_CMPXCHG))
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149 (clobber (reg:CC FLAGS_REG))]
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150 "!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
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151 "xchg{l}\t%%ebx, %3\;lock{%;| }cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3")
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152
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153 (define_expand "sync_compare_and_swap_cc<mode>"
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154 [(parallel
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155 [(set (match_operand:CASMODE 0 "register_operand" "")
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156 (match_operand:CASMODE 1 "memory_operand" ""))
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157 (set (match_dup 1)
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158 (unspec_volatile:CASMODE
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159 [(match_dup 1)
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160 (match_operand:CASMODE 2 "register_operand" "")
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161 (match_operand:CASMODE 3 "register_operand" "")]
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162 UNSPECV_CMPXCHG))
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163 (set (match_dup 4)
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164 (compare:CCZ
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165 (unspec_volatile:CASMODE
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166 [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG)
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167 (match_dup 2)))])]
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168 "TARGET_CMPXCHG"
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169 {
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170 operands[4] = gen_rtx_REG (CCZmode, FLAGS_REG);
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171 ix86_compare_op0 = operands[3];
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172 ix86_compare_op1 = NULL;
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173 ix86_compare_emitted = operands[4];
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174 if ((<MODE>mode == DImode && !TARGET_64BIT) || <MODE>mode == TImode)
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175 {
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176 enum machine_mode hmode = <MODE>mode == DImode ? SImode : DImode;
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177 rtx low = simplify_gen_subreg (hmode, operands[3], <MODE>mode, 0);
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178 rtx high = simplify_gen_subreg (hmode, operands[3], <MODE>mode,
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179 GET_MODE_SIZE (hmode));
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180 low = force_reg (hmode, low);
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181 high = force_reg (hmode, high);
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182 if (<MODE>mode == DImode)
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183 {
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184 if (flag_pic && !cmpxchg8b_pic_memory_operand (operands[1], DImode))
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185 operands[1] = replace_equiv_address (operands[1],
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186 force_reg (Pmode,
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187 XEXP (operands[1],
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188 0)));
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189 emit_insn (gen_sync_double_compare_and_swap_ccdi
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190 (operands[0], operands[1], operands[2], low, high));
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191 }
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192 else if (<MODE>mode == TImode)
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193 emit_insn (gen_sync_double_compare_and_swap_ccti
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194 (operands[0], operands[1], operands[2], low, high));
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195 else
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196 gcc_unreachable ();
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197 DONE;
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198 }
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199 })
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200
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201 (define_insn "*sync_compare_and_swap_cc<mode>"
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202 [(set (match_operand:IMODE 0 "register_operand" "=a")
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203 (match_operand:IMODE 1 "memory_operand" "+m"))
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204 (set (match_dup 1)
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205 (unspec_volatile:IMODE
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206 [(match_dup 1)
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207 (match_operand:IMODE 2 "register_operand" "a")
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208 (match_operand:IMODE 3 "register_operand" "<modeconstraint>")]
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209 UNSPECV_CMPXCHG))
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210 (set (reg:CCZ FLAGS_REG)
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211 (compare:CCZ
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212 (unspec_volatile:IMODE
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213 [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG)
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214 (match_dup 2)))]
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215 "TARGET_CMPXCHG"
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216 "lock{%;| }cmpxchg{<modesuffix>}\t{%3, %1|%1, %3}")
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217
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218 (define_insn "sync_double_compare_and_swap_cc<mode>"
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219 [(set (match_operand:DCASMODE 0 "register_operand" "=A")
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220 (match_operand:DCASMODE 1 "memory_operand" "+m"))
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221 (set (match_dup 1)
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222 (unspec_volatile:DCASMODE
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223 [(match_dup 1)
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224 (match_operand:DCASMODE 2 "register_operand" "A")
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225 (match_operand:<DCASHMODE> 3 "register_operand" "b")
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226 (match_operand:<DCASHMODE> 4 "register_operand" "c")]
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227 UNSPECV_CMPXCHG))
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228 (set (reg:CCZ FLAGS_REG)
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229 (compare:CCZ
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230 (unspec_volatile:DCASMODE
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231 [(match_dup 1) (match_dup 2) (match_dup 3) (match_dup 4)]
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232 UNSPECV_CMPXCHG)
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233 (match_dup 2)))]
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234 ""
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235 "lock{%;| }cmpxchg<doublemodesuffix>b\t%1")
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236
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237 ;; See above for the explanation of using the constraint "SD" for
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238 ;; operand 3.
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239 (define_insn "*sync_double_compare_and_swap_ccdi_pic"
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240 [(set (match_operand:DI 0 "register_operand" "=A")
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241 (match_operand:DI 1 "cmpxchg8b_pic_memory_operand" "+m"))
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242 (set (match_dup 1)
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243 (unspec_volatile:DI
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244 [(match_dup 1)
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245 (match_operand:DI 2 "register_operand" "A")
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246 (match_operand:SI 3 "register_operand" "SD")
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247 (match_operand:SI 4 "register_operand" "c")]
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248 UNSPECV_CMPXCHG))
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249 (set (reg:CCZ FLAGS_REG)
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250 (compare:CCZ
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251 (unspec_volatile:DI
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252 [(match_dup 1) (match_dup 2) (match_dup 3) (match_dup 4)]
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253 UNSPECV_CMPXCHG)
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254 (match_dup 2)))]
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255 "!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
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256 "xchg{l}\t%%ebx, %3\;lock{%;| }cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3")
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257
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258 (define_insn "sync_old_add<mode>"
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259 [(set (match_operand:IMODE 0 "register_operand" "=<modeconstraint>")
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260 (unspec_volatile:IMODE
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261 [(match_operand:IMODE 1 "memory_operand" "+m")] UNSPECV_XCHG))
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262 (set (match_dup 1)
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263 (plus:IMODE (match_dup 1)
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264 (match_operand:IMODE 2 "register_operand" "0")))
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265 (clobber (reg:CC FLAGS_REG))]
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266 "TARGET_XADD"
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267 "lock{%;| }xadd{<modesuffix>}\t{%0, %1|%1, %0}")
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268
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269 ;; Recall that xchg implicitly sets LOCK#, so adding it again wastes space.
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270 (define_insn "sync_lock_test_and_set<mode>"
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271 [(set (match_operand:IMODE 0 "register_operand" "=<modeconstraint>")
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272 (unspec_volatile:IMODE
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273 [(match_operand:IMODE 1 "memory_operand" "+m")] UNSPECV_XCHG))
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274 (set (match_dup 1)
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275 (match_operand:IMODE 2 "register_operand" "0"))]
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276 ""
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277 "xchg{<modesuffix>}\t{%1, %0|%0, %1}")
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278
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279 (define_insn "sync_add<mode>"
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280 [(set (match_operand:IMODE 0 "memory_operand" "+m")
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281 (unspec_volatile:IMODE
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282 [(plus:IMODE (match_dup 0)
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283 (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
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284 UNSPECV_LOCK))
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285 (clobber (reg:CC FLAGS_REG))]
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286 ""
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287 {
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288 if (TARGET_USE_INCDEC)
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289 {
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290 if (operands[1] == const1_rtx)
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291 return "lock{%;| }inc{<modesuffix>}\t%0";
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292 if (operands[1] == constm1_rtx)
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293 return "lock{%;| }dec{<modesuffix>}\t%0";
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294 }
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295
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296 return "lock{%;| }add{<modesuffix>}\t{%1, %0|%0, %1}";
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297 })
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298
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299 (define_insn "sync_sub<mode>"
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300 [(set (match_operand:IMODE 0 "memory_operand" "+m")
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301 (unspec_volatile:IMODE
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302 [(minus:IMODE (match_dup 0)
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303 (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
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304 UNSPECV_LOCK))
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305 (clobber (reg:CC FLAGS_REG))]
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306 ""
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307 {
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308 if (TARGET_USE_INCDEC)
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309 {
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310 if (operands[1] == const1_rtx)
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311 return "lock{%;| }dec{<modesuffix>}\t%0";
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312 if (operands[1] == constm1_rtx)
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313 return "lock{%;| }inc{<modesuffix>}\t%0";
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314 }
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315
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316 return "lock{%;| }sub{<modesuffix>}\t{%1, %0|%0, %1}";
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317 })
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318
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319 (define_insn "sync_ior<mode>"
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320 [(set (match_operand:IMODE 0 "memory_operand" "+m")
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321 (unspec_volatile:IMODE
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322 [(ior:IMODE (match_dup 0)
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323 (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
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324 UNSPECV_LOCK))
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325 (clobber (reg:CC FLAGS_REG))]
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326 ""
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327 "lock{%;| }or{<modesuffix>}\t{%1, %0|%0, %1}")
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328
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329 (define_insn "sync_and<mode>"
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330 [(set (match_operand:IMODE 0 "memory_operand" "+m")
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331 (unspec_volatile:IMODE
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332 [(and:IMODE (match_dup 0)
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333 (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
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334 UNSPECV_LOCK))
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335 (clobber (reg:CC FLAGS_REG))]
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336 ""
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337 "lock{%;| }and{<modesuffix>}\t{%1, %0|%0, %1}")
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338
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339 (define_insn "sync_xor<mode>"
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340 [(set (match_operand:IMODE 0 "memory_operand" "+m")
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341 (unspec_volatile:IMODE
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342 [(xor:IMODE (match_dup 0)
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343 (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
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344 UNSPECV_LOCK))
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345 (clobber (reg:CC FLAGS_REG))]
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346 ""
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347 "lock{%;| }xor{<modesuffix>}\t{%1, %0|%0, %1}")
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