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0
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1
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2 ;; For the internal conditional math routines:
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3
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4 ;; operand 0 is always the result
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5 ;; operand 1 is always the predicate
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6 ;; operand 2, 3, and sometimes 4 are the input values.
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7 ;; operand 4 or 5 is the floating point status register to use.
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8 ;; operand 5 or 6 is the rounding to do. (0 = single, 1 = double, 2 = none)
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9 ;;
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10 ;; addrf3_cond - F0 = F2 + F3
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11 ;; subrf3_cond - F0 = F2 - F3
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12 ;; mulrf3_cond - F0 = F2 * F3
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13 ;; nmulrf3_cond - F0 = - (F2 * F3)
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14 ;; m1addrf4_cond - F0 = (F2 * F3) + F4
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15 ;; m1subrf4_cond - F0 = (F2 * F3) - F4
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16 ;; m2addrf4_cond - F0 = F2 + (F3 * F4)
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17 ;; m2subrf4_cond - F0 = F2 - (F3 * F4)
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18
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19 ;; Basic plus/minus/mult operations
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20
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21 (define_insn "addrf3_cond"
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22 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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23 (if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
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24 (const_int 0))
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25 (plus:RF
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26 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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27 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
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28 (match_operand:RF 4 "fr_reg_or_0_operand" "0,H")))
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29 (use (match_operand:SI 5 "const_int_operand" ""))
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30 (use (match_operand:SI 6 "const_int_operand" ""))]
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31 ""
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32 "(%1) fadd%R6.s%5 %0 = %F2, %F3"
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33 [(set_attr "itanium_class" "fmac")
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34 (set_attr "predicable" "no")])
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35
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36 (define_insn "subrf3_cond"
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37 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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38 (if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
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39 (const_int 0))
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40 (minus:RF
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41 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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42 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
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43 (match_operand:RF 4 "fr_reg_or_0_operand" "0,H")))
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44 (use (match_operand:SI 5 "const_int_operand" ""))
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45 (use (match_operand:SI 6 "const_int_operand" ""))]
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46 ""
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47 "(%1) fsub%R6.s%5 %0 = %F2, %F3"
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48 [(set_attr "itanium_class" "fmac")
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49 (set_attr "predicable" "no")])
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50
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51 (define_insn "mulrf3_cond"
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52 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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53 (if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
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54 (const_int 0))
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55 (mult:RF
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56 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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57 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
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58 (match_operand:RF 4 "fr_reg_or_0_operand" "0,H")))
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59 (use (match_operand:SI 5 "const_int_operand" ""))
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60 (use (match_operand:SI 6 "const_int_operand" ""))]
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61 ""
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62 "(%1) fmpy%R6.s%5 %0 = %F2, %F3"
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63 [(set_attr "itanium_class" "fmac")
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64 (set_attr "predicable" "no")])
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65
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66 ;; neg-mult operation
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67
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68 (define_insn "nmulrf3_cond"
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69 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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70 (if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
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71 (const_int 0))
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72 (neg:RF (mult:RF
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73 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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74 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG")))
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75 (match_operand:RF 4 "fr_reg_or_0_operand" "0,H")))
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76 (use (match_operand:SI 5 "const_int_operand" ""))
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77 (use (match_operand:SI 6 "const_int_operand" ""))]
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78 ""
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79 "(%1) fnmpy%R6.s%5 %0 = %F2, %F3"
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80 [(set_attr "itanium_class" "fmac")
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81 (set_attr "predicable" "no")])
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82
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83 ;; add-mult/sub-mult operations (mult as op1)
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84
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85 (define_insn "m1addrf4_cond"
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86 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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87 (if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
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88 (const_int 0))
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89 (plus:RF
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90 (mult:RF
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91 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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92 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
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93 (match_operand:RF 4 "fr_reg_or_fp01_operand" "fG,fG"))
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94 (match_operand:RF 5 "fr_reg_or_0_operand" "0,H")))
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95 (use (match_operand:SI 6 "const_int_operand" ""))
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96 (use (match_operand:SI 7 "const_int_operand" ""))]
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97 ""
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98 "(%1) fma%R7.s%6 %0 = %F2, %F3, %F4"
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99 [(set_attr "itanium_class" "fmac")
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100 (set_attr "predicable" "no")])
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101
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102 (define_insn "m1subrf4_cond"
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103 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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104 (if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
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105 (const_int 0))
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106 (minus:RF
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107 (mult:RF
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108 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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109 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
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110 (match_operand:RF 4 "fr_reg_or_fp01_operand" "fG,fG"))
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111 (match_operand:RF 5 "fr_reg_or_0_operand" "0,H")))
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112 (use (match_operand:SI 6 "const_int_operand" ""))
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113 (use (match_operand:SI 7 "const_int_operand" ""))]
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114 ""
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115 "(%1) fms%R7.s%6 %0 = %F2, %F3, %F4"
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116 [(set_attr "itanium_class" "fmac")
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117 (set_attr "predicable" "no")])
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118
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119 ;; add-mult/sub-mult operations (mult as op2)
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120
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121 (define_insn "m2addrf4_cond"
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122 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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123 (if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
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124 (const_int 0))
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125 (plus:RF
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126 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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127 (mult:RF
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128 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG")
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129 (match_operand:RF 4 "fr_reg_or_fp01_operand" "fG,fG")))
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130 (match_operand:RF 5 "fr_reg_or_0_operand" "0,H")))
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131 (use (match_operand:SI 6 "const_int_operand" ""))
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132 (use (match_operand:SI 7 "const_int_operand" ""))]
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133 ""
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134 "(%1) fma%R7.s%6 %0 = %F3, %F4, %F2"
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135 [(set_attr "itanium_class" "fmac")
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136 (set_attr "predicable" "no")])
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137
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138 (define_insn "m2subrf4_cond"
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139 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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140 (if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
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141 (const_int 0))
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142 (minus:RF
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143 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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144 (mult:RF
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145 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG")
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146 (match_operand:RF 4 "fr_reg_or_fp01_operand" "fG,fG")))
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147 (match_operand:RF 5 "fr_reg_or_0_operand" "0,H")))
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148 (use (match_operand:SI 6 "const_int_operand" ""))
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149 (use (match_operand:SI 7 "const_int_operand" ""))]
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150 ""
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151 "(%1) fnma%R7.s%6 %0 = %F3, %F4, %F2"
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152 [(set_attr "itanium_class" "fmac")
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153 (set_attr "predicable" "no")])
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154
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155 ;; Conversions to/from RF and SF/DF/XF
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156 ;; These conversions should not generate any code but make it possible
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157 ;; for all the instructions used to implement floating point division
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158 ;; to be written for RFmode only and to not have to handle multiple
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159 ;; modes or to have to handle a register in more than one mode.
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160
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161 (define_mode_iterator SDX_F [SF DF XF])
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162
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163 (define_insn "extend<mode>rf2"
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164 [(set (match_operand:RF 0 "fr_register_operand" "=f")
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165 (float_extend:RF (match_operand:SDX_F 1 "fr_register_operand" "f")))]
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166 ""
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167 "#"
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168 [(set_attr "itanium_class" "fmisc")
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169 (set_attr "predicable" "yes")])
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170
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171 (define_split
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172 [(set (match_operand:RF 0 "fr_register_operand" "")
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173 (float_extend:RF (match_operand:SDX_F 1 "fr_register_operand" "")))]
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174 "reload_completed"
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175 [(set (match_dup 0) (match_dup 2))]
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176 {
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177 operands[2] = gen_rtx_REG (RFmode, REGNO (operands[1]));
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178 })
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179
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180
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181 (define_insn "truncrf<mode>2"
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182 [(set (match_operand:SDX_F 0 "fr_register_operand" "=f")
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183 (float_truncate:SDX_F (match_operand:RF 1 "fr_register_operand" "f")))]
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184 ""
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185 "#"
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186 [(set_attr "itanium_class" "fmisc")
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187 (set_attr "predicable" "yes")])
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188
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189 (define_split
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190 [(set (match_operand:SDX_F 0 "fr_register_operand" "")
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191 (float_truncate:SDX_F (match_operand:RF 1 "fr_register_operand" "")))]
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192 "reload_completed"
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193 [(set (match_dup 0) (match_dup 2))]
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194 {
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195 operands[2] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
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196 })
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197
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198 ;; Reciprocal approximation
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199
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200 (define_insn "recip_approx_rf"
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201 [(set (match_operand:RF 0 "fr_register_operand" "=f")
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202 (unspec:RF [(match_operand:RF 1 "fr_register_operand" "f")
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203 (match_operand:RF 2 "fr_register_operand" "f")]
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204 UNSPEC_FR_RECIP_APPROX_RES))
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205 (set (match_operand:BI 3 "register_operand" "=c")
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206 (unspec:BI [(match_dup 1) (match_dup 2)] UNSPEC_FR_RECIP_APPROX))
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207 (use (match_operand:SI 4 "const_int_operand" ""))]
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208 ""
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209 "frcpa.s%4 %0, %3 = %1, %2"
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210 [(set_attr "itanium_class" "fmisc")
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211 (set_attr "predicable" "no")])
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212
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213 ;; Single precision floating point division (maximum throughput algorithm).
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214
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215 (define_expand "divsf3_internal_thr"
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216 [(set (match_operand:SF 0 "fr_register_operand" "")
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217 (div:SF (match_operand:SF 1 "fr_register_operand" "")
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218 (match_operand:SF 2 "fr_register_operand" "")))]
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219 "TARGET_INLINE_FLOAT_DIV"
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220 {
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221 rtx y = gen_reg_rtx (RFmode);
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222 rtx a = gen_reg_rtx (RFmode);
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223 rtx b = gen_reg_rtx (RFmode);
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224 rtx e = gen_reg_rtx (RFmode);
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225 rtx y1 = gen_reg_rtx (RFmode);
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226 rtx y2 = gen_reg_rtx (RFmode);
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227 rtx q = gen_reg_rtx (RFmode);
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228 rtx r = gen_reg_rtx (RFmode);
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229 rtx q_res = gen_reg_rtx (RFmode);
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230 rtx cond = gen_reg_rtx (BImode);
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231 rtx zero = CONST0_RTX (RFmode);
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232 rtx one = CONST1_RTX (RFmode);
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233 rtx status0 = CONST0_RTX (SImode);
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234 rtx status1 = CONST1_RTX (SImode);
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235 rtx trunc_sgl = CONST0_RTX (SImode);
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236 rtx trunc_off = CONST2_RTX (SImode);
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237
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238 /* Empty conversions to put inputs into RFmode. */
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239 emit_insn (gen_extendsfrf2 (a, operands[1]));
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240 emit_insn (gen_extendsfrf2 (b, operands[2]));
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241 /* y = 1 / b */
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242 emit_insn (gen_recip_approx_rf (y, a, b, cond, status0));
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243 /* e = 1 - (b * y) */
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244 emit_insn (gen_m2subrf4_cond (e, cond, one, b, y, zero, status1, trunc_off));
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245 /* y1 = y + (y * e) */
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246 emit_insn (gen_m2addrf4_cond (y1, cond, y, y, e, zero, status1, trunc_off));
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247 /* y2 = y + (y1 * e) */
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248 emit_insn (gen_m2addrf4_cond (y2, cond, y, y1, e, zero, status1, trunc_off));
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249 /* q = single(a * y2) */
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250 emit_insn (gen_mulrf3_cond (q, cond, a, y2, zero, status1, trunc_sgl));
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251 /* r = a - (q * b) */
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252 emit_insn (gen_m2subrf4_cond (r, cond, a, q, b, zero, status1, trunc_off));
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253 /* Q = single (q + (r * y2)) */
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254 emit_insn (gen_m2addrf4_cond (q_res, cond, q, r, y2, y, status0, trunc_sgl));
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255 /* Conversion back into SFmode. */
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256 emit_insn (gen_truncrfsf2 (operands[0], q_res));
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257 DONE;
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258 })
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259
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260
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261 ;; Double precision floating point division (maximum throughput algorithm).
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262
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263 (define_expand "divdf3_internal_thr"
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264 [(set (match_operand:DF 0 "fr_register_operand" "")
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265 (div:DF (match_operand:DF 1 "fr_register_operand" "")
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266 (match_operand:DF 2 "fr_register_operand" "")))]
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267 "TARGET_INLINE_FLOAT_DIV"
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268 {
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269 rtx q_res = gen_reg_rtx (RFmode);
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270 rtx a = gen_reg_rtx (RFmode);
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271 rtx b = gen_reg_rtx (RFmode);
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272 rtx y = gen_reg_rtx (RFmode);
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273 rtx e = gen_reg_rtx (RFmode);
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274 rtx y1 = gen_reg_rtx (RFmode);
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275 rtx e1 = gen_reg_rtx (RFmode);
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276 rtx y2 = gen_reg_rtx (RFmode);
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277 rtx e2 = gen_reg_rtx (RFmode);
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278 rtx y3 = gen_reg_rtx (RFmode);
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279 rtx q = gen_reg_rtx (RFmode);
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280 rtx r = gen_reg_rtx (RFmode);
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281 rtx cond = gen_reg_rtx (BImode);
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282 rtx zero = CONST0_RTX (RFmode);
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283 rtx one = CONST1_RTX (RFmode);
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284 rtx status0 = CONST0_RTX (SImode);
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285 rtx status1 = CONST1_RTX (SImode);
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286 rtx trunc_dbl = CONST1_RTX (SImode);
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287 rtx trunc_off = CONST2_RTX (SImode);
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288 /* Empty conversions to put inputs into RFmode */
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289 emit_insn (gen_extenddfrf2 (a, operands[1]));
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290 emit_insn (gen_extenddfrf2 (b, operands[2]));
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291 /* y = 1 / b */
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292 emit_insn (gen_recip_approx_rf (y, a, b, cond, status0));
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293 /* e = 1 - (b * y) */
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294 emit_insn (gen_m2subrf4_cond (e, cond, one, b, y, zero, status1, trunc_off));
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295 /* y1 = y + (y * e) */
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296 emit_insn (gen_m2addrf4_cond (y1, cond, y, y, e, zero, status1, trunc_off));
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297 /* e1 = e * e */
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298 emit_insn (gen_mulrf3_cond (e1, cond, e, e, zero, status1, trunc_off));
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299 /* y2 = y1 + (y1 * e1) */
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300 emit_insn (gen_m2addrf4_cond (y2, cond, y1, y1, e1, zero, status1, trunc_off));
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301 /* e2 = e1 * e1 */
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302 emit_insn (gen_mulrf3_cond (e2, cond, e1, e1, zero, status1, trunc_off));
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303 /* y3 = y2 + (y2 * e2) */
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304 emit_insn (gen_m2addrf4_cond (y3, cond, y2, y2, e2, zero, status1, trunc_off));
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305 /* q = double (a * y3) */
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306 emit_insn (gen_mulrf3_cond (q, cond, a, y3, zero, status1, trunc_dbl));
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307 /* r = a - (b * q) */
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308 emit_insn (gen_m2subrf4_cond (r, cond, a, b, q, zero, status1, trunc_off));
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309 /* Q = double (q + (r * y3)) */
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310 emit_insn (gen_m2addrf4_cond (q_res, cond, q, r, y3, y, status0, trunc_dbl));
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311 /* Conversion back into DFmode */
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312 emit_insn (gen_truncrfdf2 (operands[0], q_res));
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313 DONE;
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314 })
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