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1 ;; Machine Descriptions for R8C/M16C/M32C
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2 ;; Copyright (C) 2005, 2007, 2008
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3 ;; Free Software Foundation, Inc.
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4 ;; Contributed by Red Hat.
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5 ;;
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6 ;; This file is part of GCC.
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7 ;;
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8 ;; GCC is free software; you can redistribute it and/or modify it
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9 ;; under the terms of the GNU General Public License as published
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10 ;; by the Free Software Foundation; either version 3, or (at your
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11 ;; option) any later version.
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12 ;;
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13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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16 ;; License for more details.
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17 ;;
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 ;; Bit-wise operations (and, ior, xor, shift)
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23
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24 ; On the R8C and M16C, "address" for bit instructions is usually (but
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25 ; not always!) the *bit* address, not the *byte* address. This
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26 ; confuses gcc, so we avoid cases where gcc would produce the wrong
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27 ; code. We're left with absolute addresses and registers, and the odd
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28 ; case of shifting a bit by a variable.
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29
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30 ; On the M32C, "address" for bit instructions is a regular address,
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31 ; and the bit number is stored in a separate field. Thus, we can let
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32 ; gcc do more interesting things. However, the M32C cannot set all
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33 ; the bits in a 16-bit register, which the R8C/M16C can do.
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34
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35 ; However, it all means that we end up with two sets of patterns, one
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36 ; for each chip.
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37
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38 ;;----------------------------------------------------------------------
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39
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40 ;; First off, all the ways we can set one bit, other than plain IOR.
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41
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42 (define_insn "bset_qi"
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43 [(set (match_operand:QI 0 "memsym_operand" "+Si")
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44 (ior:QI (subreg:QI (ashift:HI (const_int 1)
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45 (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)) 0)
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46 (match_operand:QI 2 "memsym_operand" "0")))]
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47 "TARGET_A16"
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48 "bset\t%0[%1]"
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49 [(set_attr "flags" "n")]
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50 )
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51
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52 (define_insn "bset_hi"
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53 [(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
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54 (const_int 1)
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55 (zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
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56 (const_int 1))]
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57 "TARGET_A16"
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58 "bset\t%0[%1]"
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59 [(set_attr "flags" "n")]
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60 )
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61
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62 ;;----------------------------------------------------------------------
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63
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64 ;; Now all the ways we can clear one bit, other than plain AND.
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65
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66 ; This is odd because the shift patterns use QI counts, but we can't
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67 ; easily put QI in $aN without causing problems elsewhere.
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68 (define_insn "bclr_qi"
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69 [(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
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70 (const_int 1)
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71 (zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
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72 (const_int 0))]
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73 "TARGET_A16"
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74 "bclr\t%0[%1]"
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75 [(set_attr "flags" "n")]
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76 )
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77
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78
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79 ;;----------------------------------------------------------------------
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80
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81 ;; Now the generic patterns.
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82
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83 (define_insn "andqi3_16"
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84 [(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
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85 (and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
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86 (match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
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87 "TARGET_A16"
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88 "@
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89 bclr\t%B2,%0
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90 bclr\t%B2,%h0
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91 and.b\t%x2,%0
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92 and.b\t%x2,%0
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93 and.b\t%x2,%0
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94 and.b\t%x2,%0"
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95 [(set_attr "flags" "n,n,sz,sz,sz,sz")]
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96 )
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97
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98 (define_insn "andhi3_16"
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99 [(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,??Rmm,RhiSd,??Rmm")
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100 (and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
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101 (match_operand:HI 2 "mrai_operand" "ImB,Imw,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
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102 "TARGET_A16"
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103 "@
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104
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105 bclr\t%B2,%0
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106 bclr\t%B2-8,1+%0
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107 bclr\t%B2,%0
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108 and.w\t%X2,%0
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109 and.w\t%X2,%0
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110 and.w\t%X2,%0
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111 and.w\t%X2,%0"
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112 [(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
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113 )
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114
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115 (define_insn "andsi3"
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116 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
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117 (and:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
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118 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
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119 ""
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120 "*
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121 switch (which_alternative)
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122 {
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123 case 0:
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124 output_asm_insn (\"and.w %X2,%h0\",operands);
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125 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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126 return \"and.w %X2,%H0\";
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127 case 1:
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128 return \"and.w %h2,%h0\;and.w %H2,%H0\";
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129 case 2:
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130 output_asm_insn (\"and.w %X2,%h0\",operands);
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131 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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132 return \"and.w %X2,%H0\";
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133 case 3:
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134 return \"and.w %h2,%h0\;and.w %H2,%H0\";
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135 case 4:
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136 return \"and.w %h2,%h0\;and.w %H2,%H0\";
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137 case 5:
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138 return \"and.w %h2,%h0\;and.w %H2,%H0\";
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139 }"
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140 [(set_attr "flags" "x,x,x,x,x,x")]
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141 )
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142
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143
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144 (define_insn "iorqi3_16"
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145 [(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RqiSd,??Rmm,RqiSd,??Rmm")
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146 (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
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147 (match_operand:QI 2 "mrai_operand" "Ilb,Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
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148 "TARGET_A16"
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149 "@
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150 bset\t%B2,%0
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151 bset\t%B2,%h0
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152 or.b\t%x2,%0
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153 or.b\t%x2,%0
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154 or.b\t%x2,%0
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155 or.b\t%x2,%0"
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156 [(set_attr "flags" "n,n,sz,sz,sz,sz")]
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157 )
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158
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159 (define_insn "iorhi3_16"
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160 [(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,RhiSd,??Rmm,??Rmm")
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161 (ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
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162 (match_operand:HI 2 "mrai_operand" "Ilb,Ilw,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
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163 "TARGET_A16"
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164 "@
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165 bset %B2,%0
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166 bset\t%B2-8,1+%0
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167 bset\t%B2,%0
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168 or.w\t%X2,%0
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169 or.w\t%X2,%0
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170 or.w\t%X2,%0
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171 or.w\t%X2,%0"
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172 [(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
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173 )
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174
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175 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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176
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177 (define_insn "andqi3_24"
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178 [(set (match_operand:QI 0 "mra_operand" "=Sd,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
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179 (and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
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180 (match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
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181 "TARGET_A24"
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182 "@
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183 bclr\t%B2,%0
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184 bclr\t%B2,%0
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185 and.b\t%x2,%0
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186 and.b\t%x2,%0
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187 and.b\t%x2,%0
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188 and.b\t%x2,%0"
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189 [(set_attr "flags" "n,n,sz,sz,sz,sz")]
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190 )
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191
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192 (define_insn "andhi3_24"
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193 [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,?Rhl,?Rhl,RhiSd,??Rmm,RhiSd,??Rmm")
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194 (and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
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195 (match_operand:HI 2 "mrai_operand" "ImB,Imw,ImB,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
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196 "TARGET_A24"
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197 "@
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198 bclr\t%B2,%0
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199 bclr\t%B2-8,1+%0
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200 bclr\t%B2,%h0
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201 bclr\t%B2-8,%H0
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202 and.w\t%X2,%0
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203 and.w\t%X2,%0
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204 and.w\t%X2,%0
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205 and.w\t%X2,%0"
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206 [(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
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207 )
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208
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209
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210
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211 (define_insn "iorqi3_24"
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212 [(set (match_operand:QI 0 "mra_operand" "=RqiSd,RqiSd,??Rmm,RqiSd,??Rmm")
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213 (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0")
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214 (match_operand:QI 2 "mrai_operand" "Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
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215 "TARGET_A24"
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216 "@
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217 bset\t%B2,%0
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218 or.b\t%x2,%0
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219 or.b\t%x2,%0
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220 or.b\t%x2,%0
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221 or.b\t%x2,%0"
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222 [(set_attr "flags" "n,sz,sz,sz,sz")]
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223 )
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224
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225 (define_insn "iorhi3_24"
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226 [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,?Rhl,?Rhl,RhiSd,RhiSd,??Rmm,??Rmm")
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227 (ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
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228 (match_operand:HI 2 "mrai_operand" "Ilb,Ilw,Ilb,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
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229 "TARGET_A24"
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230 "@
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231 bset\t%B2,%0
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232 bset\t%B2-8,1+%0
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233 bset\t%B2,%h0
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234 bset\t%B2-8,%H0
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235 or.w\t%X2,%0
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236 or.w\t%X2,%0
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237 or.w\t%X2,%0
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238 or.w\t%X2,%0"
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239 [(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
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240 )
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241
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242
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243 ; ----------------------------------------------------------------------
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244
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245 (define_expand "andqi3"
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246 [(set (match_operand:QI 0 "mra_operand" "")
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247 (and:QI (match_operand:QI 1 "mra_operand" "")
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248 (match_operand:QI 2 "mrai_operand" "")))]
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249 ""
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250 "if (TARGET_A16)
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251 emit_insn (gen_andqi3_16 (operands[0], operands[1], operands[2]));
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252 else
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253 emit_insn (gen_andqi3_24 (operands[0], operands[1], operands[2]));
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254 DONE;"
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255 )
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256
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257 (define_expand "andhi3"
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258 [(set (match_operand:HI 0 "mra_operand" "")
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259 (and:HI (match_operand:HI 1 "mra_operand" "")
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260 (match_operand:HI 2 "mrai_operand" "")))]
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261 ""
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262 "if (TARGET_A16)
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263 emit_insn (gen_andhi3_16 (operands[0], operands[1], operands[2]));
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264 else
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265 emit_insn (gen_andhi3_24 (operands[0], operands[1], operands[2]));
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266 DONE;"
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267 )
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268
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269 (define_expand "iorqi3"
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270 [(set (match_operand:QI 0 "mra_operand" "")
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271 (ior:QI (match_operand:QI 1 "mra_operand" "")
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272 (match_operand:QI 2 "mrai_operand" "")))]
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273 ""
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274 "if (TARGET_A16)
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275 emit_insn (gen_iorqi3_16 (operands[0], operands[1], operands[2]));
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276 else
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277 emit_insn (gen_iorqi3_24 (operands[0], operands[1], operands[2]));
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278 DONE;"
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279 )
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280
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281 (define_expand "iorhi3"
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282 [(set (match_operand:HI 0 "mra_operand" "")
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283 (ior:HI (match_operand:HI 1 "mra_operand" "")
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284 (match_operand:HI 2 "mrai_operand" "")))]
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285 ""
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286 "if (TARGET_A16)
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287 emit_insn (gen_iorhi3_16 (operands[0], operands[1], operands[2]));
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288 else
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289 emit_insn (gen_iorhi3_24 (operands[0], operands[1], operands[2]));
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290 DONE;"
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291 )
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292
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293 (define_insn "iorsi3"
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294 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
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295 (ior:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
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296 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
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297 ""
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298 "*
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299 switch (which_alternative)
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300 {
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301 case 0:
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302 output_asm_insn (\"or.w %X2,%h0\",operands);
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303 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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304 return \"or.w %X2,%H0\";
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305 case 1:
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306 return \"or.w %h2,%h0\;or.w %H2,%H0\";
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307 case 2:
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308 output_asm_insn (\"or.w %X2,%h0\",operands);
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309 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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310 return \"or.w %X2,%H0\";
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311 case 3:
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312 return \"or.w %h2,%h0\;or.w %H2,%H0\";
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313 case 4:
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314 return \"or.w %h2,%h0\;or.w %H2,%H0\";
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315 case 5:
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316 return \"or.w %h2,%h0\;or.w %H2,%H0\";
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317 }"
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318 [(set_attr "flags" "x,x,x,x,x,x")]
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319 )
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320
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321 (define_insn "xorqi3"
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322 [(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm")
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323 (xor:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
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324 (match_operand:QI 2 "mrai_operand" "iRhlSd,?Rmm,iRhlSd,?Rmm")))]
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325 ""
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326 "xor.b\t%x2,%0"
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327 [(set_attr "flags" "sz,sz,sz,sz")]
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328 )
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329
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330 (define_insn "xorhi3"
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331 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
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332 (xor:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
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333 (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
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334 ""
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335 "xor.w\t%X2,%0"
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336 [(set_attr "flags" "sz,sz,sz,sz")]
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337 )
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338
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339 (define_insn "xorsi3"
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340 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
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341 (xor:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
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342 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
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343 ""
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344 "*
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345 switch (which_alternative)
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346 {
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347 case 0:
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348 output_asm_insn (\"xor.w %X2,%h0\",operands);
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349 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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350 return \"xor.w %X2,%H0\";
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351 case 1:
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352 return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
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353 case 2:
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354 output_asm_insn (\"xor.w %X2,%h0\",operands);
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355 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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356 return \"xor.w %X2,%H0\";
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357 case 3:
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358 return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
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359 case 4:
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360 return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
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361 case 5:
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362 return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
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363 }"
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364 [(set_attr "flags" "x,x,x,x,x,x")]
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365 )
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366
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367 (define_insn "one_cmplqi2"
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368 [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
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369 (not:QI (match_operand:QI 1 "mra_operand" "0,0")))]
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370 ""
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371 "not.b\t%0"
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372 [(set_attr "flags" "sz,sz")]
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373 )
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374
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375 (define_insn "one_cmplhi2"
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376 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
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377 (not:HI (match_operand:HI 1 "mra_operand" "0,0")))]
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378 ""
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379 "not.w\t%0"
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380 [(set_attr "flags" "sz,sz")]
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381 )
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382
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383 ; Optimizations using bit opcodes
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384
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385 ; We need this because combine only looks at three insns at a time,
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386 ; and the bclr_qi pattern uses four - mov, shift, not, and. GCC
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387 ; should never expand this pattern, because it only shifts a constant
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388 ; by a constant, so gcc should do that itself.
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389 (define_insn "shift1_qi"
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390 [(set (match_operand:QI 0 "mra_operand" "=Rqi")
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391 (ashift:QI (const_int 1)
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392 (match_operand 1 "const_int_operand" "In4")))]
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393 ""
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394 "mov.b\t#1,%0\n\tshl.b\t%1,%0"
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395 )
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396 (define_insn "shift1_hi"
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397 [(set (match_operand:HI 0 "mra_operand" "=Rhi")
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398 (ashift:HI (const_int 1)
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399 (match_operand 1 "const_int_operand" "In4")))]
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400 ""
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401 "mov.w\t#1,%0\n\tshl.w\t%1,%0"
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402 )
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403
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404 ; Generic insert-bit expander, needed so that we can use the bit
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405 ; opcodes for volatile bitfields.
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406
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407 (define_expand "insv"
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408 [(set (zero_extract:HI (match_operand:HI 0 "mra_operand" "")
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409 (match_operand 1 "const_int_operand" "")
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410 (match_operand 2 "const_int_operand" ""))
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411 (match_operand:HI 3 "const_int_operand" ""))]
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412 ""
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413 "if (m32c_expand_insv (operands))
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414 FAIL;
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415 DONE;"
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416 )
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