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1 ;; Machine Descriptions for R8C/M16C/M32C
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2 ;; Copyright (C) 2006, 2007
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3 ;; Free Software Foundation, Inc.
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4 ;; Contributed by Red Hat.
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5 ;;
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6 ;; This file is part of GCC.
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7 ;;
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8 ;; GCC is free software; you can redistribute it and/or modify it
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9 ;; under the terms of the GNU General Public License as published
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10 ;; by the Free Software Foundation; either version 3, or (at your
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11 ;; option) any later version.
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12 ;;
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13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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16 ;; License for more details.
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17 ;;
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 ;; various block move instructions
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23
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24 ;; R8C:
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25 ;; SMOVB - while (r3--) { *a1-- = *r1ha0--; } - memcpy
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26 ;; SMOVF - while (r3--) { *a1++ = *r1ha0++; } - memcpy
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27 ;; SSTR - while (r3--) { *a1++ = [r0l,r0]; } - memset
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28
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29 ;; M32CM:
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30 ;; SCMPU - while (*a0 && *a0 != *a1) { a0++; a1++; } - strcmp
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31 ;; SIN - while (r3--) { *a1++ = *a0; }
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32 ;; SMOVB - while (r3--) { *a1-- = *a0--; } - memcpy
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33 ;; SMOVF - while (r3--) { *a1++ = *a0++; } - memcpy
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34 ;; SMOVU - while (*a1++ = *a0++) ; - strcpy
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35 ;; SOUT - while (r3--) { *a1 = *a0++; }
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36 ;; SSTR - while (r3--) { *a1++ = [r0l,r0]; } - memset
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37
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38
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39
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40 ;; 0 = destination (mem:BLK ...)
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41 ;; 1 = source (mem:BLK ...)
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42 ;; 2 = count
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43 ;; 3 = alignment
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44 (define_expand "movmemhi"
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45 [(match_operand 0 "ap_operand" "")
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46 (match_operand 1 "ap_operand" "")
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47 (match_operand 2 "m32c_r3_operand" "")
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48 (match_operand 3 "" "")
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49 ]
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50 ""
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51 "if (m32c_expand_movmemhi(operands)) DONE; FAIL;"
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52 )
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53
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54 ;; We can't use mode iterators for these because M16C uses r1h to extend
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55 ;; the source address, for copying data from ROM to RAM. We don't yet
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56 ;; support that, but we need to zero our r1h, so the patterns differ.
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57
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58 ;; 0 = dest (out)
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59 ;; 1 = src (out)
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60 ;; 2 = count (out)
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61 ;; 3 = dest (in)
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62 ;; 4 = src (in)
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63 ;; 5 = count (in)
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64 (define_insn "movmemhi_bhi_op"
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65 [(set (mem:QI (match_operand:HI 3 "ap_operand" "0"))
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66 (mem:QI (match_operand:HI 4 "ap_operand" "1")))
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67 (set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
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68 (const_int 0))
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69 (set (match_operand:HI 0 "ap_operand" "=Ra1")
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70 (plus:HI (match_dup 3)
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71 (zero_extend:HI (match_operand:HI 5 "m32c_r3_operand" "2"))))
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72 (set (match_operand:HI 1 "ap_operand" "=Ra0")
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73 (plus:HI (match_dup 4)
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74 (zero_extend:HI (match_dup 5))))
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75 (use (reg:HI R1_REGNO))]
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76 "TARGET_A16"
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77 "mov.b:q\t#0,r1h\n\tsmovf.b\t; %0[0..%2-1]=r1h%1[]"
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78 )
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79 (define_insn "movmemhi_bpsi_op"
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80 [(set (mem:QI (match_operand:PSI 3 "ap_operand" "0"))
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81 (mem:QI (match_operand:PSI 4 "ap_operand" "1")))
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82 (set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
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83 (const_int 0))
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84 (set (match_operand:PSI 0 "ap_operand" "=Ra1")
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85 (plus:PSI (match_dup 3)
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86 (zero_extend:PSI (match_operand:HI 5 "m32c_r3_operand" "2"))))
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87 (set (match_operand:PSI 1 "ap_operand" "=Ra0")
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88 (plus:PSI (match_dup 4)
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89 (zero_extend:PSI (match_dup 5))))]
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90 "TARGET_A24"
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91 "smovf.b\t; %0[0..%2-1]=%1[]"
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92 )
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93 (define_insn "movmemhi_whi_op"
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94 [(set (mem:HI (match_operand:HI 3 "ap_operand" "0"))
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95 (mem:HI (match_operand:HI 4 "ap_operand" "1")))
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96 (set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
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97 (const_int 0))
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98 (set (match_operand:HI 0 "ap_operand" "=Ra1")
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99 (plus:HI (match_dup 3)
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100 (zero_extend:HI (match_operand:HI 5 "m32c_r3_operand" "2"))))
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101 (set (match_operand:HI 1 "ap_operand" "=Ra0")
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102 (plus:HI (match_dup 4)
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103 (zero_extend:HI (match_dup 5))))
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104 (use (reg:HI R1_REGNO))]
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105 "TARGET_A16"
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106 "mov.b:q\t#0,r1h\n\tsmovf.w\t; %0[0..%2-1]=r1h%1[]"
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107 )
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108 (define_insn "movmemhi_wpsi_op"
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109 [(set (mem:HI (match_operand:PSI 3 "ap_operand" "0"))
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110 (mem:HI (match_operand:PSI 4 "ap_operand" "1")))
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111 (set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
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112 (const_int 0))
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113 (set (match_operand:PSI 0 "ap_operand" "=Ra1")
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114 (plus:PSI (match_dup 3)
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115 (zero_extend:PSI (match_operand:HI 5 "m32c_r3_operand" "2"))))
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116 (set (match_operand:PSI 1 "ap_operand" "=Ra0")
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117 (plus:PSI (match_dup 4)
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118 (zero_extend:PSI (match_dup 5))))]
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119 "TARGET_A24"
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120 "smovf.w\t; %0[0..%2-1]=%1[]"
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121 )
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122
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123
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124
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125 ;; 0 = destination (mem:BLK ...)
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126 ;; 1 = number of bytes
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127 ;; 2 = value to store
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128 ;; 3 = alignment
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129 (define_expand "setmemhi"
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130 [(match_operand 0 "ap_operand" "")
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131 (match_operand 1 "m32c_r3_operand" "")
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132 (match_operand 2 "m32c_r0_operand" "")
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133 (match_operand 3 "" "")
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134 ]
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135 "TARGET_A24"
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136 "if (m32c_expand_setmemhi(operands)) DONE; FAIL;"
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137 )
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138
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139 ;; 0 = address (out)
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140 ;; 1 = count (out)
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141 ;; 2 = value (in)
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142 ;; 3 = address (in)
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143 ;; 4 = count (in)
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144 (define_insn "setmemhi_b<mode>_op"
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145 [(set (mem:QI (match_operand:HPSI 3 "ap_operand" "0"))
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146 (match_operand:QI 2 "m32c_r0_operand" "R0w"))
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147 (set (match_operand:HI 1 "m32c_r3_operand" "=R3w")
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148 (const_int 0))
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149 (set (match_operand:HPSI 0 "ap_operand" "=Ra1")
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150 (plus:HPSI (match_dup 3)
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151 (zero_extend:HPSI (match_operand:HI 4 "m32c_r3_operand" "1"))))]
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152 "TARGET_A24"
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153 "sstr.b\t; %0[0..%1-1]=%2"
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154 )
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155
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156 (define_insn "setmemhi_w<mode>_op"
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157 [(set (mem:HI (match_operand:HPSI 3 "ap_operand" "0"))
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158 (match_operand:HI 2 "m32c_r0_operand" "R0w"))
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159 (set (match_operand:HI 1 "m32c_r3_operand" "=R3w")
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160 (const_int 0))
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161 (set (match_operand:HPSI 0 "ap_operand" "=Ra1")
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162 (plus:HPSI (match_dup 3)
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163 (zero_extend:HPSI (match_operand:HI 4 "m32c_r3_operand" "1"))))]
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164 "TARGET_A24"
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165 "sstr.w\t; %0[0..%1-1]=%2"
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166 )
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167
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168
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169 ;; SCMPU sets the flags according to the result of the string
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170 ;; comparison. GCC wants the result to be a signed value reflecting
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171 ;; the result, which it then compares to zero. Hopefully we can
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172 ;; optimize that later (see peephole in cond.md). Meanwhile, the
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173 ;; strcmp builtin is expanded to a SCMPU followed by a flags-to-int
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174 ;; pattern in cond.md.
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175
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176 ;; 0 = result:HI
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177 ;; 1 = destination (mem:BLK ...)
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178 ;; 2 = source (mem:BLK ...)
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179 ;; 3 = alignment
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180
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181 (define_expand "cmpstrsi"
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182 [(match_operand:HI 0 "" "")
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183 (match_operand 1 "ap_operand" "")
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184 (match_operand 2 "ap_operand" "")
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185 (match_operand 3 "" "")
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186 ]
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187 "TARGET_A24"
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188 "if (m32c_expand_cmpstr(operands)) DONE; FAIL;"
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189 )
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190
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191 ;; 0 = string1
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192 ;; 1 = string2
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193
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194 (define_insn "cmpstrhi_op"
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195 [(set (reg:CC FLG_REGNO)
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196 (compare:CC (mem:BLK (match_operand:PSI 0 "ap_operand" "Ra0"))
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197 (mem:BLK (match_operand:PSI 1 "ap_operand" "Ra1"))))
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198 (clobber (match_operand:PSI 2 "ap_operand" "=0"))
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199 (clobber (match_operand:PSI 3 "ap_operand" "=1"))]
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200 "TARGET_A24"
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201 "scmpu.b\t; flags := strcmp(*%0,*%1)"
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202 [(set_attr "flags" "oszc")]
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203 )
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204
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205
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206
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207 ;; Note that SMOVU leaves the address registers pointing *after*
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208 ;; the NUL at the end of the string. This is not what gcc expects; it
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209 ;; expects the address registers to point *at* the NUL. The expander
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210 ;; must emit a suitable add insn.
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211
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212 ;; 0 = target: set to &NUL in dest
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213 ;; 1 = destination (mem:BLK ...)
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214 ;; 2 = source (mem:BLK ...)
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215
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216 (define_expand "movstr"
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217 [(match_operand 0 "" "")
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218 (match_operand 1 "ap_operand" "")
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219 (match_operand 2 "ap_operand" "")
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220 ]
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221 "TARGET_A24"
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222 "if (m32c_expand_movstr(operands)) DONE; FAIL;"
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223 )
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224
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225 ;; 0 = dest (out)
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226 ;; 1 = src (out) (clobbered)
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227 ;; 2 = dest (in)
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228 ;; 3 = src (in)
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229 (define_insn "movstr_op"
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230 [(set (mem:BLK (match_operand:PSI 2 "ap_operand" "0"))
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231 (mem:BLK (match_operand:PSI 3 "ap_operand" "1")))
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232 (set (match_operand:PSI 0 "ap_operand" "=Ra1")
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233 (plus:PSI (match_dup 2)
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234 (unspec:PSI [(const_int 0)] UNS_SMOVU)))
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235 (set (match_operand:PSI 1 "ap_operand" "=Ra0")
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236 (plus:PSI (match_dup 3)
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237 (unspec:PSI [(const_int 0)] UNS_SMOVU)))]
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238 "TARGET_A24"
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239 "smovu.b\t; while (*%2++ := *%3++) != 0"
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240 [(set_attr "flags" "*")]
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241 )
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242
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