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1 ;; Machine Descriptions for R8C/M16C/M32C
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2 ;; Copyright (C) 2005, 2007, 2008
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3 ;; Free Software Foundation, Inc.
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4 ;; Contributed by Red Hat.
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5 ;;
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6 ;; This file is part of GCC.
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7 ;;
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8 ;; GCC is free software; you can redistribute it and/or modify it
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9 ;; under the terms of the GNU General Public License as published
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10 ;; by the Free Software Foundation; either version 3, or (at your
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11 ;; option) any later version.
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12 ;;
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13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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16 ;; License for more details.
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17 ;;
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 ; conditionals - cmp, jcc, setcc, etc.
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23
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24 ; Special note about conditional instructions: GCC always emits the
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25 ; compare right before the insn, which is good, because m32c's mov
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26 ; insns modify the flags. However, this means that any conditional
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27 ; insn that may require reloading must be kept with its compare until
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28 ; after reload finishes, else the reload insns might clobber the
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29 ; flags. Thus, these rules:
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30 ;
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31 ; * the cmp* expanders just save the operands in compare_op0 and
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32 ; compare_op1 via m32c_pend_compare.
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33 ; * conditional insns that won't need reload can call
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34 ; m32c_unpend_compare before their expansion.
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35 ; * other insns must expand to include the compare operands within,
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36 ; then split after reload to a separate compare and conditional.
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37
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38 ; Until support for relaxing is supported in gas, we must assume that
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39 ; short labels won't reach, so we must use long labels.
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40 ; Unfortunately, there aren't any conditional jumps with long labels,
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41 ; so instead we invert the conditional and jump around a regular jump.
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42
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43 ; Note that we can, at some point in the future, add code to omit the
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44 ; "cmp" portion of the insn if the preceding insn happened to set the
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45 ; right flags already. For example, a mov followed by a "cmp *,0" is
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46 ; redundant; the move already set the Z flag.
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47
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48 (define_insn_and_split "cbranch<mode>4"
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49 [(set (pc) (if_then_else
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50 (match_operator 0 "m32c_cmp_operator"
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51 [(match_operand:QHPSI 1 "mra_operand" "RraSd")
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52 (match_operand:QHPSI 2 "mrai_operand" "iRraSd")])
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53 (label_ref (match_operand 3 "" ""))
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54 (pc)))]
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55 ""
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56 "#"
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57 "reload_completed"
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58 [(set (reg:CC FLG_REGNO)
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59 (compare (match_dup 1)
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60 (match_dup 2)))
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61 (set (pc) (if_then_else (match_dup 4)
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62 (label_ref (match_dup 3))
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63 (pc)))]
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64 "operands[4] = m32c_cmp_flg_0 (operands[0]);"
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65 )
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66
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67 (define_insn "stzx_16"
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68 [(set (match_operand:QI 0 "mrai_operand" "=R0w,R0w,R0w")
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69 (if_then_else:QI (eq (reg:CC FLG_REGNO) (const_int 0))
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70 (match_operand:QI 1 "const_int_operand" "i,i,0")
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71 (match_operand:QI 2 "const_int_operand" "i,0,i")))]
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72 "TARGET_A16 && reload_completed"
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73 "@
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74 stzx\t%1,%2,%0
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75 stz\t%1,%0
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76 stnz\t%2,%0"
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77 [(set_attr "flags" "n,n,n")]
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78 )
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79
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80 (define_insn "stzx_24_<mode>"
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81 [(set (match_operand:QHI 0 "mrai_operand" "=RraSd,RraSd,RraSd")
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82 (if_then_else:QHI (eq (reg:CC FLG_REGNO) (const_int 0))
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83 (match_operand:QHI 1 "const_int_operand" "i,i,0")
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84 (match_operand:QHI 2 "const_int_operand" "i,0,i")))]
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85 "TARGET_A24 && reload_completed"
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86 "@
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87 stzx.<bwl>\t%1,%2,%0
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88 stz.<bwl>\t%1,%0
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89 stnz.<bwl>\t%2,%0"
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90 [(set_attr "flags" "n,n,n")])
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91
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92 (define_insn_and_split "stzx_reversed_<mode>"
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93 [(set (match_operand:QHI 0 "m32c_r0_operand" "=R0w")
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94 (if_then_else:QHI (ne (reg:CC FLG_REGNO) (const_int 0))
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95 (match_operand:QHI 1 "const_int_operand" "")
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96 (match_operand:QHI 2 "const_int_operand" "")))]
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97 "(TARGET_A24 || GET_MODE (operands[0]) == QImode) && reload_completed"
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98 "#"
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99 ""
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100 [(set (match_dup 0)
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101 (if_then_else:QHI (eq (reg:CC FLG_REGNO) (const_int 0))
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102 (match_dup 2)
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103 (match_dup 1)))]
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104 ""
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105 )
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106
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107
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108 (define_insn "cmp<mode>_op"
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109 [(set (reg:CC FLG_REGNO)
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110 (compare (match_operand:QHPSI 0 "mra_operand" "RraSd")
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111 (match_operand:QHPSI 1 "mrai_operand" "RraSdi")))]
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112 ""
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113 "* return m32c_output_compare(insn, operands); "
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114 [(set_attr "flags" "oszc")])
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115
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116 (define_expand "cmp<mode>"
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117 [(set (reg:CC FLG_REGNO)
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118 (compare (match_operand:QHPSI 0 "mra_operand" "RraSd")
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119 (match_operand:QHPSI 1 "mrai_operand" "RraSdi")))]
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120 ""
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121 "m32c_pend_compare (operands); DONE;")
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122
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123 (define_insn "b<code>_op"
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124 [(set (pc)
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125 (if_then_else (any_cond (reg:CC FLG_REGNO)
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126 (const_int 0))
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127 (label_ref (match_operand 0 ""))
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128 (pc)))]
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129 ""
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130 "j<code>\t%l0"
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131 [(set_attr "flags" "n")]
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132 )
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133
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134 (define_expand "b<code>"
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135 [(set (pc)
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136 (if_then_else (any_cond (reg:CC FLG_REGNO)
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137 (const_int 0))
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138 (label_ref (match_operand 0 ""))
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139 (pc)))]
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140 ""
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141 "m32c_unpend_compare ();"
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142 )
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143
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144 ;; m32c_conditional_register_usage changes the setcc_gen_code array to
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145 ;; point to the _24 variants if needed.
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146
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147 ;; We need to keep the compare and conditional sets together through
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148 ;; reload, because reload might need to add address reloads to the
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149 ;; set, which would clobber the flags. By keeping them together, the
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150 ;; reloads get put before the compare, thus preserving the flags.
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151
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152 ;; These are the post-split patterns for the conditional sets.
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153
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154 (define_insn "s<code>_op"
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155 [(set (match_operand:QI 0 "register_operand" "=Rqi")
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156 (any_cond:QI (reg:CC FLG_REGNO) (const_int 0)))]
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157 "TARGET_A16 && reload_completed"
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158 "* return m32c_scc_pattern(operands, <CODE>);")
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159
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160 (define_insn "s<code>_24_op"
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161 [(set (match_operand:HI 0 "mra_operand" "=RhiSd")
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162 (any_cond:HI (reg:CC FLG_REGNO) (const_int 0)))]
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163 "TARGET_A24 && reload_completed"
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164 "sc<code>\t%0"
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165 [(set_attr "flags" "n")]
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166 )
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167
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168 ;; These are the pre-split patterns for the conditional sets. Yes,
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169 ;; there are a lot of permutations.
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170
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171 (define_insn_and_split "s<code>_<mode>"
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172 [(set (match_operand:QI 0 "register_operand" "=Rqi")
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173 (any_cond:QI (match_operand:QHPSI 1 "mra_operand" "RraSd")
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174 (match_operand:QHPSI 2 "mrai_operand" "RraSdi")))]
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175 "TARGET_A16"
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176 "#"
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177 "reload_completed"
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178 [(set (reg:CC FLG_REGNO)
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179 (compare (match_dup 1)
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180 (match_dup 2)))
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181 (set (match_dup 0)
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182 (any_cond:QI (reg:CC FLG_REGNO) (const_int 0)))]
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183 ""
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184 [(set_attr "flags" "x")]
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185 )
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186
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187 (define_insn_and_split "s<code>_<mode>_24"
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188 [(set (match_operand:HI 0 "mra_nopp_operand" "=RhiSd")
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189 (any_cond:HI (match_operand:QHPSI 1 "mra_operand" "RraSd")
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190 (match_operand:QHPSI 2 "mrai_operand" "RraSdi")))]
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191 "TARGET_A24"
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192 "#"
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193 "reload_completed"
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194 [(set (reg:CC FLG_REGNO)
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195 (compare (match_dup 1)
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196 (match_dup 2)))
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197 (set (match_dup 0)
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198 (any_cond:HI (reg:CC FLG_REGNO) (const_int 0)))]
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199 ""
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200 [(set_attr "flags" "x")]
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201 )
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202
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203 (define_insn_and_split "movqicc_<code>_<mode>"
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204 [(set (match_operand:QI 0 "register_operand" "=R0w")
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205 (if_then_else:QI (eqne_cond:QI (match_operand:QHPSI 1 "mra_operand" "RraSd")
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206 (match_operand:QHPSI 2 "mrai_operand" "RraSdi"))
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207 (match_operand:QI 3 "const_int_operand" "")
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208 (match_operand:QI 4 "const_int_operand" "")))]
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209 ""
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210 "#"
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211 "reload_completed"
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212 [(set (reg:CC FLG_REGNO)
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213 (compare (match_dup 1)
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214 (match_dup 2)))
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215 (set (match_dup 0)
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216 (if_then_else:QI (eqne_cond:QI (reg:CC FLG_REGNO) (const_int 0))
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217 (match_dup 3)
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218 (match_dup 4)))]
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219 ""
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220 [(set_attr "flags" "x")]
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221 )
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222
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223 (define_insn_and_split "movhicc_<code>_<mode>"
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224 [(set (match_operand:HI 0 "register_operand" "=R0w")
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225 (if_then_else:HI (eqne_cond:HI (match_operand:QHPSI 1 "mra_operand" "RraSd")
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226 (match_operand:QHPSI 2 "mrai_operand" "RraSdi"))
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227 (match_operand:QI 3 "const_int_operand" "")
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228 (match_operand:QI 4 "const_int_operand" "")))]
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229 "TARGET_A24"
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230 "#"
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231 "reload_completed"
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232 [(set (reg:CC FLG_REGNO)
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233 (compare (match_dup 1)
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234 (match_dup 2)))
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235 (set (match_dup 0)
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236 (if_then_else:HI (eqne_cond:HI (reg:CC FLG_REGNO) (const_int 0))
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237 (match_dup 3)
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238 (match_dup 4)))]
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239 ""
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240 [(set_attr "flags" "x")]
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241 )
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242
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243 ;; And these are the expanders, which read the pending compare
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244 ;; operands to build a combined insn.
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245
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246 (define_expand "s<code>"
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247 [(set (match_operand:QI 0 "register_operand" "=Rqi")
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248 (any_cond:QI (reg:CC FLG_REGNO) (const_int 0)))]
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249 "TARGET_A16"
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250 "m32c_expand_scc (<CODE>, operands); DONE;")
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251
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252 (define_expand "s<code>_24"
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253 [(set (match_operand:HI 0 "mra_nopp_operand" "=RhiSd")
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254 (any_cond:HI (reg:CC FLG_REGNO) (const_int 0)))]
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255 "TARGET_A24"
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256 "m32c_expand_scc (<CODE>, operands); DONE;")
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257
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258
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259 (define_expand "movqicc"
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260 [(set (match_operand:QI 0 "register_operand" "")
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261 (if_then_else:QI (match_operand 1 "m32c_eqne_operator" "")
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262 (match_operand:QI 2 "const_int_operand" "")
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263 (match_operand:QI 3 "const_int_operand" "")))]
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264 ""
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265 "if (m32c_expand_movcc(operands))
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266 FAIL;
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267 DONE;"
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268 )
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269
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270 (define_expand "movhicc"
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271 [(set (match_operand:HI 0 "mra_operand" "")
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272 (if_then_else:HI (match_operand 1 "m32c_eqne_operator" "")
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273 (match_operand:HI 2 "const_int_operand" "")
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274 (match_operand:HI 3 "const_int_operand" "")))]
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275 "TARGET_A24"
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276 "if (m32c_expand_movcc(operands))
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277 FAIL;
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278 DONE;"
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279 )
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280
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281
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282 ;; CMP opcodes subtract two values, set the flags, and discard the
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283 ;; value. This pattern recovers the sign of the discarded value based
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284 ;; on the flags. Operand 0 is set to -1, 0, or 1. This is used for
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285 ;; the cmpstr pattern. For optimal code, this should be removed if
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286 ;; followed by a suitable CMP insn (see the peephole following). This
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287 ;; pattern is 7 bytes and 5 cycles. If you don't need specific
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288 ;; values, a 5/4 pattern can be made with SCGT and BMLT to set the
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289 ;; appropriate bits.
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290
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291 (define_insn "cond_to_int"
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292 [(set (match_operand:HI 0 "mra_qi_operand" "=Rqi")
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293 (if_then_else:HI (lt (reg:CC FLG_REGNO) (const_int 0))
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294 (const_int -1)
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295 (if_then_else:HI (eq (reg:CC FLG_REGNO) (const_int 0))
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296 (const_int 0)
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297 (const_int -1))))]
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298 "TARGET_A24"
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299 "sceq\t%0\n\tbmgt\t1,%h0\n\tdec.w\t%0"
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300 [(set_attr "flags" "x")]
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301 )
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302
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303 ;; A cond_to_int followed by a compare against zero is essentially a
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304 ;; no-op. However, the result of the cond_to_int may be used by later
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305 ;; insns, so make sure it's dead before deleting its set.
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306
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307 (define_peephole2
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308 [(set (match_operand:HI 0 "mra_qi_operand" "")
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309 (if_then_else:HI (lt (reg:CC FLG_REGNO) (const_int 0))
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310 (const_int -1)
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311 (if_then_else:HI (eq (reg:CC FLG_REGNO) (const_int 0))
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312 (const_int 0)
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313 (const_int -1))))
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314 (set (reg:CC FLG_REGNO)
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315 (compare (match_operand:HI 1 "mra_qi_operand" "")
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316 (const_int 0)))
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317 ]
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318 "rtx_equal_p (operands[0], operands[1])
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319 && dead_or_set_p (peep2_next_insn (1), operands[0])"
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320 [(const_int 1)]
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321 "")
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