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1 ;; Machine Descriptions for R8C/M16C/M32C
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2 ;; Copyright (C) 2005, 2007, 2008
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3 ;; Free Software Foundation, Inc.
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4 ;; Contributed by Red Hat.
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5 ;;
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6 ;; This file is part of GCC.
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7 ;;
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8 ;; GCC is free software; you can redistribute it and/or modify it
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9 ;; under the terms of the GNU General Public License as published
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10 ;; by the Free Software Foundation; either version 3, or (at your
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11 ;; option) any later version.
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12 ;;
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13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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16 ;; License for more details.
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17 ;;
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 ;; move, push, extend, etc.
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23
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24 ;; Be careful to never create an alternative that has memory as both
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25 ;; src and dest, as that makes gcc think that mem-mem moves in general
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26 ;; are supported. While the chip does support this, it only has two
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27 ;; address registers and sometimes gcc requires more than that. One
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28 ;; example is code like this: a = *b where both a and b are spilled to
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29 ;; the stack.
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30
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31 ;; Match push/pop before mov.b for passing char as arg,
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32 ;; e.g. stdlib/efgcvt.c.
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33 (define_insn "movqi_op"
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34 [(set (match_operand:QI 0 "m32c_nonimmediate_operand"
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35 "=Rqi*Rmm, <, RqiSd*Rmm, SdSs, Rqi*Rmm, Sd")
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36 (match_operand:QI 1 "m32c_any_operand"
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37 "iRqi*Rmm, iRqiSd*Rmm, >, Rqi*Rmm, SdSs, i"))]
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38 "m32c_mov_ok (operands, QImode)"
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39 "@
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40 mov.b\t%1,%0
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41 push.b\t%1
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42 pop.b\t%0
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43 mov.b\t%1,%0
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44 mov.b\t%1,%0
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45 mov.b\t%1,%0"
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46 [(set_attr "flags" "sz,*,*,sz,sz,sz")]
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47 )
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48
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49 (define_expand "movqi"
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50 [(set (match_operand:QI 0 "nonimmediate_operand" "=RqiSd*Rmm")
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51 (match_operand:QI 1 "general_operand" "iRqiSd*Rmm"))]
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52 ""
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53 "if (m32c_prepare_move (operands, QImode)) DONE;"
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54 )
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55
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56
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57 (define_insn "movhi_op"
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58 [(set (match_operand:HI 0 "m32c_nonimmediate_operand"
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59 "=Rhi*Rmm, Sd, SdSs, *Rcr, RhiSd*Rmm, <, RhiSd*Rmm, <, *Rcr")
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60 (match_operand:HI 1 "m32c_any_operand"
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61 "iRhi*RmmSdSs, i, Rhi*Rmm, RhiSd*Rmm, *Rcr, iRhiSd*Rmm, >, *Rcr, >"))]
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62 "m32c_mov_ok (operands, HImode)"
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63 "@
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64 mov.w\t%1,%0
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65 mov.w\t%1,%0
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66 mov.w\t%1,%0
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67 ldc\t%1,%0
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68 stc\t%1,%0
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69 push.w\t%1
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70 pop.w\t%0
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71 pushc\t%1
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72 popc\t%0"
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73 [(set_attr "flags" "sz,sz,sz,n,n,n,n,n,n")]
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74 )
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75
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76 (define_expand "movhi"
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77 [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhiSd*Rmm")
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78 (match_operand:HI 1 "m32c_any_operand" "iRhiSd*Rmm"))]
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79 ""
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80 "if (m32c_prepare_move (operands, HImode)) DONE;"
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81 )
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82
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83
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84 (define_insn "movpsi_op"
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85 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand"
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86 "=Raa, SdRmmRpi, Rcl, RpiSd*Rmm, <, <, Rcl, RpiRaa*Rmm")
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87 (match_operand:PSI 1 "m32c_any_operand"
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88 "sIU3, iSdRmmRpi, iRpiSd*Rmm, Rcl, Rpi*Rmm, Rcl, >, >"))]
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89 "TARGET_A24 && m32c_mov_ok (operands, PSImode)"
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90 "@
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91 mov.l:s\t%1,%0
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92 mov.l\t%1,%0
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93 ldc\t%1,%0
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94 stc\t%1,%0
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95 push.l\t%1
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96 pushc\t%1
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97 popc\t%0
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98 #"
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99 [(set_attr "flags" "sz,sz,n,n,n,n,n,*")]
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100 )
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101
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102
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103 ;; The intention here is to combine the add with the move to create an
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104 ;; indexed move. GCC doesn't always figure this out itself.
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105
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106 (define_peephole2
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107 [(set (match_operand:HPSI 0 "register_operand" "")
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108 (plus:HPSI (match_operand:HPSI 1 "register_operand" "")
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109 (match_operand:HPSI 2 "immediate_operand" "")))
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110 (set (match_operand:QHSI 3 "nonimmediate_operand" "")
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111 (mem:QHSI (match_operand:HPSI 4 "register_operand" "")))]
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112 "REGNO (operands[0]) == REGNO (operands[1])
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113 && REGNO (operands[0]) == REGNO (operands[4])
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114 && (rtx_equal_p (operands[0], operands[3])
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115 || (dead_or_set_p (peep2_next_insn (1), operands[4])
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116 && ! reg_mentioned_p (operands[0], operands[3])))"
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117 [(set (match_dup 3)
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118 (mem:QHSI (plus:HPSI (match_dup 1)
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119 (match_dup 2))))]
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120 "")
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121
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122 (define_peephole2
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123 [(set (match_operand:HPSI 0 "register_operand" "")
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124 (plus:HPSI (match_operand:HPSI 1 "register_operand" "")
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125 (match_operand:HPSI 2 "immediate_operand" "")))
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126 (set (mem:QHSI (match_operand:HPSI 4 "register_operand" ""))
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127 (match_operand:QHSI 3 "m32c_any_operand" ""))]
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128 "REGNO (operands[0]) == REGNO (operands[1])
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129 && REGNO (operands[0]) == REGNO (operands[4])
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130 && dead_or_set_p (peep2_next_insn (1), operands[4])
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131 && ! reg_mentioned_p (operands[0], operands[3])"
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132 [(set (mem:QHSI (plus:HPSI (match_dup 1)
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133 (match_dup 2)))
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134 (match_dup 3))]
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135 "")
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136
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137 ; Peephole to generate SImode mov instructions for storing an
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138 ; immediate double data to a memory location.
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139 (define_peephole2
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140 [(set (match_operand:HI 0 "memory_operand" "")
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141 (match_operand 1 "const_int_operand" ""))
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142 (set (match_operand:HI 2 "memory_operand" "")
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143 (match_operand 3 "const_int_operand" ""))]
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144 "TARGET_A24 && m32c_immd_dbl_mov (operands, HImode)"
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145 [(set (match_dup 4) (match_dup 5))]
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146 ""
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147 )
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148
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149 ; Some PSI moves must be split.
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150 (define_split
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151 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "")
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152 (match_operand:PSI 1 "m32c_any_operand" ""))]
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153 "reload_completed && m32c_split_psi_p (operands)"
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154 [(set (match_dup 2)
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155 (match_dup 3))
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156 (set (match_dup 4)
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157 (match_dup 5))]
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158 "m32c_split_move (operands, PSImode, 3);"
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159 )
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160
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161 (define_expand "movpsi"
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162 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "")
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163 (match_operand:PSI 1 "m32c_any_operand" ""))]
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164 ""
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165 "if (m32c_prepare_move (operands, PSImode)) DONE;"
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166 )
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167
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168
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169
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170 (define_expand "movsi"
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171 [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiSd*Rmm")
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172 (match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm"))]
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173 ""
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174 "if (m32c_split_move (operands, SImode, 0)) DONE;"
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175 )
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176
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177 ; All SI moves are split if TARGET_A16
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178 (define_insn_and_split "movsi_splittable"
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179 [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=Rsi<*Rmm,RsiSd*Rmm,Ss")
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180 (match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm,iRsi>*Rmm,Rsi*Rmm"))]
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181 "TARGET_A16"
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182 "#"
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183 "TARGET_A16 && reload_completed"
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184 [(pc)]
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185 "m32c_split_move (operands, SImode, 1); DONE;"
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186 )
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187
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188 ; The movsi pattern doesn't always match because sometimes the modes
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189 ; don't match.
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190 (define_insn "push_a01_l"
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191 [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
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192 (match_operand 0 "a_operand" "Raa"))]
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193 ""
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194 "push.l\t%0"
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195 [(set_attr "flags" "n")]
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196 )
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197
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198 (define_insn "movsi_24"
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199 [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=Rsi*Rmm, Sd, RsiSd*Rmm, <")
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200 (match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm, iRsi*Rmm, >, iRsiRaaSd*Rmm"))]
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201 "TARGET_A24"
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202 "@
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203 mov.l\t%1,%0
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204 mov.l\t%1,%0
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205 #
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206 push.l\t%1"
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207 [(set_attr "flags" "sz,sz,*,n")]
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208 )
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209
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210 (define_expand "movdi"
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211 [(set (match_operand:DI 0 "m32c_nonimmediate_operand" "=RdiSd*Rmm")
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212 (match_operand:DI 1 "m32c_any_operand" "iRdiSd*Rmm"))]
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213 ""
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214 "if (m32c_split_move (operands, DImode, 0)) DONE;"
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215 )
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216
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217 (define_insn_and_split "movdi_splittable"
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218 [(set (match_operand:DI 0 "m32c_nonimmediate_operand" "=Rdi<*Rmm,RdiSd*Rmm")
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219 (match_operand:DI 1 "m32c_any_operand" "iRdiSd*Rmm,iRdi>*Rmm"))]
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220 ""
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221 "#"
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222 "reload_completed"
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223 [(pc)]
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224 "m32c_split_move (operands, DImode, 1); DONE;"
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225 )
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226
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227
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228
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229
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230 (define_insn "pushqi"
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231 [(set (mem:QI (pre_dec:PSI (reg:PSI SP_REGNO)))
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232 (match_operand:QI 0 "mrai_operand" "iRqiSd*Rmm"))]
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233 ""
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234 "push.b\t%0"
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235 [(set_attr "flags" "n")]
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236 )
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237
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238 (define_expand "pushhi"
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239 [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
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240 (match_operand:HI 0 "" ""))]
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241 ""
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242 "if (TARGET_A16)
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243 gen_pushhi_16 (operands[0]);
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244 else
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245 gen_pushhi_24 (operands[0]);
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246 DONE;"
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247 )
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248
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249 (define_insn "pushhi_16"
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250 [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNO)))
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251 (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm,Rcr"))]
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252 "TARGET_A16"
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253 "@
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254 push.w\t%0
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255 pushc\t%0"
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256 [(set_attr "flags" "n,n")]
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257 )
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258
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259 (define_insn "pushhi_24"
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260 [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
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261 (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm"))]
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262 "TARGET_A24"
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263 "push.w\t%0"
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264 [(set_attr "flags" "n")]
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265 )
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266
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267 ;(define_insn "pushpi"
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268 ; [(set (mem:PSI (pre_dec:PSI (reg:PSI SP_REGNO)))
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269 ; (match_operand:PI 0 "mrai_operand" "iRaa,Rcr"))]
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270 ; "TARGET_A24"
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271 ; "@
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272 ; push.l\t%0
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273 ; pushc\t%0"
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274 ; )
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275
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276 (define_insn "pushsi"
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277 [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
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278 (match_operand:SI 0 "mrai_operand" "iRsiSd*Rmm"))]
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279 "TARGET_A24"
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280 "push.l\t%0"
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281 [(set_attr "flags" "n")]
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282 )
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283
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284 (define_expand "pophi"
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285 [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
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286 (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
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287 ""
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288 "if (TARGET_A16)
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289 gen_pophi_16 (operands[0]);
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290 else
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291 gen_pophi_24 (operands[0]);
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292 DONE;"
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293 )
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294
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295 (define_insn "pophi_16"
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296 [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
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297 (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
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298 "TARGET_A16"
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299 "@
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300 pop.w\t%0
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301 popc\t%0"
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302 [(set_attr "flags" "n,n")]
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303 )
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304
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305 (define_insn "pophi_24"
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306 [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm")
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307 (mem:HI (post_inc:PSI (reg:PSI SP_REGNO))))]
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308 "TARGET_A24"
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309 "pop.w\t%0"
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310 [(set_attr "flags" "n")]
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311 )
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312
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313 (define_insn "poppsi"
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314 [(set (match_operand:PSI 0 "cr_operand" "=Rcl")
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315 (mem:PSI (post_inc:PSI (reg:PSI SP_REGNO))))]
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316 "TARGET_A24"
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317 "popc\t%0"
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318 [(set_attr "flags" "n")]
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319 )
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320
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321
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322 ;; Rhl used here as an HI-mode Rxl
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323 (define_insn "extendqihi2"
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324 [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhlSd*Rmm")
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325 (sign_extend:HI (match_operand:QI 1 "mra_operand" "0")))]
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326 ""
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327 "exts.b\t%1"
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328 [(set_attr "flags" "sz")]
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329 )
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330
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331 (define_insn "extendhisi2"
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332 [(set (match_operand:SI 0 "register_operand" "=R03")
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333 (sign_extend:SI (match_operand:HI 1 "r0123_operand" "0")))]
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334 ""
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335 "*
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336 if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
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337 else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
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338 [(set_attr "flags" "x")]
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339 )
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340
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341 (define_insn "extendhipsi2"
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342 [(set (match_operand:PSI 0 "register_operand" "=R03")
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343 (sign_extend:PSI (match_operand:HI 1 "register_operand" "0")))]
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344 ""
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345 "*
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346 if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
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347 else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
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348 [(set_attr "flags" "x")]
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349 )
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350
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351 (define_insn "extendpsisi2"
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352 [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
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353 (sign_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
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354 ""
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355 "; expand psi %1 to si %0"
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356 [(set_attr "flags" "n")]
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357 )
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358
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359 (define_insn "zero_extendpsisi2"
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360 [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
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361 (zero_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
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362 ""
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363 "; expand psi %1 to si %0"
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364 [(set_attr "flags" "n")]
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365 )
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366
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367 (define_insn "zero_extendhipsi2"
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368 [(set (match_operand:PSI 0 "register_operand" "=Raa")
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369 (truncate:PSI (zero_extend:SI (match_operand:HI 1 "register_operand" "R03"))))]
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370 ""
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371 "mov.w\t%1,%0"
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372 [(set_attr "flags" "sz")]
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373 )
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374
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375 (define_insn "zero_extendhisi2"
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376 [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiSd")
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377 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")))]
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378 ""
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379 "mov.w\t#0,%H0"
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380 [(set_attr "flags" "x")]
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381 )
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382
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383 (define_insn "zero_extendqihi2"
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384 [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=?Rhl,RhiSd*Rmm")
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385 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
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386 ""
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387 "@
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388 mov.b\t#0,%H0
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389 and.w\t#255,%0"
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390 [(set_attr "flags" "x,x")]
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391 )
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392
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393 (define_insn "truncsipsi2_16"
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394 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
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395 (truncate:PSI (match_operand:SI 1 "nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
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396 "TARGET_A16"
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397 "@
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398 ; no-op trunc si %1 to psi %0
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399 #
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400 ldc\t%1,%0
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401 stc\t%1,%0"
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402 [(set_attr "flags" "n,*,n,n")]
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403 )
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404
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405 (define_insn "trunchiqi2"
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406 [(set (match_operand:QI 0 "m32c_nonimmediate_operand" "=RqiRmmSd")
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407 (truncate:QI (match_operand:HI 1 "mra_qi_operand" "0")))]
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408 ""
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409 "; no-op trunc hi %1 to qi %0"
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410 [(set_attr "flags" "n")]
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411 )
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412
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413 (define_insn "truncsipsi2_24"
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414 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiSd*Rmm,Raa,!Rcl,RsiSd*Rmm")
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415 (truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,!Rcl")))]
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416 "TARGET_A24"
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417 "@
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418 ; no-op trunc si %1 to psi %0
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419 mov.l\t%1,%0
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420 ldc\t%1,%0
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421 stc\t%1,%0"
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422 [(set_attr "flags" "n,sz,n,n")]
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423 )
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424
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425 (define_expand "truncsipsi2"
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426 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
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427 (truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
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428 ""
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429 ""
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430 )
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431
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432 (define_expand "reload_inqi"
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433 [(set (match_operand:QI 2 "" "=&Rqi")
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434 (match_operand:QI 1 "" ""))
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435 (set (match_operand:QI 0 "" "")
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436 (match_dup 2))
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437 ]
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438 ""
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439 "")
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440
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441 (define_expand "reload_outqi"
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442 [(set (match_operand:QI 2 "" "=&Rqi")
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443 (match_operand:QI 1 "" ""))
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444 (set (match_operand:QI 0 "" "")
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445 (match_dup 2))
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446 ]
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447 ""
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448 "")
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449
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450 (define_expand "reload_inhi"
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451 [(set (match_operand:HI 2 "" "=&Rhi")
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452 (match_operand:HI 1 "" ""))
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453 (set (match_operand:HI 0 "" "")
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454 (match_dup 2))
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455 ]
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456 ""
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457 "")
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458
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459 (define_expand "reload_outhi"
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460 [(set (match_operand:HI 2 "" "=&Rhi")
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461 (match_operand:HI 1 "" ""))
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462 (set (match_operand:HI 0 "" "")
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463 (match_dup 2))
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464 ]
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465 ""
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466 "")
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