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1 ;; Machine Descriptions for R8C/M16C/M32C
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2 ;; Copyright (C) 2005, 2007
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3 ;; Free Software Foundation, Inc.
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4 ;; Contributed by Red Hat.
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5 ;;
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6 ;; This file is part of GCC.
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7 ;;
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8 ;; GCC is free software; you can redistribute it and/or modify it
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9 ;; under the terms of the GNU General Public License as published
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10 ;; by the Free Software Foundation; either version 3, or (at your
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11 ;; option) any later version.
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12 ;;
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13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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16 ;; License for more details.
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17 ;;
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 ;; multiply and divide
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23
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24 ; Here is the pattern for the const_int.
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25 (define_insn "mulqihi3_c"
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26 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
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27 (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
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28 (match_operand 2 "immediate_operand" "i,i")))]
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29 ""
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30 "mul.b\t%2,%1"
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31 [(set_attr "flags" "o")]
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32 )
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33
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34 ; Here is the pattern for registers and such.
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35 (define_insn "mulqihi3_r"
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36 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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37 (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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38 (sign_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
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39 ""
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40 "mul.b\t%2,%1"
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41 [(set_attr "flags" "o")]
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42 )
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43
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44 ; Don't try to sign_extend a const_int. Same for all other multiplies.
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45 (define_expand "mulqihi3"
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46 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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47 (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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48 (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
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49 ""
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50 "{ if (GET_MODE (operands[2]) != VOIDmode)
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51 operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]); }"
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52 )
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53
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54 (define_insn "umulqihi3_c"
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55 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
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56 (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
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57 (match_operand 2 "immediate_operand" "i,i")))]
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58 ""
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59 "mulu.b\t%U2,%1"
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60 [(set_attr "flags" "o")]
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61 )
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62
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63 (define_insn "umulqihi3_r"
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64 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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65 (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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66 (zero_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
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67 ""
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68 "mulu.b\t%U2,%1"
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69 [(set_attr "flags" "o")]
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70 )
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71
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72 (define_expand "umulqihi3"
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73 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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74 (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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75 (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
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76 ""
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77 "{ if (GET_MODE (operands[2]) != VOIDmode)
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78 operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]); }"
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79 )
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80
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81 (define_insn "mulhisi3_c"
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82 [(set (match_operand:SI 0 "ra_operand" "=Rsi")
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83 (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
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84 (match_operand:HI 2 "immediate_operand" "i")))]
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85 ""
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86 "mul.w\t%2,%1"
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87 [(set_attr "flags" "o")]
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88 )
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89
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90 (define_insn "mulhisi3_r"
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91 [(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi")
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92 (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
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93 (sign_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))]
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94 ""
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95 "mul.w\t%2,%1"
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96 [(set_attr "flags" "o")]
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97 )
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98
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99 (define_expand "mulhisi3"
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100 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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101 (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
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102 (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
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103 ""
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104 "{ if (GET_MODE (operands[2]) != VOIDmode)
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105 operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); }"
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106 )
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107
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108 (define_insn "umulhisi3_c"
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109 [(set (match_operand:SI 0 "ra_operand" "=Rsi")
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110 (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
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111 (match_operand 2 "immediate_operand" "i")))]
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112 ""
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113 "mulu.w\t%u2,%1"
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114 [(set_attr "flags" "o")]
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115 )
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116
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117 (define_insn "umulhisi3_r"
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118 [(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi")
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119 (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
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120 (zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))]
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121 ""
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122 "mulu.w\t%u2,%1"
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123 [(set_attr "flags" "o")]
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124 )
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125
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126 (define_expand "umulhisi3"
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127 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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128 (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
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129 (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
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130 ""
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131 "{ if (GET_MODE (operands[2]) != VOIDmode)
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132 operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); }"
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133 )
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134
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135
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136 ; GCC expects to be able to multiply pointer-sized integers too, but
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137 ; fortunately it only multiplies by powers of two, although sometimes
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138 ; they're negative.
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139 (define_insn "mulpsi3_op"
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140 [(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
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141 (mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
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142 (match_operand 2 "m32c_psi_scale" "Ilb")))]
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143 "TARGET_A24"
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144 "shl.l\t%b2,%0"
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145 [(set_attr "flags" "szc")]
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146 )
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147
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148 (define_expand "mulpsi3"
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149 [(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
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150 (mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
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151 (match_operand 2 "m32c_psi_scale" "Ilb")))]
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152 "TARGET_A24"
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153 "if (GET_CODE (operands[2]) != CONST_INT
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154 || ! m32c_psi_scale (operands[2], PSImode))
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155 {
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156 m32c_expand_neg_mulpsi3 (operands);
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157 DONE;
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158 }"
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159 )
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160
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161 (define_insn "mulsi3"
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162 [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
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163 (mult:SI (match_operand:SI 1 "r0123_operand" "%0,0")
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164 (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
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165 "TARGET_M32C"
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166 "mul.l\t%2,%1"
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167 [(set_attr "flags" "o")]
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168 )
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169
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170 (define_expand "divmodqi4"
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171 [(set (match_dup 4)
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172 (sign_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
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173 (parallel [(set (match_operand:QI 0 "register_operand" "=R0w,R0w")
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174 (div:QI (match_dup 4)
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175 (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
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176 (set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
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177 (mod:QI (match_dup 4) (match_dup 2)))
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178 ])]
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179 "0"
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180 "operands[4] = gen_reg_rtx (HImode);"
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181 )
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182
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183 (define_insn "divmodqi4_n"
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184 [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
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185 (div:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
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186 (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
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187 (set (match_operand:QI 3 "register_operand" "=R0h,R0h")
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188 (mod:QI (match_dup 1) (match_dup 2)))
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189 ]
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190 "0"
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191 "div.b\t%2"
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192 [(set_attr "flags" "o")]
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193 )
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194
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195 (define_expand "udivmodqi4"
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196 [(set (match_dup 4)
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197 (zero_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
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198 (parallel [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
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199 (udiv:QI (match_dup 4)
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200 (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
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201 (set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
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202 (umod:QI (match_dup 4) (match_dup 2)))
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203 ])]
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204 "0"
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205 "operands[4] = gen_reg_rtx (HImode);"
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206 )
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207
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208 (define_insn "udivmodqi4_n"
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209 [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
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210 (udiv:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
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211 (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
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212 (set (match_operand:QI 3 "register_operand" "=R0h,R0h")
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213 (umod:QI (match_dup 1) (match_dup 2)))
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214 ]
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215 "0"
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216 "divu.b\t%2"
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217 [(set_attr "flags" "o")]
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218 )
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219
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220 (define_expand "divmodhi4"
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221 [(set (match_dup 4)
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222 (sign_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
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223 (parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
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224 (div:HI (match_dup 4)
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225 (match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
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226 (set (match_operand:HI 3 "register_operand" "=R2w,R2w")
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227 (mod:HI (match_dup 4) (match_dup 2)))
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228 ])]
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229 ""
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230 "operands[4] = gen_reg_rtx (SImode);"
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231 )
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232
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233 (define_insn "divmodhi4_n"
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234 [(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
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235 (div:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
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236 (match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
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237 (set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
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238 (mod:HI (match_dup 1) (match_dup 2)))
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239 ]
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240 ""
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241 "div.w\t%2"
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242 [(set_attr "flags" "o")]
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243 )
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244
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245 (define_expand "udivmodhi4"
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246 [(set (match_dup 4)
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247 (zero_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
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248 (parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
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249 (udiv:HI (match_dup 4)
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250 (match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
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251 (set (match_operand:HI 3 "register_operand" "=R2w,R2w")
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252 (umod:HI (match_dup 4) (match_dup 2)))
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253 ])]
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254 ""
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255 "operands[4] = gen_reg_rtx (SImode);"
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256 )
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257
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258 (define_insn "udivmodhi4_n"
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259 [(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
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260 (udiv:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
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261 (match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
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262 (set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
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263 (umod:HI (match_dup 1) (match_dup 2)))
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264 ]
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265 ""
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266 "divu.w\t%2"
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267 [(set_attr "flags" "o")]
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268 )
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269
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270 (define_insn "divsi3"
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271 [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
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272 (div:SI (match_operand:SI 1 "r0123_operand" "0,0")
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273 (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
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274 "TARGET_M32C"
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275 "div.l\t%2"
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276 [(set_attr "flags" "o")]
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277 )
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278
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279 (define_insn "udivsi3"
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280 [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
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281 (udiv:SI (match_operand:SI 1 "r0123_operand" "0,0")
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282 (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
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283 "TARGET_M32C"
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284 "divu.l\t%2"
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285 [(set_attr "flags" "o")]
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286 )
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287
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288
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