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1 ;; Predicate definitions for Renesas M32R.
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2 ;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; Return true if OP is a register or the constant 0.
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21
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22 (define_predicate "reg_or_zero_operand"
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23 (match_code "reg,subreg,const_int")
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24 {
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25 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
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26 return register_operand (op, mode);
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27
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28 if (GET_CODE (op) != CONST_INT)
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29 return 0;
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30
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31 return INTVAL (op) == 0;
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32 })
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33
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34 ;; Return nonzero if the operand is suitable for use in a conditional
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35 ;; move sequence.
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36
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37 (define_predicate "conditional_move_operand"
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38 (match_code "reg,subreg,const_int")
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39 {
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40 /* Only defined for simple integers so far... */
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41 if (mode != SImode && mode != HImode && mode != QImode)
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42 return FALSE;
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43
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44 /* At the moment we can handle moving registers and loading constants. */
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45 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
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46
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47 switch (GET_CODE (op))
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48 {
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49 case REG:
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50 return 1;
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51
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52 case CONST_INT:
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53 return satisfies_constraint_I (op);
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54
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55 default:
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56 #if 0
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57 fprintf (stderr, "Test for cond move op of type: %s\n",
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58 GET_RTX_NAME (GET_CODE (op)));
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59 #endif
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60 return 0;
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61 }
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62 })
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63
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64 ;; Return true if the code is a test of the carry bit.
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65
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66 (define_predicate "carry_compare_operand"
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67 (match_code "eq,ne")
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68 {
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69 rtx x;
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70
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71 if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
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72 return FALSE;
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73
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74 if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
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75 return FALSE;
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76
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77 x = XEXP (op, 0);
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78 if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
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79 return FALSE;
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80
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81 x = XEXP (op, 1);
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82 if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
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83 return FALSE;
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84
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85 return TRUE;
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86 })
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87
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88 ;; Return 1 if OP is an EQ or NE comparison operator.
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89
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90 (define_predicate "eqne_comparison_operator"
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91 (match_code "eq,ne")
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92 {
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93 enum rtx_code code = GET_CODE (op);
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94
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95 return (code == EQ || code == NE);
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96 })
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97
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98 ;; Return 1 if OP is a signed comparison operator.
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99
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100 (define_predicate "signed_comparison_operator"
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101 (match_code "eq,ne,lt,le,gt,ge")
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102 {
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103 enum rtx_code code = GET_CODE (op);
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104
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105 return (COMPARISON_P (op)
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106 && (code == EQ || code == NE
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107 || code == LT || code == LE || code == GT || code == GE));
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108 })
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109
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110 ;; Return true if OP is an acceptable argument for a move destination.
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111
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112 (define_predicate "move_dest_operand"
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113 (match_code "reg,subreg,mem")
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114 {
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115 switch (GET_CODE (op))
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116 {
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117 case REG :
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118 return register_operand (op, mode);
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119 case SUBREG :
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120 /* (subreg (mem ...) ...) can occur here if the inner part was once a
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121 pseudo-reg and is now a stack slot. */
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122 if (GET_CODE (SUBREG_REG (op)) == MEM)
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123 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
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124 else
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125 return register_operand (op, mode);
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126 case MEM :
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127 if (GET_CODE (XEXP (op, 0)) == POST_INC)
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128 return 0; /* stores can't do post inc */
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129 return address_operand (XEXP (op, 0), mode);
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130 default :
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131 return 0;
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132 }
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133 })
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134
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135 ;; Return true if OP is an acceptable argument for a single word move
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136 ;; source.
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137
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138 (define_predicate "move_src_operand"
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139 (match_code "reg,subreg,mem,const_int,const_double,label_ref,const,symbol_ref")
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140 {
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141 switch (GET_CODE (op))
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142 {
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143 case LABEL_REF :
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144 case SYMBOL_REF :
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145 case CONST :
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146 return addr24_operand (op, mode);
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147 case CONST_INT :
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148 /* ??? We allow more cse opportunities if we only allow constants
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149 loadable with one insn, and split the rest into two. The instances
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150 where this would help should be rare and the current way is
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151 simpler. */
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152 if (HOST_BITS_PER_WIDE_INT > 32)
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153 {
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154 HOST_WIDE_INT rest = INTVAL (op) >> 31;
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155 return (rest == 0 || rest == -1);
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156 }
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157 else
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158 return 1;
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159 case CONST_DOUBLE :
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160 if (mode == SFmode)
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161 return 1;
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162 else if (mode == SImode)
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163 {
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164 /* Large unsigned constants are represented as const_double's. */
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165 unsigned HOST_WIDE_INT low, high;
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166
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167 low = CONST_DOUBLE_LOW (op);
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168 high = CONST_DOUBLE_HIGH (op);
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169 return high == 0 && low <= (unsigned) 0xffffffff;
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170 }
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171 else
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172 return 0;
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173 case REG :
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174 return register_operand (op, mode);
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175 case SUBREG :
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176 /* (subreg (mem ...) ...) can occur here if the inner part was once a
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177 pseudo-reg and is now a stack slot. */
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178 if (GET_CODE (SUBREG_REG (op)) == MEM)
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179 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
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180 else
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181 return register_operand (op, mode);
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182 case MEM :
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183 if (GET_CODE (XEXP (op, 0)) == PRE_INC
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184 || GET_CODE (XEXP (op, 0)) == PRE_DEC)
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185 return 0; /* loads can't do pre-{inc,dec} */
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186 return address_operand (XEXP (op, 0), mode);
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187 default :
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188 return 0;
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189 }
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190 })
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191
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192 ;; Return true if OP is an acceptable argument for a double word move
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193 ;; source.
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194
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195 (define_predicate "move_double_src_operand"
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196 (match_code "reg,subreg,mem,const_int,const_double")
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197 {
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198 switch (GET_CODE (op))
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199 {
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200 case CONST_INT :
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201 case CONST_DOUBLE :
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202 return 1;
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203 case REG :
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204 return register_operand (op, mode);
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205 case SUBREG :
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206 /* (subreg (mem ...) ...) can occur here if the inner part was once a
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207 pseudo-reg and is now a stack slot. */
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208 if (GET_CODE (SUBREG_REG (op)) == MEM)
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209 return move_double_src_operand (SUBREG_REG (op), mode);
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210 else
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211 return register_operand (op, mode);
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212 case MEM :
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213 /* Disallow auto inc/dec for now. */
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214 if (GET_CODE (XEXP (op, 0)) == PRE_DEC
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215 || GET_CODE (XEXP (op, 0)) == PRE_INC)
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216 return 0;
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217 return address_operand (XEXP (op, 0), mode);
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218 default :
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219 return 0;
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220 }
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221 })
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222
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223 ;; Return true if OP is a const_int requiring two instructions to
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224 ;; load.
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225
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226 (define_predicate "two_insn_const_operand"
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227 (match_code "const_int")
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228 {
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229 if (GET_CODE (op) != CONST_INT)
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230 return 0;
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231 if (satisfies_constraint_J (op)
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232 || satisfies_constraint_M (op)
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233 || satisfies_constraint_L (op))
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234 return 0;
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235 return 1;
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236 })
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237
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238 ;; Returns 1 if OP is a symbol reference.
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239
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240 (define_predicate "symbolic_operand"
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241 (match_code "symbol_ref,label_ref,const")
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242 {
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243 switch (GET_CODE (op))
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244 {
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245 case SYMBOL_REF:
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246 case LABEL_REF:
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247 case CONST :
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248 return 1;
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249
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250 default:
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251 return 0;
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252 }
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253 })
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254
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255 ;; Return true if OP is a signed 8-bit immediate value.
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256
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257 (define_predicate "int8_operand"
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258 (match_code "const_int")
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259 {
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260 if (GET_CODE (op) != CONST_INT)
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261 return 0;
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262 return satisfies_constraint_I (op);
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263 })
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264
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265 ;; Return true if OP is an unsigned 16-bit immediate value.
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266
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267 (define_predicate "uint16_operand"
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268 (match_code "const_int")
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269 {
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270 if (GET_CODE (op) != CONST_INT)
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271 return 0;
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272 return satisfies_constraint_K (op);
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273 })
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274
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275 ;; Return true if OP is a register or signed 16-bit value.
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276
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277 (define_predicate "reg_or_int16_operand"
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278 (match_code "reg,subreg,const_int")
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279 {
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280 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
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281 return register_operand (op, mode);
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282 if (GET_CODE (op) != CONST_INT)
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283 return 0;
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284 return satisfies_constraint_J (op);
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285 })
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286
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287 ;; Return true if OP is a register or an unsigned 16-bit value.
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288
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289 (define_predicate "reg_or_uint16_operand"
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290 (match_code "reg,subreg,const_int")
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291 {
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292 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
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293 return register_operand (op, mode);
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294 if (GET_CODE (op) != CONST_INT)
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295 return 0;
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296 return satisfies_constraint_K (op);
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297 })
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298
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299 ;; Return true if OP is a register or signed 16-bit value for
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300 ;; compares.
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301
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302 (define_predicate "reg_or_cmp_int16_operand"
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303 (match_code "reg,subreg,const_int")
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304 {
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305 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
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306 return register_operand (op, mode);
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307 if (GET_CODE (op) != CONST_INT)
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308 return 0;
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309 return satisfies_constraint_P (op);
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310 })
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311
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312 ;; Return true if OP is a register or an integer value that can be
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313 ;; used is SEQ/SNE. We can use either XOR of the value or ADD of the
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314 ;; negative of the value for the constant. Don't allow 0, because
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315 ;; that is special cased.
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316
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317 (define_predicate "reg_or_eq_int16_operand"
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318 (match_code "reg,subreg,const_int")
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319 {
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320 HOST_WIDE_INT value;
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321
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322 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
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323 return register_operand (op, mode);
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324
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325 if (GET_CODE (op) != CONST_INT)
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326 return 0;
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327
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328 value = INTVAL (op);
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329 return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
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330 })
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331
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332 ;; Return true if OP is a signed 16-bit immediate value useful in
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333 ;; comparisons.
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334
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335 (define_predicate "cmp_int16_operand"
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336 (match_code "const_int")
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337 {
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338 if (GET_CODE (op) != CONST_INT)
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339 return 0;
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340 return satisfies_constraint_P (op);
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341 })
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342
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343 ;; Acceptable arguments to the call insn.
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344
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345 (define_predicate "call_address_operand"
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346 (match_code "symbol_ref,label_ref,const")
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347 {
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348 return symbolic_operand (op, mode);
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349
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350 /* Constants and values in registers are not OK, because
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351 the m32r BL instruction can only support PC relative branching. */
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352 })
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353
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354 ;; Return true if OP is an acceptable input argument for a zero/sign
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355 ;; extend operation.
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356
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357 (define_predicate "extend_operand"
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358 (match_code "reg,subreg,mem")
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359 {
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360 rtx addr;
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361
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362 switch (GET_CODE (op))
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363 {
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364 case REG :
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365 case SUBREG :
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366 return register_operand (op, mode);
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367
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368 case MEM :
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369 addr = XEXP (op, 0);
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370 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
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371 return 0; /* loads can't do pre inc/pre dec */
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372
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373 return address_operand (addr, mode);
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374
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375 default :
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376 return 0;
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377 }
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378 })
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379
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380 ;; Return nonzero if the operand is an insn that is a small
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381 ;; insn. Allow const_int 0 as well, which is a placeholder for NOP
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382 ;; slots.
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383
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384 (define_predicate "small_insn_p"
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385 (match_code "insn,call_insn,jump_insn")
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386 {
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387 if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
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388 return 1;
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389
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390 if (! INSN_P (op))
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391 return 0;
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392
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393 return get_attr_length (op) == 2;
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394 })
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395
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396 ;; Return true if op is an integer constant, less than or equal to
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397 ;; MAX_MOVE_BYTES.
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398
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399 (define_predicate "m32r_block_immediate_operand"
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400 (match_code "const_int")
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401 {
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402 if (GET_CODE (op) != CONST_INT
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403 || INTVAL (op) > MAX_MOVE_BYTES
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404 || INTVAL (op) <= 0)
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405 return 0;
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406
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407 return 1;
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408 })
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409
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410 ;; Return nonzero if the operand is an insn that is a large insn.
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411
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412 (define_predicate "large_insn_p"
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413 (match_code "insn,call_insn,jump_insn")
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414 {
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415 if (! INSN_P (op))
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416 return 0;
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417
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418 return get_attr_length (op) != 2;
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419 })
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420
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421 ;; Returns 1 if OP is an acceptable operand for seth/add3.
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422
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423 (define_predicate "seth_add3_operand"
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424 (match_code "symbol_ref,label_ref,const")
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425 {
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426 if (flag_pic)
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427 return 0;
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428
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429 if (GET_CODE (op) == SYMBOL_REF
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430 || GET_CODE (op) == LABEL_REF)
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431 return 1;
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432
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433 if (GET_CODE (op) == CONST
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434 && GET_CODE (XEXP (op, 0)) == PLUS
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435 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
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436 && satisfies_constraint_J (XEXP (XEXP (op, 0), 1)))
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437 return 1;
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438
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439 return 0;
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440 })
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