0
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1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
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2 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify
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8 it under the terms of the GNU General Public License as published by
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9 the Free Software Foundation; either version 3, or (at your option)
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10 any later version.
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11
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12 GCC is distributed in the hope that it will be useful,
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13 but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 GNU General Public License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
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22 if-statements and ?: on it. This way we have compile-time error checking
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23 for both the MOTOROLA and MIT code paths. We do rely on the host compiler
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24 to optimize away all constant tests. */
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25 #if MOTOROLA /* Use the Motorola assembly syntax. */
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26 # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)")
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27 #else
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28 # define MOTOROLA 0 /* Use the MIT assembly syntax. */
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29 # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)")
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30 #endif
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31
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32 /* Handle --with-cpu default option from configure script. */
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33 #define OPTION_DEFAULT_SPECS \
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34 { "cpu", "%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:\
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35 %{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:\
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36 %{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!mcfv4e:\
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37 %{!mcpu=*:%{!march=*:-%(VALUE)}}}}}}}}}}}}}}}}}}}}}" },
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38
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39 /* Pass flags to gas indicating which type of processor we have. This
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40 can be simplified when we can rely on the assembler supporting .cpu
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41 and .arch directives. */
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42
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43 #define ASM_CPU_SPEC "\
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44 %{m68851}%{mno-68851} %{m68881}%{mno-68881} %{msoft-float:-mno-float} \
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45 %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}\
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46 %{m68040}%{m68020-40:-m68040}%{m68020-60:-m68040}\
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47 %{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{mcfv4e}\
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48 %{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\
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49 "
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50 #define ASM_PCREL_SPEC "%{fPIC|fpic|mpcrel:--pcrel} \
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51 %{msep-data|mid-shared-library:--pcrel} \
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52 "
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53
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54 #define ASM_SPEC "%(asm_cpu_spec) %(asm_pcrel_spec)"
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55
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56 #define EXTRA_SPECS \
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57 { "asm_cpu_spec", ASM_CPU_SPEC }, \
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58 { "asm_pcrel_spec", ASM_PCREL_SPEC }, \
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59 SUBTARGET_EXTRA_SPECS
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60
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61 #define SUBTARGET_EXTRA_SPECS
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62
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63 /* Note that some other tm.h files include this one and then override
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64 many of the definitions that relate to assembler syntax. */
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65
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66 #define TARGET_CPU_CPP_BUILTINS() \
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67 do \
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68 { \
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69 builtin_define ("__m68k__"); \
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70 builtin_define_std ("mc68000"); \
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71 /* The other mc680x0 macros have traditionally been derived \
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72 from the tuning setting. For example, -m68020-60 defines \
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73 m68060, even though it generates pure 68020 code. */ \
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74 switch (m68k_tune) \
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75 { \
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76 case u68010: \
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77 builtin_define_std ("mc68010"); \
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78 break; \
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79 \
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80 case u68020: \
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81 builtin_define_std ("mc68020"); \
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82 break; \
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83 \
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84 case u68030: \
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85 builtin_define_std ("mc68030"); \
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86 break; \
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87 \
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88 case u68040: \
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89 builtin_define_std ("mc68040"); \
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90 break; \
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91 \
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92 case u68060: \
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93 builtin_define_std ("mc68060"); \
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94 break; \
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95 \
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96 case u68020_60: \
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97 builtin_define_std ("mc68060"); \
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98 /* Fall through. */ \
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99 case u68020_40: \
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100 builtin_define_std ("mc68040"); \
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101 builtin_define_std ("mc68030"); \
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102 builtin_define_std ("mc68020"); \
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103 break; \
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104 \
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105 case ucpu32: \
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106 builtin_define_std ("mc68332"); \
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107 builtin_define_std ("mcpu32"); \
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108 builtin_define_std ("mc68020"); \
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109 break; \
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110 \
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111 case ucfv1: \
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112 builtin_define ("__mcfv1__"); \
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113 break; \
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114 \
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115 case ucfv2: \
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116 builtin_define ("__mcfv2__"); \
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117 break; \
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118 \
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119 case ucfv3: \
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120 builtin_define ("__mcfv3__"); \
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121 break; \
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122 \
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123 case ucfv4: \
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124 builtin_define ("__mcfv4__"); \
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125 break; \
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126 \
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127 case ucfv4e: \
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128 builtin_define ("__mcfv4e__"); \
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129 break; \
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130 \
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131 case ucfv5: \
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132 builtin_define ("__mcfv5__"); \
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133 break; \
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134 \
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135 default: \
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136 break; \
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137 } \
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138 \
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139 if (TARGET_68881) \
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140 builtin_define ("__HAVE_68881__"); \
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141 \
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142 if (TARGET_COLDFIRE) \
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143 { \
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144 const char *tmp; \
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145 \
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146 tmp = m68k_cpp_cpu_ident ("cf"); \
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147 if (tmp) \
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148 builtin_define (tmp); \
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149 tmp = m68k_cpp_cpu_family ("cf"); \
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150 if (tmp) \
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151 builtin_define (tmp); \
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152 builtin_define ("__mcoldfire__"); \
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153 \
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154 if (TARGET_ISAC) \
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155 builtin_define ("__mcfisac__"); \
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156 else if (TARGET_ISAB) \
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157 { \
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158 builtin_define ("__mcfisab__"); \
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159 /* ISA_B: Legacy 5407 defines. */ \
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160 builtin_define ("__mcf5400__"); \
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161 builtin_define ("__mcf5407__"); \
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162 } \
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163 else if (TARGET_ISAAPLUS) \
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164 { \
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165 builtin_define ("__mcfisaaplus__"); \
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166 /* ISA_A+: legacy defines. */ \
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167 builtin_define ("__mcf528x__"); \
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168 builtin_define ("__mcf5200__"); \
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169 } \
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170 else \
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171 { \
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172 builtin_define ("__mcfisaa__"); \
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173 /* ISA_A: legacy defines. */ \
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174 switch (m68k_tune) \
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175 { \
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176 case ucfv2: \
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177 builtin_define ("__mcf5200__"); \
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178 break; \
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179 \
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180 case ucfv3: \
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181 builtin_define ("__mcf5307__"); \
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182 builtin_define ("__mcf5300__"); \
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183 break; \
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184 \
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185 default: \
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186 break; \
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187 } \
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188 } \
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189 } \
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190 \
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191 if (TARGET_COLDFIRE_FPU) \
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192 builtin_define ("__mcffpu__"); \
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193 \
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194 if (TARGET_CF_HWDIV) \
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195 builtin_define ("__mcfhwdiv__"); \
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196 \
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197 if (TARGET_FIDOA) \
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198 builtin_define ("__mfido__"); \
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199 \
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200 builtin_assert ("cpu=m68k"); \
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201 builtin_assert ("machine=m68k"); \
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202 } \
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203 while (0)
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204
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205 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
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206 quantities. */
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207 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
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208 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
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209 #define INT_OP_NO_DOT 2 /* byte, short, long */
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210 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
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211
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212 /* Set the default. */
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213 #define INT_OP_GROUP INT_OP_DOT_WORD
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214
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215 /* Bit values used by m68k-devices.def to identify processor capabilities. */
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216 #define FL_BITFIELD (1 << 0) /* Support bitfield instructions. */
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217 #define FL_68881 (1 << 1) /* (Default) support for 68881/2. */
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218 #define FL_COLDFIRE (1 << 2) /* ColdFire processor. */
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219 #define FL_CF_HWDIV (1 << 3) /* ColdFire hardware divide supported. */
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220 #define FL_CF_MAC (1 << 4) /* ColdFire MAC unit supported. */
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221 #define FL_CF_EMAC (1 << 5) /* ColdFire eMAC unit supported. */
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222 #define FL_CF_EMAC_B (1 << 6) /* ColdFire eMAC-B unit supported. */
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223 #define FL_CF_USP (1 << 7) /* ColdFire User Stack Pointer supported. */
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224 #define FL_CF_FPU (1 << 8) /* ColdFire FPU supported. */
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225 #define FL_ISA_68000 (1 << 9)
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226 #define FL_ISA_68010 (1 << 10)
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227 #define FL_ISA_68020 (1 << 11)
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228 #define FL_ISA_68040 (1 << 12)
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229 #define FL_ISA_A (1 << 13)
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230 #define FL_ISA_APLUS (1 << 14)
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231 #define FL_ISA_B (1 << 15)
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232 #define FL_ISA_C (1 << 16)
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233 #define FL_FIDOA (1 << 17)
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234 #define FL_MMU 0 /* Used by multilib machinery. */
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235
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236 #define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0)
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237 #define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0)
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238 #define TARGET_68040 ((m68k_cpu_flags & FL_ISA_68040) != 0)
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239 #define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0)
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240 #define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE)
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241 #define TARGET_68881 (m68k_fpu == FPUTYPE_68881)
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242 #define TARGET_FIDOA ((m68k_cpu_flags & FL_FIDOA) != 0)
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243
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244 /* Size (in bytes) of FPU registers. */
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245 #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12)
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246
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247 #define TARGET_ISAAPLUS ((m68k_cpu_flags & FL_ISA_APLUS) != 0)
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248 #define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0)
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249 #define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0)
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250
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251 /* Some instructions are common to more than one ISA. */
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252 #define ISA_HAS_MVS_MVZ (TARGET_ISAB || TARGET_ISAC)
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253 #define ISA_HAS_FF1 (TARGET_ISAAPLUS || TARGET_ISAC)
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254
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255 #define TUNE_68000 (m68k_tune == u68000)
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256 #define TUNE_68010 (m68k_tune == u68010)
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257 #define TUNE_68000_10 (TUNE_68000 || TUNE_68010)
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258 #define TUNE_68030 (m68k_tune == u68030 \
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259 || m68k_tune == u68020_40 \
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260 || m68k_tune == u68020_60)
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261 #define TUNE_68040 (m68k_tune == u68040 \
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262 || m68k_tune == u68020_40 \
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263 || m68k_tune == u68020_60)
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264 #define TUNE_68060 (m68k_tune == u68060 || m68k_tune == u68020_60)
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265 #define TUNE_68040_60 (TUNE_68040 || TUNE_68060)
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266 #define TUNE_CPU32 (m68k_tune == ucpu32)
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267 #define TUNE_CFV1 (m68k_tune == ucfv1)
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268 #define TUNE_CFV2 (m68k_tune == ucfv2)
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269 #define TUNE_CFV3 (m68k_tune == ucfv3)
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270 #define TUNE_CFV4 (m68k_tune == ucfv4 || m68k_tune == ucfv4e)
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271
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272 #define TUNE_MAC ((m68k_tune_flags & FL_CF_MAC) != 0)
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273 #define TUNE_EMAC ((m68k_tune_flags & FL_CF_EMAC) != 0)
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274
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275 #define OVERRIDE_OPTIONS override_options()
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276
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277 /* These are meant to be redefined in the host dependent files */
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278 #define SUBTARGET_OVERRIDE_OPTIONS
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279
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280 /* target machine storage layout */
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281
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282 /* "long double" is the same as "double" on ColdFire and fido
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283 targets. */
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284
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285 #define LONG_DOUBLE_TYPE_SIZE \
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286 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 64 : 80)
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287
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288 /* We need to know the size of long double at compile-time in libgcc2. */
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289
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290 #if defined(__mcoldfire__) || defined(__mfido__)
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291 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
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292 #else
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293 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80
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294 #endif
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295
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296 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
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297 instructions, we get proper intermediate rounding, otherwise we
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298 get extended precision results. */
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299 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040 || ! TARGET_68881) ? 0 : 2)
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300
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301 #define BITS_BIG_ENDIAN 1
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302 #define BYTES_BIG_ENDIAN 1
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303 #define WORDS_BIG_ENDIAN 1
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304
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305 #define UNITS_PER_WORD 4
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306
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307 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
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308 #define STACK_BOUNDARY 16
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309 #define FUNCTION_BOUNDARY 16
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310 #define EMPTY_FIELD_BOUNDARY 16
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311 /* ColdFire and fido strongly prefer a 32-bit aligned stack. */
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312 #define PREFERRED_STACK_BOUNDARY \
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313 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 32 : 16)
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314
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315 /* No data type wants to be aligned rounder than this.
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316 Most published ABIs say that ints should be aligned on 16-bit
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317 boundaries, but CPUs with 32-bit busses get better performance
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318 aligned on 32-bit boundaries. */
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319 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
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320
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321 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
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322 #define M68K_HONOR_TARGET_STRICT_ALIGNMENT 1
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323
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324 #define DWARF_CIE_DATA_ALIGNMENT -2
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325
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326 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
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327
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328 /* Define these to avoid dependence on meaning of `int'. */
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329 #define WCHAR_TYPE "long int"
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330 #define WCHAR_TYPE_SIZE 32
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331
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332 /* Maximum number of library IDs we permit with -mid-shared-library. */
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333 #define MAX_LIBRARY_ID 255
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334
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335
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336 /* Standard register usage. */
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337
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338 /* For the m68k, we give the data registers numbers 0-7,
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339 the address registers numbers 010-017 (8-15),
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340 and the 68881 floating point registers numbers 020-027 (16-23).
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341 We also have a fake `arg-pointer' register 030 (24) used for
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342 register elimination. */
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343 #define FIRST_PSEUDO_REGISTER 25
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344
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345 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */
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346 #define PIC_OFFSET_TABLE_REGNUM \
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347 (!flag_pic ? INVALID_REGNUM \
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348 : reload_completed ? REGNO (pic_offset_table_rtx) \
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349 : PIC_REG)
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350
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351 /* 1 for registers that have pervasive standard uses
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352 and are not available for the register allocator.
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353 On the m68k, only the stack pointer is such.
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354 Our fake arg-pointer is obviously fixed as well. */
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355 #define FIXED_REGISTERS \
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356 {/* Data registers. */ \
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357 0, 0, 0, 0, 0, 0, 0, 0, \
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358 \
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359 /* Address registers. */ \
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360 0, 0, 0, 0, 0, 0, 0, 1, \
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361 \
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362 /* Floating point registers \
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363 (if available). */ \
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364 0, 0, 0, 0, 0, 0, 0, 0, \
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365 \
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366 /* Arg pointer. */ \
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367 1 }
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368
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369 /* 1 for registers not available across function calls.
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370 These must include the FIXED_REGISTERS and also any
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371 registers that can be used without being saved.
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372 The latter must include the registers where values are returned
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373 and the register where structure-value addresses are passed.
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374 Aside from that, you can include as many other registers as you like. */
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375 #define CALL_USED_REGISTERS \
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376 {/* Data registers. */ \
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377 1, 1, 0, 0, 0, 0, 0, 0, \
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378 \
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379 /* Address registers. */ \
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380 1, 1, 0, 0, 0, 0, 0, 1, \
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381 \
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382 /* Floating point registers \
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383 (if available). */ \
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384 1, 1, 0, 0, 0, 0, 0, 0, \
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385 \
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386 /* Arg pointer. */ \
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387 1 }
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388
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389 #define REG_ALLOC_ORDER \
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390 { /* d0/d1/a0/a1 */ \
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391 0, 1, 8, 9, \
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392 /* d2-d7 */ \
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393 2, 3, 4, 5, 6, 7, \
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394 /* a2-a7/arg */ \
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395 10, 11, 12, 13, 14, 15, 24, \
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396 /* fp0-fp7 */ \
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397 16, 17, 18, 19, 20, 21, 22, 23\
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398 }
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399
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400
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401 /* Make sure everything's fine if we *don't* have a given processor.
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402 This assumes that putting a register in fixed_regs will keep the
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403 compiler's mitts completely off it. We don't bother to zero it out
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404 of register classes. */
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405 #define CONDITIONAL_REGISTER_USAGE \
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406 { \
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407 int i; \
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408 HARD_REG_SET x; \
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409 if (!TARGET_HARD_FLOAT) \
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410 { \
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411 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
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412 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
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413 if (TEST_HARD_REG_BIT (x, i)) \
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414 fixed_regs[i] = call_used_regs[i] = 1; \
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415 } \
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416 if (flag_pic) \
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417 fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1; \
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418 }
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419
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420 /* On the m68k, ordinary registers hold 32 bits worth;
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421 for the 68881 registers, a single register is always enough for
|
|
422 anything that can be stored in them at all. */
|
|
423 #define HARD_REGNO_NREGS(REGNO, MODE) \
|
|
424 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
|
|
425 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
|
|
426
|
|
427 /* A C expression that is nonzero if hard register NEW_REG can be
|
|
428 considered for use as a rename register for OLD_REG register. */
|
|
429
|
|
430 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
|
|
431 m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
|
|
432
|
|
433 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
|
|
434 m68k_regno_mode_ok ((REGNO), (MODE))
|
|
435
|
|
436 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
|
|
437 m68k_secondary_reload_class (CLASS, MODE, X)
|
|
438
|
|
439 #define MODES_TIEABLE_P(MODE1, MODE2) \
|
|
440 (! TARGET_HARD_FLOAT \
|
|
441 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
|
|
442 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
|
|
443 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
|
|
444 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
|
|
445
|
|
446 /* Specify the registers used for certain standard purposes.
|
|
447 The values of these macros are register numbers. */
|
|
448
|
|
449 #define STACK_POINTER_REGNUM SP_REG
|
|
450
|
|
451 /* Most m68k targets use %a6 as a frame pointer. The AmigaOS
|
|
452 ABI uses %a6 for shared library calls, therefore the frame
|
|
453 pointer is shifted to %a5 on this target. */
|
|
454 #define FRAME_POINTER_REGNUM A6_REG
|
|
455
|
|
456 #define FRAME_POINTER_REQUIRED 0
|
|
457
|
|
458 /* Base register for access to arguments of the function.
|
|
459 * This isn't a hardware register. It will be eliminated to the
|
|
460 * stack pointer or frame pointer.
|
|
461 */
|
|
462 #define ARG_POINTER_REGNUM 24
|
|
463
|
|
464 #define STATIC_CHAIN_REGNUM A0_REG
|
|
465 #define M68K_STATIC_CHAIN_REG_NAME REGISTER_PREFIX "a0"
|
|
466
|
|
467 /* Register in which address to store a structure value
|
|
468 is passed to a function. */
|
|
469 #define M68K_STRUCT_VALUE_REGNUM A1_REG
|
|
470
|
|
471
|
|
472
|
|
473 /* The m68k has three kinds of registers, so eight classes would be
|
|
474 a complete set. One of them is not needed. */
|
|
475 enum reg_class {
|
|
476 NO_REGS, DATA_REGS,
|
|
477 ADDR_REGS, FP_REGS,
|
|
478 GENERAL_REGS, DATA_OR_FP_REGS,
|
|
479 ADDR_OR_FP_REGS, ALL_REGS,
|
|
480 LIM_REG_CLASSES };
|
|
481
|
|
482 #define N_REG_CLASSES (int) LIM_REG_CLASSES
|
|
483
|
|
484 #define REG_CLASS_NAMES \
|
|
485 { "NO_REGS", "DATA_REGS", \
|
|
486 "ADDR_REGS", "FP_REGS", \
|
|
487 "GENERAL_REGS", "DATA_OR_FP_REGS", \
|
|
488 "ADDR_OR_FP_REGS", "ALL_REGS" }
|
|
489
|
|
490 #define REG_CLASS_CONTENTS \
|
|
491 { \
|
|
492 {0x00000000}, /* NO_REGS */ \
|
|
493 {0x000000ff}, /* DATA_REGS */ \
|
|
494 {0x0100ff00}, /* ADDR_REGS */ \
|
|
495 {0x00ff0000}, /* FP_REGS */ \
|
|
496 {0x0100ffff}, /* GENERAL_REGS */ \
|
|
497 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
|
|
498 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \
|
|
499 {0x01ffffff}, /* ALL_REGS */ \
|
|
500 }
|
|
501
|
|
502 extern enum reg_class regno_reg_class[];
|
|
503 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)])
|
|
504 #define INDEX_REG_CLASS GENERAL_REGS
|
|
505 #define BASE_REG_CLASS ADDR_REGS
|
|
506
|
|
507 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
|
|
508 m68k_preferred_reload_class (X, CLASS)
|
|
509
|
|
510 /* On the m68k, this is the size of MODE in words,
|
|
511 except in the FP regs, where a single reg is always enough. */
|
|
512 #define CLASS_MAX_NREGS(CLASS, MODE) \
|
|
513 ((CLASS) == FP_REGS ? 1 \
|
|
514 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
|
|
515
|
|
516 /* Moves between fp regs and other regs are two insns. */
|
|
517 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
|
|
518 ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2)
|
|
519
|
|
520 #define IRA_COVER_CLASSES \
|
|
521 { \
|
|
522 ALL_REGS, LIM_REG_CLASSES \
|
|
523 }
|
|
524
|
|
525 /* Stack layout; function entry, exit and calling. */
|
|
526
|
|
527 #define STACK_GROWS_DOWNWARD 1
|
|
528 #define FRAME_GROWS_DOWNWARD 1
|
|
529 #define STARTING_FRAME_OFFSET 0
|
|
530
|
|
531 /* On the 680x0, sp@- in a byte insn really pushes a word.
|
|
532 On the ColdFire, sp@- in a byte insn pushes just a byte. */
|
|
533 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
|
|
534
|
|
535 #define FIRST_PARM_OFFSET(FNDECL) 8
|
|
536
|
|
537 /* On the 68000, the RTS insn cannot pop anything.
|
|
538 On the 68010, the RTD insn may be used to pop them if the number
|
|
539 of args is fixed, but if the number is variable then the caller
|
|
540 must pop them all. RTD can't be used for library calls now
|
|
541 because the library is compiled with the Unix compiler.
|
|
542 Use of RTD is a selectable option, since it is incompatible with
|
|
543 standard Unix calling sequences. If the option is not selected,
|
|
544 the caller must always pop the args. */
|
|
545 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
|
|
546 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
|
|
547 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
|
|
548 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
|
|
549 == void_type_node))) \
|
|
550 ? (SIZE) : 0)
|
|
551
|
|
552 /* On the m68k the return value defaults to D0. */
|
|
553 #define FUNCTION_VALUE(VALTYPE, FUNC) \
|
|
554 gen_rtx_REG (TYPE_MODE (VALTYPE), D0_REG)
|
|
555
|
|
556 /* On the m68k the return value defaults to D0. */
|
|
557 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, D0_REG)
|
|
558
|
|
559 /* On the m68k, D0 is usually the only register used. */
|
|
560 #define FUNCTION_VALUE_REGNO_P(N) ((N) == D0_REG)
|
|
561
|
|
562 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
|
|
563 more than one register.
|
|
564 XXX This macro is m68k specific and used only for m68kemb.h. */
|
|
565 #define NEEDS_UNTYPED_CALL 0
|
|
566
|
|
567 /* On the m68k, all arguments are usually pushed on the stack. */
|
|
568 #define FUNCTION_ARG_REGNO_P(N) 0
|
|
569
|
|
570 /* On the m68k, this is a single integer, which is a number of bytes
|
|
571 of arguments scanned so far. */
|
|
572 #define CUMULATIVE_ARGS int
|
|
573
|
|
574 /* On the m68k, the offset starts at 0. */
|
|
575 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
|
|
576 ((CUM) = 0)
|
|
577
|
|
578 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
|
|
579 ((CUM) += ((MODE) != BLKmode \
|
|
580 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
|
|
581 : (int_size_in_bytes (TYPE) + 3) & ~3))
|
|
582
|
|
583 /* On the m68k all args are always pushed. */
|
|
584 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
|
|
585
|
|
586 #define FUNCTION_PROFILER(FILE, LABELNO) \
|
|
587 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
|
|
588
|
|
589 #define EXIT_IGNORE_STACK 1
|
|
590
|
|
591 /* Output assembler code for a block containing the constant parts
|
|
592 of a trampoline, leaving space for the variable parts.
|
|
593
|
|
594 On the m68k, the trampoline looks like this:
|
|
595 movl #STATIC,a0
|
|
596 jmp FUNCTION
|
|
597
|
|
598 WARNING: Targets that may run on 68040+ cpus must arrange for
|
|
599 the instruction cache to be flushed. Previous incarnations of
|
|
600 the m68k trampoline code attempted to get around this by either
|
|
601 using an out-of-line transfer function or pc-relative data, but
|
|
602 the fact remains that the code to jump to the transfer function
|
|
603 or the code to load the pc-relative data needs to be flushed
|
|
604 just as much as the "variable" portion of the trampoline.
|
|
605 Recognizing that a cache flush is going to be required anyway,
|
|
606 dispense with such notions and build a smaller trampoline.
|
|
607
|
|
608 Since more instructions are required to move a template into
|
|
609 place than to create it on the spot, don't use a template. */
|
|
610
|
|
611 #define TRAMPOLINE_SIZE 12
|
|
612 #define TRAMPOLINE_ALIGNMENT 16
|
|
613
|
|
614 /* Targets redefine this to invoke code to either flush the cache,
|
|
615 or enable stack execution (or both). */
|
|
616 #ifndef FINALIZE_TRAMPOLINE
|
|
617 #define FINALIZE_TRAMPOLINE(TRAMP)
|
|
618 #endif
|
|
619
|
|
620 /* We generate a two-instructions program at address TRAMP :
|
|
621 movea.l &CXT,%a0
|
|
622 jmp FNADDR */
|
|
623 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
|
|
624 { \
|
|
625 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), \
|
|
626 GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9))); \
|
|
627 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
|
|
628 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
|
|
629 GEN_INT(0x4EF9)); \
|
|
630 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
|
|
631 FINALIZE_TRAMPOLINE(TRAMP); \
|
|
632 }
|
|
633
|
|
634 /* This is the library routine that is used to transfer control from the
|
|
635 trampoline to the actual nested function. It is defined for backward
|
|
636 compatibility, for linking with object code that used the old trampoline
|
|
637 definition.
|
|
638
|
|
639 A colon is used with no explicit operands to cause the template string
|
|
640 to be scanned for %-constructs.
|
|
641
|
|
642 The function name __transfer_from_trampoline is not actually used.
|
|
643 The function definition just permits use of "asm with operands"
|
|
644 (though the operand list is empty). */
|
|
645 #define TRANSFER_FROM_TRAMPOLINE \
|
|
646 void \
|
|
647 __transfer_from_trampoline () \
|
|
648 { \
|
|
649 register char *a0 asm (M68K_STATIC_CHAIN_REG_NAME); \
|
|
650 asm (GLOBAL_ASM_OP "___trampoline"); \
|
|
651 asm ("___trampoline:"); \
|
|
652 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
|
|
653 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
|
|
654 asm ("rts":); \
|
|
655 }
|
|
656
|
|
657 /* There are two registers that can always be eliminated on the m68k.
|
|
658 The frame pointer and the arg pointer can be replaced by either the
|
|
659 hard frame pointer or to the stack pointer, depending upon the
|
|
660 circumstances. The hard frame pointer is not used before reload and
|
|
661 so it is not eligible for elimination. */
|
|
662 #define ELIMINABLE_REGS \
|
|
663 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
|
|
664 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
|
|
665 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
|
|
666
|
|
667 #define CAN_ELIMINATE(FROM, TO) \
|
|
668 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
|
|
669
|
|
670 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
|
671 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
|
|
672
|
|
673 /* Addressing modes, and classification of registers for them. */
|
|
674
|
|
675 #define HAVE_POST_INCREMENT 1
|
|
676 #define HAVE_PRE_DECREMENT 1
|
|
677
|
|
678 /* Macros to check register numbers against specific register classes. */
|
|
679
|
|
680 /* True for data registers, D0 through D7. */
|
|
681 #define DATA_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 7)
|
|
682
|
|
683 /* True for address registers, A0 through A7. */
|
|
684 #define ADDRESS_REGNO_P(REGNO) IN_RANGE (REGNO, 8, 15)
|
|
685
|
|
686 /* True for integer registers, D0 through D7 and A0 through A7. */
|
|
687 #define INT_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 15)
|
|
688
|
|
689 /* True for floating point registers, FP0 through FP7. */
|
|
690 #define FP_REGNO_P(REGNO) IN_RANGE (REGNO, 16, 23)
|
|
691
|
|
692 #define REGNO_OK_FOR_INDEX_P(REGNO) \
|
|
693 (INT_REGNO_P (REGNO) \
|
|
694 || INT_REGNO_P (reg_renumber[REGNO]))
|
|
695
|
|
696 #define REGNO_OK_FOR_BASE_P(REGNO) \
|
|
697 (ADDRESS_REGNO_P (REGNO) \
|
|
698 || ADDRESS_REGNO_P (reg_renumber[REGNO]))
|
|
699
|
|
700 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \
|
|
701 (INT_REGNO_P (REGNO) \
|
|
702 || REGNO == ARG_POINTER_REGNUM \
|
|
703 || REGNO >= FIRST_PSEUDO_REGISTER)
|
|
704
|
|
705 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \
|
|
706 (ADDRESS_REGNO_P (REGNO) \
|
|
707 || REGNO == ARG_POINTER_REGNUM \
|
|
708 || REGNO >= FIRST_PSEUDO_REGISTER)
|
|
709
|
|
710 /* Now macros that check whether X is a register and also,
|
|
711 strictly, whether it is in a specified class.
|
|
712
|
|
713 These macros are specific to the m68k, and may be used only
|
|
714 in code for printing assembler insns and in conditions for
|
|
715 define_optimization. */
|
|
716
|
|
717 /* 1 if X is a data register. */
|
|
718 #define DATA_REG_P(X) (REG_P (X) && DATA_REGNO_P (REGNO (X)))
|
|
719
|
|
720 /* 1 if X is an fp register. */
|
|
721 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
|
|
722
|
|
723 /* 1 if X is an address register */
|
|
724 #define ADDRESS_REG_P(X) (REG_P (X) && ADDRESS_REGNO_P (REGNO (X)))
|
|
725
|
|
726 /* True if SYMBOL + OFFSET constants must refer to something within
|
|
727 SYMBOL's section. */
|
|
728 #ifndef M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
|
|
729 #define M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
|
|
730 #endif
|
|
731
|
|
732 #define MAX_REGS_PER_ADDRESS 2
|
|
733
|
|
734 #define CONSTANT_ADDRESS_P(X) \
|
|
735 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
|
|
736 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
|
|
737 || GET_CODE (X) == HIGH) \
|
|
738 && LEGITIMATE_CONSTANT_P (X))
|
|
739
|
|
740 /* Nonzero if the constant value X is a legitimate general operand.
|
|
741 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
|
|
742 #define LEGITIMATE_CONSTANT_P(X) \
|
|
743 (GET_MODE (X) != XFmode \
|
|
744 && !m68k_illegitimate_symbolic_constant_p (X))
|
|
745
|
|
746 #ifndef REG_OK_STRICT
|
|
747 #define REG_STRICT_P 0
|
|
748 #else
|
|
749 #define REG_STRICT_P 1
|
|
750 #endif
|
|
751
|
|
752 #define LEGITIMATE_PIC_OPERAND_P(X) \
|
|
753 (!symbolic_operand (X, VOIDmode) \
|
|
754 || (TARGET_PCREL && REG_STRICT_P))
|
|
755
|
|
756 #define REG_OK_FOR_BASE_P(X) \
|
|
757 m68k_legitimate_base_reg_p (X, REG_STRICT_P)
|
|
758
|
|
759 #define REG_OK_FOR_INDEX_P(X) \
|
|
760 m68k_legitimate_index_reg_p (X, REG_STRICT_P)
|
|
761
|
|
762 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
|
|
763 do \
|
|
764 { \
|
|
765 if (m68k_legitimate_address_p (MODE, X, REG_STRICT_P)) \
|
|
766 goto ADDR; \
|
|
767 } \
|
|
768 while (0)
|
|
769
|
|
770 /* This address is OK as it stands. */
|
|
771 #define PIC_CASE_VECTOR_ADDRESS(index) index
|
|
772
|
|
773 /* For the 68000, we handle X+REG by loading X into a register R and
|
|
774 using R+REG. R will go in an address reg and indexing will be used.
|
|
775 However, if REG is a broken-out memory address or multiplication,
|
|
776 nothing needs to be done because REG can certainly go in an address reg. */
|
|
777 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
|
|
778 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
|
|
779 { register int ch = (X) != (OLDX); \
|
|
780 if (GET_CODE (X) == PLUS) \
|
|
781 { int copied = 0; \
|
|
782 if (GET_CODE (XEXP (X, 0)) == MULT) \
|
|
783 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
|
|
784 if (GET_CODE (XEXP (X, 1)) == MULT) \
|
|
785 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
|
|
786 if (ch && GET_CODE (XEXP (X, 1)) == REG \
|
|
787 && GET_CODE (XEXP (X, 0)) == REG) \
|
|
788 { if (TARGET_COLDFIRE_FPU \
|
|
789 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
|
|
790 { COPY_ONCE (X); X = force_operand (X, 0);} \
|
|
791 goto WIN; } \
|
|
792 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
|
|
793 if (GET_CODE (XEXP (X, 0)) == REG \
|
|
794 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
|
|
795 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
|
|
796 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
|
|
797 { register rtx temp = gen_reg_rtx (Pmode); \
|
|
798 register rtx val = force_operand (XEXP (X, 1), 0); \
|
|
799 emit_move_insn (temp, val); \
|
|
800 COPY_ONCE (X); \
|
|
801 XEXP (X, 1) = temp; \
|
|
802 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
|
|
803 && GET_CODE (XEXP (X, 0)) == REG) \
|
|
804 X = force_operand (X, 0); \
|
|
805 goto WIN; } \
|
|
806 else if (GET_CODE (XEXP (X, 1)) == REG \
|
|
807 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
|
|
808 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
|
|
809 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
|
|
810 { register rtx temp = gen_reg_rtx (Pmode); \
|
|
811 register rtx val = force_operand (XEXP (X, 0), 0); \
|
|
812 emit_move_insn (temp, val); \
|
|
813 COPY_ONCE (X); \
|
|
814 XEXP (X, 0) = temp; \
|
|
815 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
|
|
816 && GET_CODE (XEXP (X, 1)) == REG) \
|
|
817 X = force_operand (X, 0); \
|
|
818 goto WIN; }}}
|
|
819
|
|
820 /* On the 68000, only predecrement and postincrement address depend thus
|
|
821 (the amount of decrement or increment being the length of the operand).
|
|
822 These are now treated generically in recog.c. */
|
|
823 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
|
|
824
|
|
825 #define CASE_VECTOR_MODE HImode
|
|
826 #define CASE_VECTOR_PC_RELATIVE 1
|
|
827
|
|
828 #define DEFAULT_SIGNED_CHAR 1
|
|
829 #define MOVE_MAX 4
|
|
830 #define SLOW_BYTE_ACCESS 0
|
|
831
|
|
832 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
|
|
833
|
|
834 /* The ColdFire FF1 instruction returns 32 for zero. */
|
|
835 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
|
|
836
|
|
837 #define STORE_FLAG_VALUE (-1)
|
|
838
|
|
839 #define Pmode SImode
|
|
840 #define FUNCTION_MODE QImode
|
|
841
|
|
842
|
|
843 /* Tell final.c how to eliminate redundant test instructions. */
|
|
844
|
|
845 /* Here we define machine-dependent flags and fields in cc_status
|
|
846 (see `conditions.h'). */
|
|
847
|
|
848 /* Set if the cc value is actually in the 68881, so a floating point
|
|
849 conditional branch must be output. */
|
|
850 #define CC_IN_68881 04000
|
|
851
|
|
852 /* On the 68000, all the insns to store in an address register fail to
|
|
853 set the cc's. However, in some cases these instructions can make it
|
|
854 possibly invalid to use the saved cc's. In those cases we clear out
|
|
855 some or all of the saved cc's so they won't be used. */
|
|
856 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
|
|
857
|
|
858 /* The shift instructions always clear the overflow bit. */
|
|
859 #define CC_OVERFLOW_UNUSABLE 01000
|
|
860
|
|
861 /* The shift instructions use the carry bit in a way not compatible with
|
|
862 conditional branches. conditions.h uses CC_NO_OVERFLOW for this purpose.
|
|
863 Rename it to something more understandable. */
|
|
864 #define CC_NO_CARRY CC_NO_OVERFLOW
|
|
865
|
|
866 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
|
|
867 do { if (cc_prev_status.flags & CC_IN_68881) \
|
|
868 return FLOAT; \
|
|
869 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
|
|
870 return NO_OV; \
|
|
871 return NORMAL; } while (0)
|
|
872
|
|
873 /* Control the assembler format that we output. */
|
|
874
|
|
875 #define ASM_APP_ON "#APP\n"
|
|
876 #define ASM_APP_OFF "#NO_APP\n"
|
|
877 #define TEXT_SECTION_ASM_OP "\t.text"
|
|
878 #define DATA_SECTION_ASM_OP "\t.data"
|
|
879 #define GLOBAL_ASM_OP "\t.globl\t"
|
|
880 #define REGISTER_PREFIX ""
|
|
881 #define LOCAL_LABEL_PREFIX ""
|
|
882 #define USER_LABEL_PREFIX "_"
|
|
883 #define IMMEDIATE_PREFIX "#"
|
|
884
|
|
885 #define REGISTER_NAMES \
|
|
886 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \
|
|
887 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \
|
|
888 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \
|
|
889 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \
|
|
890 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \
|
|
891 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \
|
|
892 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
|
|
893 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
|
|
894 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
|
|
895
|
|
896 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
|
|
897
|
|
898 /* Return a register name by index, handling %fp nicely.
|
|
899 We don't replace %fp for targets that don't map it to %a6
|
|
900 since it may confuse GAS. */
|
|
901 #define M68K_REGNAME(r) ( \
|
|
902 ((FRAME_POINTER_REGNUM == A6_REG) \
|
|
903 && ((r) == FRAME_POINTER_REGNUM) \
|
|
904 && frame_pointer_needed) ? \
|
|
905 M68K_FP_REG_NAME : reg_names[(r)])
|
|
906
|
|
907 /* On the Sun-3, the floating point registers have numbers
|
|
908 18 to 25, not 16 to 23 as they do in the compiler. */
|
|
909 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
|
|
910
|
|
911 /* Before the prologue, RA is at 0(%sp). */
|
|
912 #define INCOMING_RETURN_ADDR_RTX \
|
|
913 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
|
|
914
|
|
915 /* After the prologue, RA is at 4(AP) in the current frame. */
|
|
916 #define RETURN_ADDR_RTX(COUNT, FRAME) \
|
|
917 ((COUNT) == 0 \
|
|
918 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, UNITS_PER_WORD)) \
|
|
919 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
|
|
920
|
|
921 /* We must not use the DBX register numbers for the DWARF 2 CFA column
|
|
922 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
|
|
923 Instead use the identity mapping. */
|
|
924 #define DWARF_FRAME_REGNUM(REG) \
|
|
925 (INT_REGNO_P (REG) || FP_REGNO_P (REG) ? (REG) : INVALID_REGNUM)
|
|
926
|
|
927 /* The return column was originally 24, but gcc used 25 for a while too.
|
|
928 Define both registers 24 and 25 as Pmode ones and use 24 in our own
|
|
929 unwind information. */
|
|
930 #define DWARF_FRAME_REGISTERS 25
|
|
931 #define DWARF_FRAME_RETURN_COLUMN 24
|
|
932 #define DWARF_ALT_FRAME_RETURN_COLUMN 25
|
|
933
|
|
934 /* Before the prologue, the top of the frame is at 4(%sp). */
|
|
935 #define INCOMING_FRAME_SP_OFFSET 4
|
|
936
|
|
937 /* All registers are live on exit from an interrupt routine. */
|
|
938 #define EPILOGUE_USES(REGNO) \
|
|
939 (reload_completed \
|
|
940 && (m68k_get_function_kind (current_function_decl) \
|
|
941 == m68k_fk_interrupt_handler))
|
|
942
|
|
943 /* Describe how we implement __builtin_eh_return. */
|
|
944 #define EH_RETURN_DATA_REGNO(N) \
|
|
945 ((N) < 2 ? (N) : INVALID_REGNUM)
|
|
946 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, A0_REG)
|
|
947 #define EH_RETURN_HANDLER_RTX \
|
|
948 gen_rtx_MEM (Pmode, \
|
|
949 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
|
|
950 plus_constant (EH_RETURN_STACKADJ_RTX, \
|
|
951 UNITS_PER_WORD)))
|
|
952
|
|
953 /* Select a format to encode pointers in exception handling data. CODE
|
|
954 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
|
|
955 true if the symbol may be affected by dynamic relocations.
|
|
956
|
|
957 TARGET_ID_SHARED_LIBRARY and TARGET_SEP_DATA are designed to support
|
|
958 a read-only text segment without imposing a fixed gap between the
|
|
959 text and data segments. As a result, the text segment cannot refer
|
|
960 to anything in the data segment, even in PC-relative form. Because
|
|
961 .eh_frame refers to both code and data, it follows that .eh_frame
|
|
962 must be in the data segment itself, and that the offset between
|
|
963 .eh_frame and code will not be a link-time constant.
|
|
964
|
|
965 In theory, we could create a read-only .eh_frame by using DW_EH_PE_pcrel
|
|
966 | DW_EH_PE_indirect for all code references. However, gcc currently
|
|
967 handles indirect references using a per-TU constant pool. This means
|
|
968 that if a function and its eh_frame are removed by the linker, the
|
|
969 eh_frame's indirect references to the removed function will not be
|
|
970 removed, leading to an unresolved symbol error.
|
|
971
|
|
972 It isn't clear that any -msep-data or -mid-shared-library target
|
|
973 would benefit from a read-only .eh_frame anyway. In particular,
|
|
974 no known target that supports these options has a feature like
|
|
975 PT_GNU_RELRO. Without any such feature to motivate them, indirect
|
|
976 references would be unnecessary bloat, so we simply use an absolute
|
|
977 pointer for code and global references. We still use pc-relative
|
|
978 references to data, as this avoids a relocation. */
|
|
979 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
|
|
980 (flag_pic \
|
|
981 && !((TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) \
|
|
982 && ((GLOBAL) || (CODE))) \
|
|
983 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
|
|
984 : DW_EH_PE_absptr)
|
|
985
|
|
986 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
|
|
987 asm_fprintf (FILE, "%U%s", NAME)
|
|
988
|
|
989 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
|
|
990 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
|
|
991
|
|
992 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
|
|
993 asm_fprintf (FILE, (MOTOROLA \
|
|
994 ? "\tmove.l %s,-(%Rsp)\n" \
|
|
995 : "\tmovel %s,%Rsp@-\n"), \
|
|
996 reg_names[REGNO])
|
|
997
|
|
998 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
|
|
999 asm_fprintf (FILE, (MOTOROLA \
|
|
1000 ? "\tmove.l (%Rsp)+,%s\n" \
|
|
1001 : "\tmovel %Rsp@+,%s\n"), \
|
|
1002 reg_names[REGNO])
|
|
1003
|
|
1004 /* The m68k does not use absolute case-vectors, but we must define this macro
|
|
1005 anyway. */
|
|
1006 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
|
|
1007 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
|
|
1008
|
|
1009 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
|
|
1010 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
|
|
1011
|
|
1012 /* We don't have a way to align to more than a two-byte boundary, so do the
|
|
1013 best we can and don't complain. */
|
|
1014 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
|
|
1015 if ((LOG) >= 1) \
|
|
1016 fprintf (FILE, "\t.even\n");
|
|
1017
|
|
1018 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
|
|
1019 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
|
|
1020
|
|
1021 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
|
|
1022 ( fputs (".comm ", (FILE)), \
|
|
1023 assemble_name ((FILE), (NAME)), \
|
|
1024 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
|
|
1025
|
|
1026 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
|
|
1027 ( fputs (".lcomm ", (FILE)), \
|
|
1028 assemble_name ((FILE), (NAME)), \
|
|
1029 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
|
|
1030
|
|
1031 /* On the 68000, we use several CODE characters:
|
|
1032 '.' for dot needed in Motorola-style opcode names.
|
|
1033 '-' for an operand pushing on the stack:
|
|
1034 sp@-, -(sp) or -(%sp) depending on the style of syntax.
|
|
1035 '+' for an operand pushing on the stack:
|
|
1036 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
|
|
1037 '@' for a reference to the top word on the stack:
|
|
1038 sp@, (sp) or (%sp) depending on the style of syntax.
|
|
1039 '#' for an immediate operand prefix (# in MIT and Motorola syntax
|
|
1040 but & in SGS syntax).
|
|
1041 '!' for the fpcr register (used in some float-to-fixed conversions).
|
|
1042 '$' for the letter `s' in an op code, but only on the 68040.
|
|
1043 '&' for the letter `d' in an op code, but only on the 68040.
|
|
1044 '/' for register prefix needed by longlong.h.
|
|
1045 '?' for m68k_library_id_string
|
|
1046
|
|
1047 'b' for byte insn (no effect, on the Sun; this is for the ISI).
|
|
1048 'd' to force memory addressing to be absolute, not relative.
|
|
1049 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
|
|
1050 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
|
|
1051 or print pair of registers as rx:ry. */
|
|
1052
|
|
1053 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
|
|
1054 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
|
|
1055 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
|
|
1056 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/' || (CODE) == '?')
|
|
1057
|
|
1058
|
|
1059 /* See m68k.c for the m68k specific codes. */
|
|
1060 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
|
|
1061
|
|
1062 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
|
|
1063
|
|
1064 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
|
|
1065 do { \
|
|
1066 if (! m68k_output_addr_const_extra (FILE, (X))) \
|
|
1067 goto FAIL; \
|
|
1068 } while (0);
|
|
1069
|
|
1070 /* Values used in the MICROARCH argument to M68K_DEVICE. */
|
|
1071 enum uarch_type
|
|
1072 {
|
|
1073 u68000,
|
|
1074 u68010,
|
|
1075 u68020,
|
|
1076 u68020_40,
|
|
1077 u68020_60,
|
|
1078 u68030,
|
|
1079 u68040,
|
|
1080 u68060,
|
|
1081 ucpu32,
|
|
1082 ucfv1,
|
|
1083 ucfv2,
|
|
1084 ucfv3,
|
|
1085 ucfv4,
|
|
1086 ucfv4e,
|
|
1087 ucfv5,
|
|
1088 unk_arch
|
|
1089 };
|
|
1090
|
|
1091 /* An enumeration of all supported target devices. */
|
|
1092 enum target_device
|
|
1093 {
|
|
1094 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
|
|
1095 ENUM_VALUE,
|
|
1096 #include "m68k-devices.def"
|
|
1097 #undef M68K_DEVICE
|
|
1098 unk_device
|
|
1099 };
|
|
1100
|
|
1101 enum fpu_type
|
|
1102 {
|
|
1103 FPUTYPE_NONE,
|
|
1104 FPUTYPE_68881,
|
|
1105 FPUTYPE_COLDFIRE
|
|
1106 };
|
|
1107
|
|
1108 enum m68k_function_kind
|
|
1109 {
|
|
1110 m68k_fk_normal_function,
|
|
1111 m68k_fk_interrupt_handler,
|
|
1112 m68k_fk_interrupt_thread
|
|
1113 };
|
|
1114
|
|
1115 /* Variables in m68k.c; see there for details. */
|
|
1116 extern const char *m68k_library_id_string;
|
|
1117 extern int m68k_last_compare_had_fp_operands;
|
|
1118 extern enum target_device m68k_cpu;
|
|
1119 extern enum uarch_type m68k_tune;
|
|
1120 extern enum fpu_type m68k_fpu;
|
|
1121 extern unsigned int m68k_cpu_flags;
|
|
1122 extern unsigned int m68k_tune_flags;
|
|
1123 extern const char *m68k_symbolic_call;
|
|
1124 extern const char *m68k_symbolic_jump;
|
|
1125
|
|
1126 enum M68K_SYMBOLIC_CALL { M68K_SYMBOLIC_CALL_NONE, M68K_SYMBOLIC_CALL_JSR,
|
|
1127 M68K_SYMBOLIC_CALL_BSR_C, M68K_SYMBOLIC_CALL_BSR_P };
|
|
1128
|
|
1129 extern enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var;
|
|
1130
|
|
1131 /* ??? HOST_WIDE_INT is not being defined for auto-generated files.
|
|
1132 Workaround that. */
|
|
1133 #ifdef HOST_WIDE_INT
|
|
1134 typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ }
|
|
1135 M68K_CONST_METHOD;
|
|
1136
|
|
1137 extern M68K_CONST_METHOD m68k_const_method (HOST_WIDE_INT);
|
|
1138 #endif
|
|
1139
|
|
1140 extern void m68k_emit_move_double (rtx [2]);
|
|
1141
|
|
1142 extern int m68k_sched_address_bypass_p (rtx, rtx);
|
|
1143 extern int m68k_sched_indexed_address_bypass_p (rtx, rtx);
|
|
1144
|
|
1145 #define CPU_UNITS_QUERY 1
|