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1 ;;
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2 ;; Pipeline description for the VR4130 family.
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3 ;;
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4 ;; The processor issues each 8-byte aligned pair of instructions together,
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5 ;; stalling the second instruction if it depends on the first. Thus, if we
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6 ;; want two instructions to issue in parallel, we need to make sure that the
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7 ;; first one is 8-byte aligned.
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8 ;;
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9 ;; For the purposes of this pipeline description, we treat the processor
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10 ;; like a standard two-way superscalar architecture. If scheduling were
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11 ;; the last pass to run, we could use the scheduler hooks to vary the
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12 ;; issue rate depending on whether an instruction is at an aligned or
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13 ;; unaligned address. Unfortunately, delayed branch scheduling and
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14 ;; hazard avoidance are done after the final scheduling pass, and they
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15 ;; can change the addresses of many instructions.
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16 ;;
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17 ;; We get around this in two ways:
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18 ;;
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19 ;; (1) By running an extra pass at the end of compilation. This pass goes
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20 ;; through the function looking for pairs of instructions that could
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21 ;; execute in parallel. It makes sure that the first instruction in
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22 ;; each pair is suitably aligned, inserting nops if necessary. Doing
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23 ;; this gives the same kind of pipeline behavior we would see on a
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24 ;; normal superscalar target.
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25 ;;
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26 ;; This pass is generally a speed improvement, but the extra nops will
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27 ;; obviously make the program bigger. It is therefore unsuitable for
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28 ;; -Os (at the very least).
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29 ;;
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30 ;; (2) By modifying the scheduler hooks so that, where possible:
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31 ;;
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32 ;; (a) dependent instructions are separated by a non-dependent
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33 ;; instruction;
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34 ;;
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35 ;; (b) instructions that use the multiplication unit are separated
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36 ;; by non-multiplication instructions; and
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37 ;;
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38 ;; (c) memory access instructions are separated by non-memory
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39 ;; instructions.
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40 ;;
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41 ;; The idea is to keep conflicting instructions apart wherever possible
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42 ;; and thus make the schedule less dependent on alignment.
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43
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44 (define_automaton "vr4130_main, vr4130_muldiv, vr4130_mulpre")
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45
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46 (define_cpu_unit "vr4130_alu1, vr4130_alu2, vr4130_dcache" "vr4130_main")
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47 (define_cpu_unit "vr4130_muldiv" "vr4130_muldiv")
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48
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49 ;; This is a fake unit for pre-reload scheduling of multiplications.
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50 ;; It enforces the true post-reload repeat rate.
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51 (define_cpu_unit "vr4130_mulpre" "vr4130_mulpre")
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52
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53 ;; The scheduling hooks use this attribute for (b) above.
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54 (define_attr "vr4130_class" "mul,mem,alu"
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55 (cond [(eq_attr "type" "load,store")
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56 (const_string "mem")
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57
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58 (eq_attr "type" "mfhilo,mthilo,imul,imul3,imadd,idiv")
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59 (const_string "mul")]
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60 (const_string "alu")))
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61
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62 (define_insn_reservation "vr4130_multi" 1
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63 (and (eq_attr "cpu" "r4130")
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64 (eq_attr "type" "multi,unknown"))
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65 "vr4130_alu1 + vr4130_alu2 + vr4130_dcache + vr4130_muldiv")
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66
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67 (define_insn_reservation "vr4130_int" 1
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68 (and (eq_attr "cpu" "r4130")
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69 (eq_attr "type" "arith,const,logical,move,nop,shift,signext,slt"))
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70 "vr4130_alu1 | vr4130_alu2")
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71
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72 (define_insn_reservation "vr4130_load" 3
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73 (and (eq_attr "cpu" "r4130")
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74 (eq_attr "type" "load"))
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75 "vr4130_dcache")
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76
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77 (define_insn_reservation "vr4130_store" 1
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78 (and (eq_attr "cpu" "r4130")
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79 (eq_attr "type" "store"))
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80 "vr4130_dcache")
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81
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82 (define_insn_reservation "vr4130_mfhilo" 3
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83 (and (eq_attr "cpu" "r4130")
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84 (eq_attr "type" "mfhilo"))
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85 "vr4130_muldiv")
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86
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87 (define_insn_reservation "vr4130_mthilo" 1
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88 (and (eq_attr "cpu" "r4130")
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89 (eq_attr "type" "mthilo"))
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90 "vr4130_muldiv")
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91
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92 ;; The product is available in LO & HI after one cycle. Moving the result
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93 ;; into an integer register will take an additional three cycles, see mflo
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94 ;; & mfhi above. Note that the same latencies and repeat rates apply if we
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95 ;; use "mtlo; macc" instead of "mult; mflo".
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96 (define_insn_reservation "vr4130_mulsi" 4
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97 (and (eq_attr "cpu" "r4130")
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98 (and (eq_attr "type" "imul,imul3")
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99 (eq_attr "mode" "SI")))
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100 "vr4130_muldiv + (vr4130_mulpre * 2)")
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101
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102 ;; As for vr4130_mulsi, but the product is available in LO and HI
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103 ;; after 3 cycles.
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104 (define_insn_reservation "vr4130_muldi" 6
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105 (and (eq_attr "cpu" "r4130")
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106 (and (eq_attr "type" "imul,imul3")
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107 (eq_attr "mode" "DI")))
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108 "(vr4130_muldiv * 3) + (vr4130_mulpre * 4)")
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109
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110 ;; maccs can execute in consecutive cycles without stalling, but it
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111 ;; is 3 cycles before the integer destination can be read.
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112 (define_insn_reservation "vr4130_macc" 3
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113 (and (eq_attr "cpu" "r4130")
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114 (eq_attr "type" "imadd"))
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115 "vr4130_muldiv")
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116
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117 (define_bypass 1 "vr4130_mulsi,vr4130_macc" "vr4130_macc" "mips_linked_madd_p")
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118 (define_bypass 1 "vr4130_mulsi,vr4130_macc" "vr4130_mfhilo")
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119 (define_bypass 3 "vr4130_muldi" "vr4130_mfhilo")
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120
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121 (define_insn_reservation "vr4130_divsi" 36
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122 (and (eq_attr "cpu" "r4130")
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123 (and (eq_attr "type" "idiv")
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124 (eq_attr "mode" "SI")))
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125 "vr4130_muldiv * 36")
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126
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127 (define_insn_reservation "vr4130_divdi" 72
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128 (and (eq_attr "cpu" "r4130")
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129 (and (eq_attr "type" "idiv")
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130 (eq_attr "mode" "DI")))
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131 "vr4130_muldiv * 72")
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132
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133 (define_insn_reservation "vr4130_branch" 0
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134 (and (eq_attr "cpu" "r4130")
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135 (eq_attr "type" "branch,jump,call"))
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136 "vr4130_alu1 | vr4130_alu2")
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