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1 ;; Pipeline model for ST Microelectronics Loongson-2E/2F cores.
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3 ;; Copyright (C) 2008 Free Software Foundation, Inc.
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4 ;; Contributed by CodeSourcery.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; Automaton for integer instructions.
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21 (define_automaton "ls2_alu")
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22
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23 ;; ALU1 and ALU2.
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24 ;; We need to query these units to adjust round-robin counter.
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25 (define_query_cpu_unit "ls2_alu1_core,ls2_alu2_core" "ls2_alu")
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26
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27 ;; Pseudo units to help modeling of ALU1/2 round-robin dispatch strategy.
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28 (define_cpu_unit "ls2_alu1_turn,ls2_alu2_turn" "ls2_alu")
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29
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30 ;; Pseudo units to enable/disable ls2_alu[12]_turn units.
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31 ;; ls2_alu[12]_turn unit can be subscribed only after ls2_alu[12]_turn_enabled
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32 ;; unit is subscribed.
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33 (define_cpu_unit "ls2_alu1_turn_enabled,ls2_alu2_turn_enabled" "ls2_alu")
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34 (presence_set "ls2_alu1_turn" "ls2_alu1_turn_enabled")
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35 (presence_set "ls2_alu2_turn" "ls2_alu2_turn_enabled")
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36
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37 ;; Reservations for ALU1 (ALU2) instructions.
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38 ;; Instruction goes to ALU1 (ALU2) and makes next ALU1/2 instruction to
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39 ;; be dispatched to ALU2 (ALU1).
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40 (define_reservation "ls2_alu1"
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41 "(ls2_alu1_core+ls2_alu2_turn_enabled)|ls2_alu1_core")
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42 (define_reservation "ls2_alu2"
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43 "(ls2_alu2_core+ls2_alu1_turn_enabled)|ls2_alu2_core")
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44
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45 ;; Reservation for ALU1/2 instructions.
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46 ;; Instruction will go to ALU1 iff ls2_alu1_turn_enabled is subscribed and
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47 ;; switch the turn to ALU2 by subscribing ls2_alu2_turn_enabled.
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48 ;; Or to ALU2 otherwise.
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49 (define_reservation "ls2_alu"
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50 "(ls2_alu1_core+ls2_alu1_turn+ls2_alu2_turn_enabled)
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51 |(ls2_alu1_core+ls2_alu1_turn)
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52 |(ls2_alu2_core+ls2_alu2_turn+ls2_alu1_turn_enabled)
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53 |(ls2_alu2_core+ls2_alu2_turn)")
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54
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55 ;; Automaton for floating-point instructions.
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56 (define_automaton "ls2_falu")
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57
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58 ;; FALU1 and FALU2.
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59 ;; We need to query these units to adjust round-robin counter.
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60 (define_query_cpu_unit "ls2_falu1_core,ls2_falu2_core" "ls2_falu")
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61
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62 ;; Pseudo units to help modeling of FALU1/2 round-robin dispatch strategy.
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63 (define_cpu_unit "ls2_falu1_turn,ls2_falu2_turn" "ls2_falu")
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64
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65 ;; Pseudo units to enable/disable ls2_falu[12]_turn units.
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66 ;; ls2_falu[12]_turn unit can be subscribed only after
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67 ;; ls2_falu[12]_turn_enabled unit is subscribed.
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68 (define_cpu_unit "ls2_falu1_turn_enabled,ls2_falu2_turn_enabled" "ls2_falu")
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69 (presence_set "ls2_falu1_turn" "ls2_falu1_turn_enabled")
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70 (presence_set "ls2_falu2_turn" "ls2_falu2_turn_enabled")
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71
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72 ;; Reservations for FALU1 (FALU2) instructions.
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73 ;; Instruction goes to FALU1 (FALU2) and makes next FALU1/2 instruction to
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74 ;; be dispatched to FALU2 (FALU1).
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75 (define_reservation "ls2_falu1"
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76 "(ls2_falu1_core+ls2_falu2_turn_enabled)|ls2_falu1_core")
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77 (define_reservation "ls2_falu2"
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78 "(ls2_falu2_core+ls2_falu1_turn_enabled)|ls2_falu2_core")
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79
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80 ;; Reservation for FALU1/2 instructions.
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81 ;; Instruction will go to FALU1 iff ls2_falu1_turn_enabled is subscribed and
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82 ;; switch the turn to FALU2 by subscribing ls2_falu2_turn_enabled.
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83 ;; Or to FALU2 otherwise.
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84 (define_reservation "ls2_falu"
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85 "(ls2_falu1+ls2_falu1_turn+ls2_falu2_turn_enabled)
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86 |(ls2_falu1+ls2_falu1_turn)
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87 |(ls2_falu2+ls2_falu2_turn+ls2_falu1_turn_enabled)
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88 |(ls2_falu2+ls2_falu2_turn)")
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89
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90 ;; The following 4 instructions each subscribe one of
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91 ;; ls2_[f]alu{1,2}_turn_enabled units according to this attribute.
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92 ;; These instructions are used in mips.c: sched_ls2_dfa_post_advance_cycle.
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93
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94 (define_attr "ls2_turn_type" "alu1,alu2,falu1,falu2,unknown"
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95 (const_string "unknown"))
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96
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97 ;; Subscribe ls2_alu1_turn_enabled.
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98 (define_insn "ls2_alu1_turn_enabled_insn"
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99 [(unspec [(const_int 0)] UNSPEC_LOONGSON_ALU1_TURN_ENABLED_INSN)]
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100 "TUNE_LOONGSON_2EF"
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101 { gcc_unreachable (); }
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102 [(set_attr "ls2_turn_type" "alu1")])
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103
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104 (define_insn_reservation "ls2_alu1_turn_enabled" 0
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105 (eq_attr "ls2_turn_type" "alu1")
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106 "ls2_alu1_turn_enabled")
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107
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108 ;; Subscribe ls2_alu2_turn_enabled.
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109 (define_insn "ls2_alu2_turn_enabled_insn"
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110 [(unspec [(const_int 0)] UNSPEC_LOONGSON_ALU2_TURN_ENABLED_INSN)]
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111 "TUNE_LOONGSON_2EF"
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112 { gcc_unreachable (); }
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113 [(set_attr "ls2_turn_type" "alu2")])
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114
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115 (define_insn_reservation "ls2_alu2_turn_enabled" 0
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116 (eq_attr "ls2_turn_type" "alu2")
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117 "ls2_alu2_turn_enabled")
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118
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119 ;; Subscribe ls2_falu1_turn_enabled.
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120 (define_insn "ls2_falu1_turn_enabled_insn"
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121 [(unspec [(const_int 0)] UNSPEC_LOONGSON_FALU1_TURN_ENABLED_INSN)]
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122 "TUNE_LOONGSON_2EF"
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123 { gcc_unreachable (); }
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124 [(set_attr "ls2_turn_type" "falu1")])
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125
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126 (define_insn_reservation "ls2_falu1_turn_enabled" 0
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127 (eq_attr "ls2_turn_type" "falu1")
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128 "ls2_falu1_turn_enabled")
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129
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130 ;; Subscribe ls2_falu2_turn_enabled.
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131 (define_insn "ls2_falu2_turn_enabled_insn"
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132 [(unspec [(const_int 0)] UNSPEC_LOONGSON_FALU2_TURN_ENABLED_INSN)]
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133 "TUNE_LOONGSON_2EF"
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134 { gcc_unreachable (); }
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135 [(set_attr "ls2_turn_type" "falu2")])
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136
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137 (define_insn_reservation "ls2_falu2_turn_enabled" 0
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138 (eq_attr "ls2_turn_type" "falu2")
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139 "ls2_falu2_turn_enabled")
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140
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141 ;; Automaton for memory operations.
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142 (define_automaton "ls2_mem")
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143
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144 ;; Memory unit.
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145 (define_query_cpu_unit "ls2_mem" "ls2_mem")
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146
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147 ;; Reservation for integer instructions.
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148 (define_insn_reservation "ls2_alu" 2
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149 (and (eq_attr "cpu" "loongson_2e,loongson_2f")
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150 (eq_attr "type" "arith,condmove,const,logical,mfhilo,move,
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151 mthilo,nop,shift,signext,slt"))
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152 "ls2_alu")
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153
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154 ;; Reservation for branch instructions.
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155 (define_insn_reservation "ls2_branch" 2
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156 (and (eq_attr "cpu" "loongson_2e,loongson_2f")
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157 (eq_attr "type" "branch,jump,call,trap"))
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158 "ls2_alu1")
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159
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160 ;; Reservation for integer multiplication instructions.
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161 (define_insn_reservation "ls2_imult" 5
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162 (and (eq_attr "cpu" "loongson_2e,loongson_2f")
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163 (eq_attr "type" "imul,imul3nc"))
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164 "ls2_alu2,ls2_alu2_core")
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165
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166 ;; Reservation for integer division / remainder instructions.
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167 ;; These instructions use the SRT algorithm and hence take 2-38 cycles.
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168 (define_insn_reservation "ls2_idiv" 20
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169 (and (eq_attr "cpu" "loongson_2e,loongson_2f")
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170 (eq_attr "type" "idiv,idiv3"))
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171 "ls2_alu2,ls2_alu2_core*18")
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172
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173 ;; Reservation for memory load instructions.
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174 (define_insn_reservation "ls2_load" 5
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175 (and (eq_attr "cpu" "loongson_2e,loongson_2f")
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176 (eq_attr "type" "load,fpload,mfc,mtc"))
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177 "ls2_mem")
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178
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179 (define_insn_reservation "ls2_prefetch" 0
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180 (and (eq_attr "cpu" "loongson_2e,loongson_2f")
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181 (eq_attr "type" "prefetch,prefetchx"))
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182 "ls2_mem")
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183
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184 ;; Reservation for memory store instructions.
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185 ;; With stores we assume they don't alias with dependent loads.
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186 ;; Therefore we set the latency to zero.
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187 (define_insn_reservation "ls2_store" 0
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188 (and (eq_attr "cpu" "loongson_2e,loongson_2f")
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189 (eq_attr "type" "store,fpstore"))
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190 "ls2_mem")
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191
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192 ;; Reservation for floating-point instructions of latency 3.
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193 (define_insn_reservation "ls2_fp3" 3
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194 (and (eq_attr "cpu" "loongson_2e,loongson_2f")
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195 (eq_attr "type" "fabs,fneg,fcmp,fmove"))
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196 "ls2_falu1")
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197
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198 ;; Reservation for floating-point instructions of latency 5.
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199 (define_insn_reservation "ls2_fp5" 5
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200 (and (eq_attr "cpu" "loongson_2e,loongson_2f")
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201 (eq_attr "type" "fcvt"))
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202 "ls2_falu1")
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203
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204 ;; Reservation for floating-point instructions that can go
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205 ;; to either of FALU1/2 units.
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206 (define_insn_reservation "ls2_falu" 7
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207 (and (eq_attr "cpu" "loongson_2e,loongson_2f")
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208 (eq_attr "type" "fadd,fmul,fmadd"))
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209 "ls2_falu")
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210
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211 ;; Reservation for floating-point division / remainder instructions.
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212 ;; These instructions use the SRT algorithm and hence take a variable amount
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213 ;; of cycles:
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214 ;; div.s takes 5-11 cycles
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215 ;; div.d takes 5-18 cycles
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216 (define_insn_reservation "ls2_fdiv" 9
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217 (and (eq_attr "cpu" "loongson_2e,loongson_2f")
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218 (eq_attr "type" "fdiv"))
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219 "ls2_falu2,ls2_falu2_core*7")
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220
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221 ;; Reservation for floating-point sqrt instructions.
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222 ;; These instructions use the SRT algorithm and hence take a variable amount
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223 ;; of cycles:
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224 ;; sqrt.s takes 5-17 cycles
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225 ;; sqrt.d takes 5-32 cycles
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226 (define_insn_reservation "ls2_fsqrt" 15
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227 (and (eq_attr "cpu" "loongson_2e,loongson_2f")
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228 (eq_attr "type" "fsqrt"))
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229 "ls2_falu2,ls2_falu2_core*13")
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230
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231 ;; Two consecutive ALU instructions.
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232 (define_insn_reservation "ls2_multi" 4
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233 (and (eq_attr "cpu" "loongson_2e,loongson_2f")
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234 (eq_attr "type" "multi"))
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235 "(ls2_alu1,ls2_alu2_core)|(ls2_alu2,ls2_alu1_core)")
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236
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237 ;; Reservation for everything else. Normally, this reservation
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238 ;; will only be used to handle cases like compiling for non-loongson
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239 ;; CPUs with -mtune=loongson2?.
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240 ;;
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241 ;; This reservation depends upon the fact that DFA will check
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242 ;; reservations in the same order as they appear in the file.
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243 (define_insn_reservation "ls2_unknown" 1
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244 (eq_attr "cpu" "loongson_2e,loongson_2f")
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245 "ls2_alu1_core+ls2_alu2_core+ls2_falu1_core+ls2_falu2_core+ls2_mem")
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