Mercurial > hg > CbC > CbC_gcc

annotate gcc/config/mips/mips-fixed.md @ 0:a06113de4d67

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first commit
author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
parents
children 77e2b8dfacca
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1 ;; This file contains MIPS instructions that support fixed-point operations.
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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2
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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3 ;; All supported fixed-point modes
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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4 (define_mode_iterator FIXED [(QQ "") (HQ "") (SQ "") (DQ "TARGET_64BIT")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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5 (UQQ "") (UHQ "") (USQ "") (UDQ "TARGET_64BIT")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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6 (HA "") (SA "") (DA "TARGET_64BIT")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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7 (UHA "") (USA "") (UDA "TARGET_64BIT")])
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8
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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9 ;; For signed add/sub with saturation
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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10 (define_mode_iterator ADDSUB [(HQ "") (SQ "") (HA "") (SA "") (V2HQ "")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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11 (V2HA "")])
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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12 (define_mode_attr addsubfmt [(HQ "ph") (SQ "w") (HA "ph") (SA "w")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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13 (V2HQ "ph") (V2HA "ph")])
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14
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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15 ;; For unsigned add/sub with saturation
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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16 (define_mode_iterator UADDSUB [(UQQ "ISA_HAS_DSP") (UHQ "ISA_HAS_DSPR2")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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17 (UHA "ISA_HAS_DSPR2") (V4UQQ "ISA_HAS_DSP")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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18 (V2UHQ "ISA_HAS_DSPR2") (V2UHA "ISA_HAS_DSPR2")])
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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19 (define_mode_attr uaddsubfmt [(UQQ "qb") (UHQ "ph") (UHA "ph")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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20 (V4UQQ "qb") (V2UHQ "ph") (V2UHA "ph")])
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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21
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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22 ;; For signed multiplication with saturation
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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23 (define_mode_iterator MULQ [(V2HQ "ISA_HAS_DSP") (HQ "ISA_HAS_DSP")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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24 (SQ "ISA_HAS_DSPR2")])
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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25 (define_mode_attr mulqfmt [(V2HQ "ph") (HQ "ph") (SQ "w")])
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26
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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27 (define_insn "add<mode>3"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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28 [(set (match_operand:FIXED 0 "register_operand" "=d")
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29 (plus:FIXED (match_operand:FIXED 1 "register_operand" "d")
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30 (match_operand:FIXED 2 "register_operand" "d")))]
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31 ""
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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32 "<d>addu\t%0,%1,%2"
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33 [(set_attr "type" "arith")
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34 (set_attr "mode" "<IMODE>")])
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35
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36 (define_insn "usadd<mode>3"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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37 [(parallel
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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38 [(set (match_operand:UADDSUB 0 "register_operand" "=d")
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39 (us_plus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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40 (match_operand:UADDSUB 2 "register_operand" "d")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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41 (set (reg:CCDSP CCDSP_OU_REGNUM)
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42 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
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43 ""
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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44 "addu_s.<uaddsubfmt>\t%0,%1,%2"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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45 [(set_attr "type" "arith")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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46 (set_attr "mode" "<IMODE>")])
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47
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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48 (define_insn "ssadd<mode>3"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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49 [(parallel
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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50 [(set (match_operand:ADDSUB 0 "register_operand" "=d")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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51 (ss_plus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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52 (match_operand:ADDSUB 2 "register_operand" "d")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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53 (set (reg:CCDSP CCDSP_OU_REGNUM)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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54 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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55 "ISA_HAS_DSP"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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56 "addq_s.<addsubfmt>\t%0,%1,%2"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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57 [(set_attr "type" "arith")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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58 (set_attr "mode" "<IMODE>")])
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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59
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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60 (define_insn "sub<mode>3"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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61 [(set (match_operand:FIXED 0 "register_operand" "=d")
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62 (minus:FIXED (match_operand:FIXED 1 "register_operand" "d")
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63 (match_operand:FIXED 2 "register_operand" "d")))]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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64 ""
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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65 "<d>subu\t%0,%1,%2"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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66 [(set_attr "type" "arith")
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67 (set_attr "mode" "<IMODE>")])
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68
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69 (define_insn "ussub<mode>3"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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70 [(parallel
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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71 [(set (match_operand:UADDSUB 0 "register_operand" "=d")
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72 (us_minus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d")
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73 (match_operand:UADDSUB 2 "register_operand" "d")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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74 (set (reg:CCDSP CCDSP_OU_REGNUM)
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75 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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76 ""
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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77 "subu_s.<uaddsubfmt>\t%0,%1,%2"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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78 [(set_attr "type" "arith")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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79 (set_attr "mode" "<IMODE>")])
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80
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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81 (define_insn "sssub<mode>3"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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82 [(parallel
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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83 [(set (match_operand:ADDSUB 0 "register_operand" "=d")
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84 (ss_minus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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85 (match_operand:ADDSUB 2 "register_operand" "d")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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86 (set (reg:CCDSP CCDSP_OU_REGNUM)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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87 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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88 "ISA_HAS_DSP"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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89 "subq_s.<addsubfmt>\t%0,%1,%2"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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90 [(set_attr "type" "arith")
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91 (set_attr "mode" "<IMODE>")])
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92
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93 (define_insn "ssmul<mode>3"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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94 [(parallel
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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95 [(set (match_operand:MULQ 0 "register_operand" "=d")
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96 (ss_mult:MULQ (match_operand:MULQ 1 "register_operand" "d")
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97 (match_operand:MULQ 2 "register_operand" "d")))
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98 (set (reg:CCDSP CCDSP_OU_REGNUM)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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99 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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100 (clobber (match_scratch:DI 3 "=x"))])]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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101 ""
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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102 "mulq_rs.<mulqfmt>\t%0,%1,%2"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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103 [(set_attr "type" "imul3")
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104 (set_attr "mode" "<IMODE>")])
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105
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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106 (define_insn "ssmaddsqdq4"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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107 [(parallel
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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108 [(set (match_operand:DQ 0 "register_operand" "=a")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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109 (ss_plus:DQ
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110 (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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111 "register_operand" "d"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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112 (sat_fract:DQ (match_operand:SQ 2
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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113 "register_operand" "d")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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114 (match_operand:DQ 3 "register_operand" "0")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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115 (set (reg:CCDSP CCDSP_OU_REGNUM)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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116 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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117 UNSPEC_DPAQ_SA_L_W))])]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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118 "ISA_HAS_DSP && !TARGET_64BIT"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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119 "dpaq_sa.l.w\t%q0,%1,%2"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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120 [(set_attr "type" "imadd")
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121 (set_attr "mode" "SI")])
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122
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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123 (define_insn "ssmsubsqdq4"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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124 [(parallel
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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125 [(set (match_operand:DQ 0 "register_operand" "=a")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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126 (ss_minus:DQ
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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127 (match_operand:DQ 3 "register_operand" "0")
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128 (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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129 "register_operand" "d"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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130 (sat_fract:DQ (match_operand:SQ 2
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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131 "register_operand" "d")))))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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132 (set (reg:CCDSP CCDSP_OU_REGNUM)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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133 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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134 UNSPEC_DPSQ_SA_L_W))])]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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135 "ISA_HAS_DSP && !TARGET_64BIT"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
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136 "dpsq_sa.l.w\t%q0,%1,%2"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
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137 [(set_attr "type" "imadd")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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138 (set_attr "mode" "SI")])