0
|
1 ;; DFA-based pipeline description for the XLR.
|
|
2 ;; Copyright (C) 2008 Free Software Foundation, Inc.
|
|
3 ;;
|
|
4 ;; xlr.md Machine Description for the RMI XLR Microprocessor
|
|
5 ;; This file is part of GCC.
|
|
6
|
|
7 ;; GCC is free software; you can redistribute it and/or modify it
|
|
8 ;; under the terms of the GNU General Public License as published
|
|
9 ;; by the Free Software Foundation; either version 3, or (at your
|
|
10 ;; option) any later version.
|
|
11
|
|
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
|
|
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
|
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
|
15 ;; License for more details.
|
|
16
|
|
17 ;; You should have received a copy of the GNU General Public License
|
|
18 ;; along with GCC; see the file COPYING3. If not see
|
|
19 ;; <http://www.gnu.org/licenses/>.
|
|
20
|
|
21 (define_automaton "xlr_main,xlr_muldiv")
|
|
22
|
|
23 ;; Definitions for xlr_main automaton.
|
|
24 (define_cpu_unit "xlr_main_pipe" "xlr_main")
|
|
25
|
|
26 (define_insn_reservation "ir_xlr_alu_slt" 2
|
|
27 (and (eq_attr "cpu" "xlr")
|
|
28 (eq_attr "type" "slt"))
|
|
29 "xlr_main_pipe")
|
|
30
|
|
31 ;; Integer arithmetic instructions.
|
|
32 (define_insn_reservation "ir_xlr_alu" 1
|
|
33 (and (eq_attr "cpu" "xlr")
|
|
34 (eq_attr "type" "arith,shift,clz,const,unknown,multi,nop,trap"))
|
|
35 "xlr_main_pipe")
|
|
36
|
|
37 ;; Integer arithmetic instructions.
|
|
38 (define_insn_reservation "ir_xlr_condmove" 2
|
|
39 (and (eq_attr "cpu" "xlr")
|
|
40 (eq_attr "type" "condmove"))
|
|
41 "xlr_main_pipe")
|
|
42
|
|
43 ;; Load/store instructions.
|
|
44 (define_insn_reservation "ir_xlr_load" 4
|
|
45 (and (eq_attr "cpu" "xlr")
|
|
46 (eq_attr "type" "load"))
|
|
47 "xlr_main_pipe")
|
|
48
|
|
49 (define_insn_reservation "ir_xlr_store" 1
|
|
50 (and (eq_attr "cpu" "xlr")
|
|
51 (eq_attr "type" "store"))
|
|
52 "xlr_main_pipe")
|
|
53
|
|
54 (define_insn_reservation "ir_xlr_prefetch_x" 1
|
|
55 (and (eq_attr "cpu" "xlr")
|
|
56 (eq_attr "type" "prefetch,prefetchx"))
|
|
57 "xlr_main_pipe")
|
|
58
|
|
59 ;; Branch instructions - use branch misprediction latency.
|
|
60 (define_insn_reservation "ir_xlr_branch" 1
|
|
61 (and (eq_attr "cpu" "xlr")
|
|
62 (eq_attr "type" "branch,jump,call"))
|
|
63 "xlr_main_pipe")
|
|
64
|
|
65 ;; Coprocessor move instructions.
|
|
66 (define_insn_reservation "ir_xlr_xfer" 2
|
|
67 (and (eq_attr "cpu" "xlr")
|
|
68 (eq_attr "type" "mtc,mfc"))
|
|
69 "xlr_main_pipe")
|
|
70
|
|
71 (define_bypass 5 "ir_xlr_xfer" "ir_xlr_xfer")
|
|
72
|
|
73 ;; Definitions for the xlr_muldiv automaton.
|
|
74 (define_cpu_unit "xlr_imuldiv_nopipe" "xlr_muldiv")
|
|
75
|
|
76 (define_insn_reservation "ir_xlr_imul" 8
|
|
77 (and (eq_attr "cpu" "xlr")
|
|
78 (eq_attr "type" "imul,imul3,imadd"))
|
|
79 "xlr_main_pipe,xlr_imuldiv_nopipe*6")
|
|
80
|
|
81 (define_insn_reservation "ir_xlr_div" 68
|
|
82 (and (eq_attr "cpu" "xlr")
|
|
83 (eq_attr "type" "idiv"))
|
|
84 "xlr_main_pipe,xlr_imuldiv_nopipe*67")
|
|
85
|
|
86 (define_insn_reservation "xlr_hilo" 2
|
|
87 (and (eq_attr "cpu" "xlr")
|
|
88 (eq_attr "type" "mfhilo,mthilo"))
|
|
89 "xlr_imuldiv_nopipe")
|