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1 /* Configuration for GCC-compiler for PA-RISC.
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2 Copyright (C) 1999, 2000, 2003, 2004, 2007, 2008
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3 Free Software Foundation, Inc.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify
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8 it under the terms of the GNU General Public License as published by
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9 the Free Software Foundation; either version 3, or (at your option)
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10 any later version.
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11
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12 GCC is distributed in the hope that it will be useful,
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13 but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 GNU General Public License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21 /* Standard register usage.
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22
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23 It is safe to refer to actual register numbers in this file. */
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24
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25 /* Number of actual hardware registers.
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26 The hardware registers are assigned numbers for the compiler
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27 from 0 to just below FIRST_PSEUDO_REGISTER.
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28 All registers that the compiler knows about must be given numbers,
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29 even those that are not normally considered general registers.
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30
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31 HP-PA 2.0w has 32 fullword registers and 32 floating point
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32 registers. However, the floating point registers behave
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33 differently: the left and right halves of registers are addressable
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34 as 32-bit registers.
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35
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36 Due to limitations within GCC itself, we do not expose the left/right
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37 half addressability when in wide mode. This is not a major performance
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38 issue as using the halves independently triggers false dependency stalls
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39 anyway. */
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40
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41 #define FIRST_PSEUDO_REGISTER 61 /* 32 general regs + 28 fp regs +
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42 + 1 shift reg */
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43
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44 /* 1 for registers that have pervasive standard uses
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45 and are not available for the register allocator.
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46
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47 On the HP-PA, these are:
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48 Reg 0 = 0 (hardware). However, 0 is used for condition code,
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49 so is not fixed.
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50 Reg 1 = ADDIL target/Temporary (hardware).
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51 Reg 2 = Return Pointer
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52 Reg 3 = Frame Pointer
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53 Reg 4 = Frame Pointer (>8k varying frame with HP compilers only)
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54 Reg 4-18 = Preserved Registers
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55 Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme.
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56 Reg 20-22 = Temporary Registers
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57 Reg 23-26 = Temporary/Parameter Registers
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58 Reg 27 = Global Data Pointer (hp)
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59 Reg 28 = Temporary/Return Value register
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60 Reg 29 = Temporary/Static Chain/Return Value register #2
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61 Reg 30 = stack pointer
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62 Reg 31 = Temporary/Millicode Return Pointer (hp)
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63
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64 Freg 0-3 = Status Registers -- Not known to the compiler.
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65 Freg 4-7 = Arguments/Return Value
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66 Freg 8-11 = Temporary Registers
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67 Freg 12-21 = Preserved Registers
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68 Freg 22-31 = Temporary Registers
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69
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70 */
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71
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72 #define FIXED_REGISTERS \
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73 {0, 0, 0, 0, 0, 0, 0, 0, \
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74 0, 0, 0, 0, 0, 0, 0, 0, \
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75 0, 0, 0, 0, 0, 0, 0, 0, \
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76 0, 0, 0, 1, 0, 0, 1, 0, \
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77 /* fp registers */ \
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78 0, 0, 0, 0, 0, 0, 0, 0, \
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79 0, 0, 0, 0, 0, 0, 0, 0, \
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80 0, 0, 0, 0, 0, 0, 0, 0, \
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81 0, 0, 0, 0, \
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82 /* shift register */ \
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83 0}
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84
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85 /* 1 for registers not available across function calls.
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86 These must include the FIXED_REGISTERS and also any
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87 registers that can be used without being saved.
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88 The latter must include the registers where values are returned
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89 and the register where structure-value addresses are passed.
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90 Aside from that, you can include as many other registers as you like. */
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91 #define CALL_USED_REGISTERS \
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92 {1, 1, 1, 0, 0, 0, 0, 0, \
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93 0, 0, 0, 0, 0, 0, 0, 0, \
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94 0, 0, 0, 1, 1, 1, 1, 1, \
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95 1, 1, 1, 1, 1, 1, 1, 1, \
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96 /* fp registers */ \
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97 1, 1, 1, 1, 1, 1, 1, 1, \
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98 0, 0, 0, 0, 0, 0, 0, 0, \
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99 0, 0, 1, 1, 1, 1, 1, 1, \
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100 1, 1, 1, 1, \
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101 /* shift register */ \
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102 1}
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103
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104 #define CONDITIONAL_REGISTER_USAGE \
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105 { \
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106 int i; \
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107 if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
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108 { \
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109 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)\
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110 fixed_regs[i] = call_used_regs[i] = 1; \
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111 } \
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112 if (flag_pic) \
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113 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
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114 }
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115
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116 /* Allocate the call used registers first. This should minimize
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117 the number of registers that need to be saved (as call used
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118 registers will generally not be allocated across a call).
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119
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120 Experimentation has shown slightly better results by allocating
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121 FP registers first. We allocate the caller-saved registers more
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122 or less in reverse order to their allocation as arguments. */
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123
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124 #define REG_ALLOC_ORDER \
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125 { \
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126 /* caller-saved fp regs. */ \
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127 50, 51, 52, 53, 54, 55, 56, 57, \
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128 58, 59, 39, 38, 37, 36, 35, 34, \
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129 33, 32, \
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130 /* caller-saved general regs. */ \
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131 28, 31, 19, 20, 21, 22, 23, 24, \
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132 25, 26, 29, 2, \
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133 /* callee-saved fp regs. */ \
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134 40, 41, 42, 43, 44, 45, 46, 47, \
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135 48, 49, \
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136 /* callee-saved general regs. */ \
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137 3, 4, 5, 6, 7, 8, 9, 10, \
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138 11, 12, 13, 14, 15, 16, 17, 18, \
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139 /* special registers. */ \
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140 1, 27, 30, 0, 60}
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141
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142
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143 /* Return number of consecutive hard regs needed starting at reg REGNO
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144 to hold something of mode MODE.
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145 This is ordinarily the length in words of a value of mode MODE
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146 but can be less for certain modes in special long registers.
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147
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148 For PA64, GPRs and FPRs hold 64 bits worth. We ignore the 32-bit
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149 addressability of the FPRs and pretend each register holds precisely
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150 WORD_SIZE bits. Note that SCmode values are placed in a single FPR.
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151 Thus, any patterns defined to operate on these values would have to
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152 use the 32-bit addressability of the FPR registers. */
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153 #define HARD_REGNO_NREGS(REGNO, MODE) \
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154 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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155
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156 /* These are the valid FP modes. */
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157 #define VALID_FP_MODE_P(MODE) \
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158 ((MODE) == SFmode || (MODE) == DFmode \
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159 || (MODE) == SCmode || (MODE) == DCmode \
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160 || (MODE) == SImode || (MODE) == DImode)
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161
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162 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
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163 On the HP-PA, the cpu registers can hold any mode. We
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164 force this to be an even register is it cannot hold the full mode. */
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165 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
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166 ((REGNO) == 0 \
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167 ? (MODE) == CCmode || (MODE) == CCFPmode \
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168 /* Make wide modes be in aligned registers. */ \
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169 : FP_REGNO_P (REGNO) \
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170 ? (VALID_FP_MODE_P (MODE) \
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171 && (GET_MODE_SIZE (MODE) <= 8 \
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172 || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 1) == 0) \
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173 || (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 3) == 0))) \
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174 : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
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175 || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD \
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176 && ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28)) \
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177 || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD \
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178 && ((REGNO) & 3) == 3 && (REGNO) <= 23)))
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179
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180 /* How to renumber registers for dbx and gdb.
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181
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182 Registers 0 - 31 remain unchanged.
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183
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184 Registers 32 - 59 are mapped to 72, 74, 76 ...
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185
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186 Register 60 is mapped to 32. */
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187 #define DBX_REGISTER_NUMBER(REGNO) \
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188 ((REGNO) <= 31 ? (REGNO) : ((REGNO) < 60 ? (REGNO - 32) * 2 + 72 : 32))
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189
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190 /* We must not use the DBX register numbers for the DWARF 2 CFA column
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191 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
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192 Instead use the identity mapping. */
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193 #define DWARF_FRAME_REGNUM(REG) REG
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194
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195 /* Define the classes of registers for register constraints in the
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196 machine description. Also define ranges of constants.
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197
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198 One of the classes must always be named ALL_REGS and include all hard regs.
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199 If there is more than one class, another class must be named NO_REGS
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200 and contain no registers.
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201
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202 The name GENERAL_REGS must be the name of a class (or an alias for
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203 another name such as ALL_REGS). This is the class of registers
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204 that is allowed by "g" or "r" in a register constraint.
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205 Also, registers outside this class are allocated only when
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206 instructions express preferences for them.
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207
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208 The classes must be numbered in nondecreasing order; that is,
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209 a larger-numbered class must never be contained completely
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210 in a smaller-numbered class.
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211
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212 For any two classes, it is very desirable that there be another
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213 class that represents their union. */
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214
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215 /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs,
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216 1.1 fp regs, and the high 1.1 fp regs, to which the operands of
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217 fmpyadd and fmpysub are restricted. */
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218
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219 enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
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220 GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
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221
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222 #define N_REG_CLASSES (int) LIM_REG_CLASSES
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223
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224 /* Give names of register classes as strings for dump file. */
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225
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226 #define REG_CLASS_NAMES \
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227 {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
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228 "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"}
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229
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230 /* Define which registers fit in which classes.
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231 This is an initializer for a vector of HARD_REG_SET
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232 of length N_REG_CLASSES. Register 0, the "condition code" register,
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233 is in no class. */
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234
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235 #define REG_CLASS_CONTENTS \
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236 {{0x00000000, 0x00000000}, /* NO_REGS */ \
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237 {0x00000002, 0x00000000}, /* R1_REGS */ \
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238 {0xfffffffe, 0x00000000}, /* GENERAL_REGS */ \
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239 {0x00000000, 0x00000000}, /* FPUPPER_REGS */ \
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240 {0x00000000, 0x0fffffff}, /* FP_REGS */ \
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241 {0xfffffffe, 0x0fffffff}, /* GENERAL_OR_FP_REGS */ \
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242 {0x00000000, 0x10000000}, /* SHIFT_REGS */ \
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243 {0xfffffffe, 0x1fffffff}} /* ALL_REGS */
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244
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245 /* The following macro defines cover classes for Integrated Register
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246 Allocator. Cover classes is a set of non-intersected register
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247 classes covering all hard registers used for register allocation
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248 purpose. Any move between two registers of a cover class should be
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249 cheaper than load or store of the registers. The macro value is
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250 array of register classes with LIM_REG_CLASSES used as the end
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251 marker. */
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252
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253 #define IRA_COVER_CLASSES \
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254 { \
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255 GENERAL_REGS, FP_REGS, SHIFT_REGS, LIM_REG_CLASSES \
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256 }
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257
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258 /* Defines invalid mode changes. */
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259
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260 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
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261 pa_cannot_change_mode_class (FROM, TO, CLASS)
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262
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263 /* Return the class number of the smallest class containing
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264 reg number REGNO. This could be a conditional expression
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265 or could index an array. */
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266
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267 #define REGNO_REG_CLASS(REGNO) \
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268 ((REGNO) == 0 ? NO_REGS \
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269 : (REGNO) == 1 ? R1_REGS \
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270 : (REGNO) < 32 ? GENERAL_REGS \
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271 : (REGNO) < 60 ? FP_REGS \
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272 : SHIFT_REGS)
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273
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274 /* Return the maximum number of consecutive registers
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275 needed to represent mode MODE in a register of class CLASS. */
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276 #define CLASS_MAX_NREGS(CLASS, MODE) \
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277 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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278
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279 /* 1 if N is a possible register number for function argument passing. */
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280
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281 #define FUNCTION_ARG_REGNO_P(N) \
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282 ((((N) >= 19) && (N) <= 26) \
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283 || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39))
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284
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285 /* How to refer to registers in assembler output.
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286 This sequence is indexed by compiler's hard-register-number (see above). */
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287
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288 #define REGISTER_NAMES \
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289 {"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \
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290 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
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291 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \
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292 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \
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293 "%fr4", "%fr5", "%fr6", "%fr7", "%fr8", "%fr9", "%fr10", "%fr11", \
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294 "%fr12", "%fr13", "%fr14", "%fr15", "%fr16", "%fr17", "%fr18", "%fr19", \
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295 "%fr20", "%fr21", "%fr22", "%fr23", "%fr24", "%fr25", "%fr26", "%fr27", \
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296 "%fr28", "%fr29", "%fr30", "%fr31", "SAR"}
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297
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298 #define ADDITIONAL_REGISTER_NAMES \
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299 {{"%cr11",60}}
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300
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301 #define FP_SAVED_REG_LAST 49
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302 #define FP_SAVED_REG_FIRST 40
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303 #define FP_REG_STEP 1
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304 #define FP_REG_FIRST 32
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305 #define FP_REG_LAST 59
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