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1 ;; Scheduling description for z900 (cpu 2064).
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2 ;; Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
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4 ;; Ulrich Weigand (uweigand@de.ibm.com).
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5
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6 ;; This file is part of GCC.
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7
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8 ;; GCC is free software; you can redistribute it and/or modify it under
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9 ;; the terms of the GNU General Public License as published by the Free
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10 ;; Software Foundation; either version 3, or (at your option) any later
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11 ;; version.
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12
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13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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14 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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15 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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16 ;; for more details.
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17
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 ;;
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23 ;; References:
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24 ;; The microarchitecture of the IBM eServer z900 processor.
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25 ;; E.M. Schwarz et al.
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26 ;; IBM Journal of Research and Development Vol. 46 No 4/5, 2002.
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27 ;;
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28 ;; z900 (cpu 2064) pipeline
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29 ;;
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30 ;; dec
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31 ;; --> | <---
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32 ;; LA bypass | agen |
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33 ;; | | |
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34 ;; --- c1 | Load bypass
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35 ;; | |
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36 ;; c2----
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37 ;; |
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38 ;; e1
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39 ;; |
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40 ;; wr
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41
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42 ;; This scheduler description is also used for the g5 and g6.
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43
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44 (define_automaton "z_ipu")
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45 (define_cpu_unit "z_e1" "z_ipu")
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46 (define_cpu_unit "z_wr" "z_ipu")
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47
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48
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49 (define_insn_reservation "z_la" 1
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50 (and (eq_attr "cpu" "z900,g5,g6")
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51 (eq_attr "type" "la"))
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52 "z_e1,z_wr")
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53
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54 (define_insn_reservation "z_larl" 1
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55 (and (eq_attr "cpu" "z900,g5,g6")
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56 (eq_attr "type" "larl"))
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57 "z_e1,z_wr")
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58
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59 (define_insn_reservation "z_load" 1
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60 (and (eq_attr "cpu" "z900,g5,g6")
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61 (eq_attr "type" "load"))
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62 "z_e1,z_wr")
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63
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64 (define_insn_reservation "z_store" 1
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65 (and (eq_attr "cpu" "z900,g5,g6")
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66 (eq_attr "type" "store"))
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67 "z_e1,z_wr")
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68
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69 (define_insn_reservation "z_sem" 2
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70 (and (eq_attr "cpu" "z900,g5,g6")
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71 (eq_attr "type" "sem"))
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72 "z_e1*2,z_wr")
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73
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74 (define_insn_reservation "z_call" 5
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75 (and (eq_attr "cpu" "z900,g5,g6")
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76 (eq_attr "type" "jsr"))
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77 "z_e1*5,z_wr")
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78
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79 (define_insn_reservation "z_mul" 5
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80 (and (eq_attr "cpu" "g5,g6,z900")
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81 (eq_attr "type" "imulsi,imulhi"))
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82 "z_e1*5,z_wr")
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83
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84 (define_insn_reservation "z_inf" 10
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85 (and (eq_attr "cpu" "g5,g6,z900")
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86 (eq_attr "type" "idiv,imuldi"))
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87 "z_e1*10,z_wr")
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88
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89 ;; For everything else we check the atype flag.
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90
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91 (define_insn_reservation "z_int" 1
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92 (and (eq_attr "cpu" "z900,g5,g6")
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93 (and (not (eq_attr "type" "la,larl,load,store,jsr"))
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94 (eq_attr "atype" "reg")))
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95 "z_e1,z_wr")
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96
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97 (define_insn_reservation "z_agen" 1
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98 (and (eq_attr "cpu" "z900,g5,g6")
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99 (and (not (eq_attr "type" "la,larl,load,store,jsr"))
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100 (eq_attr "atype" "agen")))
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101 "z_e1,z_wr")
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102
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103 ;;
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104 ;; s390_agen_dep_p returns 1, if a register is set in the
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105 ;; first insn and used in the dependent insn to form a address.
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106 ;;
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107
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108 ;;
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109 ;; If an instruction uses a register to address memory, it needs
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110 ;; to be set 5 cycles in advance.
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111 ;;
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112
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113 (define_bypass 5 "z_int,z_agen"
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114 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
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115
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116 ;;
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117 ;; A load type instruction uses a bypass to feed the result back
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118 ;; to the address generation pipeline stage.
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119 ;;
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120
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121 (define_bypass 3 "z_load"
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122 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
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123
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124 ;;
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125 ;; A load address type instruction uses a bypass to feed the
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126 ;; result back to the address generation pipeline stage.
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127 ;;
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128
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129 (define_bypass 2 "z_larl,z_la"
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130 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
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131
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132
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133
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134
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135
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