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1 ;; Scheduling description for z990 (cpu 2084).
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2 ;; Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008
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3 ;; Free Software Foundation, Inc.
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4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
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5 ;; Ulrich Weigand (uweigand@de.ibm.com).
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6
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7 ;; This file is part of GCC.
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8
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9 ;; GCC is free software; you can redistribute it and/or modify it under
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10 ;; the terms of the GNU General Public License as published by the Free
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11 ;; Software Foundation; either version 3, or (at your option) any later
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12 ;; version.
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13
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14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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17 ;; for more details.
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18
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19 ;; You should have received a copy of the GNU General Public License
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20 ;; along with GCC; see the file COPYING3. If not see
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21 ;; <http://www.gnu.org/licenses/>.
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22
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23 (define_automaton "x_ipu")
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24
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25 (define_cpu_unit "x_e1_r,x_e1_s,x_e1_t" "x_ipu")
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26 (define_cpu_unit "x_wr_r,x_wr_s,x_wr_t,x_wr_fp" "x_ipu")
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27 (define_cpu_unit "x_s1,x_s2,x_s3,x_s4" "x_ipu")
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28 (define_cpu_unit "x_t1,x_t2,x_t3,x_t4" "x_ipu")
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29 (define_cpu_unit "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6" "x_ipu")
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30 (define_cpu_unit "x_store_tok" "x_ipu")
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31 (define_cpu_unit "x_ms,x_mt" "x_ipu")
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32
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33 (define_reservation "x-e1-st" "(x_e1_s | x_e1_t)")
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34
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35 (define_reservation "x-e1-np" "(x_e1_r + x_e1_s + x_e1_t)")
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36
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37 (absence_set "x_e1_r" "x_e1_s,x_e1_t")
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38 (absence_set "x_e1_s" "x_e1_t")
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39
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40 ;; Try to avoid int <-> fp transitions.
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41
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42 (define_reservation "x-x" "x_s1|x_t1,x_s2|x_t2,x_s3|x_t3,x_s4|x_t4")
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43 (define_reservation "x-f" "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6")
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44 (define_reservation "x-wr-st" "((x_wr_s | x_wr_t),x-x)")
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45 (define_reservation "x-wr-np" "((x_wr_r + x_wr_s + x_wr_t),x-x)")
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46 (define_reservation "x-wr-fp" "x_wr_fp,x-f")
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47 (define_reservation "x-mem" "x_ms|x_mt")
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48
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49 (absence_set "x_wr_fp"
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50 "x_s1,x_s2,x_s3,x_s4,x_t1,x_t2,x_t3,x_t4,x_wr_s,x_wr_t")
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51
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52 (absence_set "x_e1_r,x_wr_r,x_wr_s,x_wr_t"
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53 "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6,x_wr_fp")
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54
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55 ;; Don't have any load type insn in same group as store
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56
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57 (absence_set "x_ms,x_mt" "x_store_tok")
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58
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59
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60 ;;
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61 ;; Simple insns
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62 ;;
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63
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64 (define_insn_reservation "x_int" 1
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65 (and (eq_attr "cpu" "z990,z9_109")
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66 (and (eq_attr "type" "integer")
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67 (eq_attr "atype" "reg")))
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68 "x-e1-st,x-wr-st")
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69
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70 (define_insn_reservation "x_agen" 1
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71 (and (eq_attr "cpu" "z990,z9_109")
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72 (and (eq_attr "type" "integer")
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73 (eq_attr "atype" "agen")))
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74 "x-e1-st,x-wr-st")
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75
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76 (define_insn_reservation "x_lr" 1
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77 (and (eq_attr "cpu" "z990,z9_109")
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78 (eq_attr "type" "lr"))
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79 "x-e1-st,x-wr-st")
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80
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81 (define_insn_reservation "x_la" 1
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82 (and (eq_attr "cpu" "z990,z9_109")
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83 (eq_attr "type" "la"))
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84 "x-e1-st,x-wr-st")
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85
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86 (define_insn_reservation "x_larl" 1
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87 (and (eq_attr "cpu" "z990,z9_109")
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88 (eq_attr "type" "larl"))
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89 "x-e1-st,x-wr-st")
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90
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91 (define_insn_reservation "x_load" 1
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92 (and (eq_attr "cpu" "z990,z9_109")
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93 (eq_attr "type" "load"))
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94 "x-e1-st+x-mem,x-wr-st")
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95
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96 (define_insn_reservation "x_store" 1
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97 (and (eq_attr "cpu" "z990,z9_109")
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98 (eq_attr "type" "store"))
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99 "x-e1-st+x_store_tok,x-wr-st")
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100
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101 (define_insn_reservation "x_branch" 1
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102 (and (eq_attr "cpu" "z990,z9_109")
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103 (eq_attr "type" "branch"))
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104 "x_e1_r,x_wr_r")
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105
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106 (define_insn_reservation "x_call" 5
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107 (and (eq_attr "cpu" "z990,z9_109")
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108 (eq_attr "type" "jsr"))
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109 "x-e1-np*5,x-wr-np")
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110
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111 (define_insn_reservation "x_mul_hi" 2
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112 (and (eq_attr "cpu" "z990,z9_109")
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113 (eq_attr "type" "imulhi"))
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114 "x-e1-np*2,x-wr-np")
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115
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116 (define_insn_reservation "x_mul_sidi" 4
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117 (and (eq_attr "cpu" "z990,z9_109")
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118 (eq_attr "type" "imulsi,imuldi"))
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119 "x-e1-np*4,x-wr-np")
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120
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121 (define_insn_reservation "x_div" 10
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122 (and (eq_attr "cpu" "z990,z9_109")
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123 (eq_attr "type" "idiv"))
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124 "x-e1-np*10,x-wr-np")
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125
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126 (define_insn_reservation "x_sem" 17
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127 (and (eq_attr "cpu" "z990,z9_109")
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128 (eq_attr "type" "sem"))
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129 "x-e1-np+x-mem,x-e1-np*16,x-wr-st")
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130
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131 ;;
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132 ;; Multicycle insns
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133 ;;
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134
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135 (define_insn_reservation "x_cs" 1
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136 (and (eq_attr "cpu" "z990,z9_109")
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137 (eq_attr "type" "cs"))
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138 "x-e1-np,x-wr-np")
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139
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140 (define_insn_reservation "x_vs" 1
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141 (and (eq_attr "cpu" "z990,z9_109")
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142 (eq_attr "type" "vs"))
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143 "x-e1-np*10,x-wr-np")
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144
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145 (define_insn_reservation "x_stm" 1
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146 (and (eq_attr "cpu" "z990,z9_109")
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147 (eq_attr "type" "stm"))
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148 "(x-e1-np+x_store_tok)*10,x-wr-np")
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149
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150 (define_insn_reservation "x_lm" 1
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151 (and (eq_attr "cpu" "z990,z9_109")
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152 (eq_attr "type" "lm"))
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153 "x-e1-np*10,x-wr-np")
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154
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155 (define_insn_reservation "x_other" 1
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156 (and (eq_attr "cpu" "z990,z9_109")
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157 (eq_attr "type" "other"))
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158 "x-e1-np,x-wr-np")
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159
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160 ;;
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161 ;; Floating point insns
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162 ;;
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163
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164 (define_insn_reservation "x_fsimptf" 7
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165 (and (eq_attr "cpu" "z990,z9_109")
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166 (eq_attr "type" "fsimptf"))
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167 "x_e1_t*2,x-wr-fp")
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168
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169 (define_insn_reservation "x_fsimpdf" 6
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170 (and (eq_attr "cpu" "z990,z9_109")
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171 (eq_attr "type" "fsimpdf,fmuldf"))
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172 "x_e1_t,x-wr-fp")
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173
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174 (define_insn_reservation "x_fsimpsf" 6
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175 (and (eq_attr "cpu" "z990,z9_109")
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176 (eq_attr "type" "fsimpsf,fmulsf"))
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177 "x_e1_t,x-wr-fp")
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178
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179
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180 (define_insn_reservation "x_fmultf" 33
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181 (and (eq_attr "cpu" "z990,z9_109")
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182 (eq_attr "type" "fmultf"))
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183 "x_e1_t*27,x-wr-fp")
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184
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185
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186 (define_insn_reservation "x_fdivtf" 82
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187 (and (eq_attr "cpu" "z990,z9_109")
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188 (eq_attr "type" "fdivtf,fsqrttf"))
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189 "x_e1_t*76,x-wr-fp")
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190
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191 (define_insn_reservation "x_fdivdf" 36
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192 (and (eq_attr "cpu" "z990,z9_109")
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193 (eq_attr "type" "fdivdf,fsqrtdf"))
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194 "x_e1_t*30,x-wr-fp")
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195
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196 (define_insn_reservation "x_fdivsf" 36
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197 (and (eq_attr "cpu" "z990,z9_109")
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198 (eq_attr "type" "fdivsf,fsqrtsf"))
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199 "x_e1_t*30,x-wr-fp")
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200
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201
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202 (define_insn_reservation "x_floadtf" 6
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203 (and (eq_attr "cpu" "z990,z9_109")
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204 (eq_attr "type" "floadtf"))
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205 "x_e1_t,x-wr-fp")
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206
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207 (define_insn_reservation "x_floaddf" 6
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208 (and (eq_attr "cpu" "z990,z9_109")
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209 (eq_attr "type" "floaddf"))
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210 "x_e1_t,x-wr-fp")
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211
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212 (define_insn_reservation "x_floadsf" 6
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213 (and (eq_attr "cpu" "z990,z9_109")
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214 (eq_attr "type" "floadsf"))
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215 "x_e1_t,x-wr-fp")
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216
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217
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218 (define_insn_reservation "x_fstoredf" 1
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219 (and (eq_attr "cpu" "z990,z9_109")
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220 (eq_attr "type" "fstoredf"))
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221 "x_e1_t,x-wr-fp")
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222
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223 (define_insn_reservation "x_fstoresf" 1
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224 (and (eq_attr "cpu" "z990,z9_109")
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225 (eq_attr "type" "fstoresf"))
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226 "x_e1_t,x-wr-fp")
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227
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228
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229 (define_insn_reservation "x_ftrunctf" 16
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230 (and (eq_attr "cpu" "z990,z9_109")
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231 (eq_attr "type" "ftrunctf"))
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232 "x_e1_t*10,x-wr-fp")
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233
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234 (define_insn_reservation "x_ftruncdf" 11
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235 (and (eq_attr "cpu" "z990,z9_109")
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236 (eq_attr "type" "ftruncdf"))
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237 "x_e1_t*5,x-wr-fp")
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238
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239
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240 (define_insn_reservation "x_ftoi" 1
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241 (and (eq_attr "cpu" "z990,z9_109")
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242 (eq_attr "type" "ftoi"))
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243 "x_e1_t*3,x-wr-fp")
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244
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245 (define_insn_reservation "x_itof" 7
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246 (and (eq_attr "cpu" "z990,z9_109")
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247 (eq_attr "type" "itoftf,itofdf,itofsf"))
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248 "x_e1_t*3,x-wr-fp")
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249
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250 (define_bypass 1 "x_fsimpdf" "x_fstoredf")
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251
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252 (define_bypass 1 "x_fsimpsf" "x_fstoresf")
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253
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254 (define_bypass 1 "x_floaddf" "x_fsimpdf,x_fstoredf,x_floaddf")
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255
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256 (define_bypass 1 "x_floadsf" "x_fsimpsf,x_fstoresf,x_floadsf")
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257
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258 ;;
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259 ;; s390_agen_dep_p returns 1, if a register is set in the
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260 ;; first insn and used in the dependent insn to form a address.
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261 ;;
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262
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263 ;;
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264 ;; If an instruction uses a register to address memory, it needs
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265 ;; to be set 5 cycles in advance.
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266 ;;
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267
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268 (define_bypass 5 "x_int,x_agen,x_lr"
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269 "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
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270 "s390_agen_dep_p")
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271
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272 (define_bypass 9 "x_int,x_agen,x_lr"
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273 "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
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274 x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
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275 "s390_agen_dep_p")
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276 ;;
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277 ;; A load type instruction uses a bypass to feed the result back
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278 ;; to the address generation pipeline stage.
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279 ;;
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280
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281 (define_bypass 4 "x_load"
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282 "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
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283 "s390_agen_dep_p")
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284
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285 (define_bypass 5 "x_load"
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286 "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
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287 x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
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288 "s390_agen_dep_p")
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289
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290 ;;
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291 ;; A load address type instruction uses a bypass to feed the
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292 ;; result back to the address generation pipeline stage.
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293 ;;
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294
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295 (define_bypass 3 "x_larl,x_la"
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296 "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
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297 "s390_agen_dep_p")
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298
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299 (define_bypass 5 "x_larl, x_la"
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300 "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
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301 x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
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302 "s390_agen_dep_p")
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303
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304 ;;
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305 ;; Operand forwarding
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306 ;;
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307
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308 (define_bypass 0 "x_lr,x_la,x_load" "x_int,x_lr")
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309
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310
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