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1 ;; Predicate definitions for S/390 and zSeries.
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2 ;; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
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3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
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4 ;; Ulrich Weigand (uweigand@de.ibm.com).
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5 ;;
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6 ;; This file is part of GCC.
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7 ;;
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8 ;; GCC is free software; you can redistribute it and/or modify
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9 ;; it under the terms of the GNU General Public License as published by
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10 ;; the Free Software Foundation; either version 3, or (at your option)
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11 ;; any later version.
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12 ;;
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13 ;; GCC is distributed in the hope that it will be useful,
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14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 ;; GNU General Public License for more details.
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17 ;;
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 ;; OP is the current operation.
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23 ;; MODE is the current operation mode.
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24
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25 ;; operands --------------------------------------------------------------
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26
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27 ;; Return true if OP a (const_int 0) operand.
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28
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29 (define_predicate "const0_operand"
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30 (and (match_code "const_int, const_double")
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31 (match_test "op == CONST0_RTX (mode)")))
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32
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33 ;; Return true if OP is constant.
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34
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35 (define_special_predicate "consttable_operand"
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36 (and (match_code "symbol_ref, label_ref, const, const_int, const_double")
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37 (match_test "CONSTANT_P (op)")))
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38
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39 ;; Return true if OP is a valid S-type operand.
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40
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41 (define_predicate "s_operand"
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42 (and (match_code "subreg, mem")
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43 (match_operand 0 "general_operand"))
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44 {
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45 /* Just like memory_operand, allow (subreg (mem ...))
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46 after reload. */
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47 if (reload_completed
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48 && GET_CODE (op) == SUBREG
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49 && GET_CODE (SUBREG_REG (op)) == MEM)
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50 op = SUBREG_REG (op);
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51
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52 if (GET_CODE (op) != MEM)
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53 return false;
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54 if (!s390_legitimate_address_without_index_p (op))
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55 return false;
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56
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57 return true;
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58 })
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59
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60 ;; Return true if OP is a valid operand for the BRAS instruction.
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61 ;; Allow SYMBOL_REFs and @PLT stubs.
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62
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63 (define_special_predicate "bras_sym_operand"
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64 (ior (and (match_code "symbol_ref")
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65 (match_test "!flag_pic || SYMBOL_REF_LOCAL_P (op)"))
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66 (and (match_code "const")
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67 (and (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC")
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68 (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_PLT")))))
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69
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70 ;; Return true if OP is a PLUS that is not a legitimate
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71 ;; operand for the LA instruction.
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72
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73 (define_predicate "s390_plus_operand"
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74 (and (match_code "plus")
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75 (and (match_test "mode == Pmode")
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76 (match_test "!legitimate_la_operand_p (op)"))))
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77
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78 ;; Return true if OP is a valid operand as shift count or setmem.
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79
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80 (define_predicate "shift_count_or_setmem_operand"
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81 (match_code "reg, subreg, plus, const_int")
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82 {
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83 HOST_WIDE_INT offset;
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84 rtx base;
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85
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86 /* Extract base register and offset. */
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87 if (!s390_decompose_shift_count (op, &base, &offset))
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88 return false;
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89
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90 /* Don't allow any non-base hard registers. Doing so without
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91 confusing reload and/or regrename would be tricky, and doesn't
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92 buy us much anyway. */
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93 if (base && REGNO (base) < FIRST_PSEUDO_REGISTER && !ADDR_REG_P (base))
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94 return false;
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95
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96 /* Unfortunately we have to reject constants that are invalid
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97 for an address, or else reload will get confused. */
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98 if (!DISP_IN_RANGE (offset))
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99 return false;
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100
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101 return true;
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102 })
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103
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104 ;; Return true if OP a valid operand for the LARL instruction.
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105
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106 (define_predicate "larl_operand"
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107 (match_code "label_ref, symbol_ref, const, const_int, const_double")
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108 {
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109 /* Allow labels and local symbols. */
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110 if (GET_CODE (op) == LABEL_REF)
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111 return true;
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112 if (GET_CODE (op) == SYMBOL_REF)
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113 return (!SYMBOL_REF_ALIGN1_P (op)
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114 && SYMBOL_REF_TLS_MODEL (op) == 0
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115 && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
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116
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117 /* Everything else must have a CONST, so strip it. */
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118 if (GET_CODE (op) != CONST)
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119 return false;
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120 op = XEXP (op, 0);
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121
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122 /* Allow adding *even* in-range constants. */
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123 if (GET_CODE (op) == PLUS)
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124 {
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125 if (GET_CODE (XEXP (op, 1)) != CONST_INT
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126 || (INTVAL (XEXP (op, 1)) & 1) != 0)
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127 return false;
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128 if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 31
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129 || INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 31))
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130 return false;
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131 op = XEXP (op, 0);
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132 }
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133
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134 /* Labels and local symbols allowed here as well. */
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135 if (GET_CODE (op) == LABEL_REF)
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136 return true;
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137 if (GET_CODE (op) == SYMBOL_REF)
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138 return ((SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_ALIGN1) == 0
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139 && SYMBOL_REF_TLS_MODEL (op) == 0
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140 && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
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141
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142 /* Now we must have a @GOTENT offset or @PLT stub
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143 or an @INDNTPOFF TLS offset. */
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144 if (GET_CODE (op) == UNSPEC
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145 && XINT (op, 1) == UNSPEC_GOTENT)
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146 return true;
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147 if (GET_CODE (op) == UNSPEC
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148 && XINT (op, 1) == UNSPEC_PLT)
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149 return true;
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150 if (GET_CODE (op) == UNSPEC
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151 && XINT (op, 1) == UNSPEC_INDNTPOFF)
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152 return true;
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153
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154 return false;
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155 })
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156
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157 ;; operators --------------------------------------------------------------
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158
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159 ;; Return nonzero if OP is a valid comparison operator
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160 ;; for a branch condition.
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161
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162 (define_predicate "s390_comparison"
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163 (match_code "eq, ne, lt, gt, le, ge, ltu, gtu, leu, geu,
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164 uneq, unlt, ungt, unle, unge, ltgt,
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165 unordered, ordered")
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166 {
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167 if (GET_CODE (XEXP (op, 0)) != REG
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168 || REGNO (XEXP (op, 0)) != CC_REGNUM
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169 || XEXP (op, 1) != const0_rtx)
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170 return false;
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171
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172 return (s390_branch_condition_mask (op) >= 0);
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173 })
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174
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175 (define_predicate "s390_signed_integer_comparison"
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176 (match_code "eq, ne, lt, gt, le, ge")
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177 {
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178 return (s390_compare_and_branch_condition_mask (op) >= 0);
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179 })
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180
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181 (define_predicate "s390_unsigned_integer_comparison"
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182 (match_code "eq, ne, ltu, gtu, leu, geu")
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183 {
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184 return (s390_compare_and_branch_condition_mask (op) >= 0);
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185 })
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186
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187 ;; Return nonzero if OP is a valid comparison operator
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188 ;; for an ALC condition.
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189
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190 (define_predicate "s390_alc_comparison"
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191 (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
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192 {
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193 while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
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194 op = XEXP (op, 0);
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195
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196 if (!COMPARISON_P (op))
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197 return false;
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198
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199 if (GET_CODE (XEXP (op, 0)) != REG
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200 || REGNO (XEXP (op, 0)) != CC_REGNUM
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201 || XEXP (op, 1) != const0_rtx)
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202 return false;
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203
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204 switch (GET_MODE (XEXP (op, 0)))
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205 {
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206 case CCL1mode:
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207 return GET_CODE (op) == LTU;
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208
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209 case CCL2mode:
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210 return GET_CODE (op) == LEU;
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211
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212 case CCL3mode:
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213 return GET_CODE (op) == GEU;
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214
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215 case CCUmode:
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216 return GET_CODE (op) == GTU;
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217
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218 case CCURmode:
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219 return GET_CODE (op) == LTU;
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220
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221 case CCSmode:
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222 return GET_CODE (op) == UNGT;
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223
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224 case CCSRmode:
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225 return GET_CODE (op) == UNLT;
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226
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227 default:
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228 return false;
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229 }
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230 })
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231
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232 ;; Return nonzero if OP is a valid comparison operator
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233 ;; for an SLB condition.
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234
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235 (define_predicate "s390_slb_comparison"
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236 (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
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237 {
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238 while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
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239 op = XEXP (op, 0);
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240
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241 if (!COMPARISON_P (op))
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242 return false;
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243
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244 if (GET_CODE (XEXP (op, 0)) != REG
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245 || REGNO (XEXP (op, 0)) != CC_REGNUM
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246 || XEXP (op, 1) != const0_rtx)
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247 return false;
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248
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249 switch (GET_MODE (XEXP (op, 0)))
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250 {
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251 case CCL1mode:
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252 return GET_CODE (op) == GEU;
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253
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254 case CCL2mode:
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255 return GET_CODE (op) == GTU;
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256
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257 case CCL3mode:
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258 return GET_CODE (op) == LTU;
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259
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260 case CCUmode:
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261 return GET_CODE (op) == LEU;
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262
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263 case CCURmode:
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264 return GET_CODE (op) == GEU;
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265
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266 case CCSmode:
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267 return GET_CODE (op) == LE;
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268
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269 case CCSRmode:
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270 return GET_CODE (op) == GE;
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271
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272 default:
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273 return false;
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274 }
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275 })
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276
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277 ;; Return true if OP is a load multiple operation. It is known to be a
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278 ;; PARALLEL and the first section will be tested.
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279
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280 (define_special_predicate "load_multiple_operation"
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281 (match_code "parallel")
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282 {
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283 enum machine_mode elt_mode;
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284 int count = XVECLEN (op, 0);
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285 unsigned int dest_regno;
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286 rtx src_addr;
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287 int i, off;
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288
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289 /* Perform a quick check so we don't blow up below. */
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290 if (count <= 1
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291 || GET_CODE (XVECEXP (op, 0, 0)) != SET
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292 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
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293 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
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294 return false;
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295
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296 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
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297 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
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298 elt_mode = GET_MODE (SET_DEST (XVECEXP (op, 0, 0)));
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299
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300 /* Check, is base, or base + displacement. */
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301
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302 if (GET_CODE (src_addr) == REG)
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303 off = 0;
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304 else if (GET_CODE (src_addr) == PLUS
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305 && GET_CODE (XEXP (src_addr, 0)) == REG
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306 && GET_CODE (XEXP (src_addr, 1)) == CONST_INT)
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307 {
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308 off = INTVAL (XEXP (src_addr, 1));
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309 src_addr = XEXP (src_addr, 0);
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310 }
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311 else
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312 return false;
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313
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314 for (i = 1; i < count; i++)
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315 {
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316 rtx elt = XVECEXP (op, 0, i);
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317
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318 if (GET_CODE (elt) != SET
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319 || GET_CODE (SET_DEST (elt)) != REG
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320 || GET_MODE (SET_DEST (elt)) != elt_mode
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321 || REGNO (SET_DEST (elt)) != dest_regno + i
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322 || GET_CODE (SET_SRC (elt)) != MEM
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323 || GET_MODE (SET_SRC (elt)) != elt_mode
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324 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
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325 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
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326 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
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327 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1))
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328 != off + i * GET_MODE_SIZE (elt_mode))
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329 return false;
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330 }
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331
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332 return true;
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333 })
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334
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335 ;; Return true if OP is a store multiple operation. It is known to be a
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336 ;; PARALLEL and the first section will be tested.
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337
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338 (define_special_predicate "store_multiple_operation"
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339 (match_code "parallel")
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340 {
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341 enum machine_mode elt_mode;
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342 int count = XVECLEN (op, 0);
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343 unsigned int src_regno;
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344 rtx dest_addr;
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345 int i, off;
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346
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347 /* Perform a quick check so we don't blow up below. */
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348 if (count <= 1
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349 || GET_CODE (XVECEXP (op, 0, 0)) != SET
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350 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
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351 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
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352 return false;
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353
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354 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
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355 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
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356 elt_mode = GET_MODE (SET_SRC (XVECEXP (op, 0, 0)));
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357
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358 /* Check, is base, or base + displacement. */
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359
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360 if (GET_CODE (dest_addr) == REG)
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361 off = 0;
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362 else if (GET_CODE (dest_addr) == PLUS
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363 && GET_CODE (XEXP (dest_addr, 0)) == REG
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364 && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
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365 {
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366 off = INTVAL (XEXP (dest_addr, 1));
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367 dest_addr = XEXP (dest_addr, 0);
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368 }
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369 else
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370 return false;
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371
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372 for (i = 1; i < count; i++)
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373 {
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374 rtx elt = XVECEXP (op, 0, i);
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375
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376 if (GET_CODE (elt) != SET
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377 || GET_CODE (SET_SRC (elt)) != REG
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378 || GET_MODE (SET_SRC (elt)) != elt_mode
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379 || REGNO (SET_SRC (elt)) != src_regno + i
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380 || GET_CODE (SET_DEST (elt)) != MEM
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381 || GET_MODE (SET_DEST (elt)) != elt_mode
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382 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
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383 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
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384 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
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385 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1))
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386 != off + i * GET_MODE_SIZE (elt_mode))
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387 return false;
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388 }
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389 return true;
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390 })
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