annotate gcc/config/score/predicates.md @ 0:a06113de4d67

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author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
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children f6334be47118
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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1 ;; Predicate definitions for Sunplus S+CORE.
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2 ;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_predicate "const_uimm5"
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21 (match_code "const_int")
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22 {
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23 return IMM_IN_RANGE (INTVAL (op), 5, 0);
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24 })
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25
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26 (define_predicate "const_simm12"
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27 (match_code "const_int")
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28 {
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29 return IMM_IN_RANGE (INTVAL (op), 12, 1);
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30 })
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31
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32 (define_predicate "const_simm15"
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33 (match_code "const_int")
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34 {
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35 return IMM_IN_RANGE (INTVAL (op), 15, 1);
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36 })
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37
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38 (define_predicate "arith_operand"
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39 (ior (match_code "const_int")
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40 (match_operand 0 "register_operand")))
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41
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42 (define_predicate "score_register_operand"
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43 (match_code "reg,subreg")
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44 {
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45 if (GET_CODE (op) == SUBREG)
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46 op = SUBREG_REG (op);
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47
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48 return (GET_CODE (op) == REG)
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49 && (REGNO (op) != CC_REGNUM);
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50 })
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51
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52 (define_predicate "const_call_insn_operand"
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53 (match_code "const,symbol_ref,label_ref")
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54 {
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55 enum score_symbol_type symbol_type;
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56
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57 return (score_symbolic_constant_p (op, &symbol_type)
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58 && (symbol_type == SYMBOL_GENERAL));
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59 })
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60
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61 (define_predicate "call_insn_operand"
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62 (ior (match_operand 0 "const_call_insn_operand")
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63 (match_operand 0 "register_operand")))
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64
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65 (define_predicate "hireg_operand"
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66 (and (match_code "reg")
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67 (match_test "REGNO (op) == HI_REGNUM")))
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68
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69 (define_predicate "loreg_operand"
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70 (and (match_code "reg")
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71 (match_test "REGNO (op) == LO_REGNUM")))
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72
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73 (define_predicate "sr0_operand"
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74 (and (match_code "reg")
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75 (match_test "REGNO (op) == CN_REGNUM")))
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76
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77 (define_predicate "g32reg_operand"
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78 (and (match_code "reg")
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79 (match_test "GP_REG_P (REGNO (op))")))
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80
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81 (define_predicate "branch_n_operator"
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82 (match_code "lt,ge"))
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83
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84 (define_predicate "branch_nz_operator"
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85 (match_code "eq,ne,lt,ge"))
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86
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87 (define_predicate "score_load_multiple_operation"
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88 (match_code "parallel")
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89 {
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90 int count = XVECLEN (op, 0);
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91 int dest_regno;
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92 rtx src_addr;
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93 int i;
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94
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95 /* Perform a quick check so we don't blow up below. */
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96 if (count <= 1
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97 || GET_CODE (XVECEXP (op, 0, 0)) != SET
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98 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
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99 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
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100 return 0;
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101
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102 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
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103 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
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104
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105 for (i = 1; i < count; i++)
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106 {
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107 rtx elt = XVECEXP (op, 0, i);
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108
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109 if (GET_CODE (elt) != SET
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110 || GET_CODE (SET_DEST (elt)) != REG
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111 || GET_MODE (SET_DEST (elt)) != SImode
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112 || REGNO (SET_DEST (elt)) != (unsigned) (dest_regno + i)
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113 || GET_CODE (SET_SRC (elt)) != MEM
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114 || GET_MODE (SET_SRC (elt)) != SImode
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115 || GET_CODE (XEXP (SET_SRC (elt), 0)) != POST_INC)
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116 return 0;
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117 }
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118
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119 return 1;
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120 })
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121
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122 (define_predicate "score_store_multiple_operation"
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123 (match_code "parallel")
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124 {
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125 int count = XVECLEN (op, 0);
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126 int src_regno;
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127 rtx dest_addr;
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128 int i;
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129
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130 /* Perform a quick check so we don't blow up below. */
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131 if (count <= 1
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132 || GET_CODE (XVECEXP (op, 0, 0)) != SET
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133 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
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134 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
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135 return 0;
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136
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137 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
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138 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
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139
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140 for (i = 1; i < count; i++)
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141 {
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142 rtx elt = XVECEXP (op, 0, i);
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143
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144 if (GET_CODE (elt) != SET
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145 || GET_CODE (SET_SRC (elt)) != REG
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146 || GET_MODE (SET_SRC (elt)) != SImode
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147 || REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
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148 || GET_CODE (SET_DEST (elt)) != MEM
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149 || GET_MODE (SET_DEST (elt)) != SImode
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
150 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PRE_DEC)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
151 return 0;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
152 }
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
153
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
154 return 1;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
155 })
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
156