0
|
1 ;; Predicate definitions for Sunplus S+CORE.
|
|
2 ;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
|
|
3 ;;
|
|
4 ;; This file is part of GCC.
|
|
5 ;;
|
|
6 ;; GCC is free software; you can redistribute it and/or modify
|
|
7 ;; it under the terms of the GNU General Public License as published by
|
|
8 ;; the Free Software Foundation; either version 3, or (at your option)
|
|
9 ;; any later version.
|
|
10 ;;
|
|
11 ;; GCC is distributed in the hope that it will be useful,
|
|
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
14 ;; GNU General Public License for more details.
|
|
15 ;;
|
|
16 ;; You should have received a copy of the GNU General Public License
|
|
17 ;; along with GCC; see the file COPYING3. If not see
|
|
18 ;; <http://www.gnu.org/licenses/>.
|
|
19
|
|
20 (define_predicate "const_uimm5"
|
|
21 (match_code "const_int")
|
|
22 {
|
|
23 return IMM_IN_RANGE (INTVAL (op), 5, 0);
|
|
24 })
|
|
25
|
|
26 (define_predicate "const_simm12"
|
|
27 (match_code "const_int")
|
|
28 {
|
|
29 return IMM_IN_RANGE (INTVAL (op), 12, 1);
|
|
30 })
|
|
31
|
|
32 (define_predicate "const_simm15"
|
|
33 (match_code "const_int")
|
|
34 {
|
|
35 return IMM_IN_RANGE (INTVAL (op), 15, 1);
|
|
36 })
|
|
37
|
|
38 (define_predicate "arith_operand"
|
|
39 (ior (match_code "const_int")
|
|
40 (match_operand 0 "register_operand")))
|
|
41
|
|
42 (define_predicate "score_register_operand"
|
|
43 (match_code "reg,subreg")
|
|
44 {
|
|
45 if (GET_CODE (op) == SUBREG)
|
|
46 op = SUBREG_REG (op);
|
|
47
|
|
48 return (GET_CODE (op) == REG)
|
|
49 && (REGNO (op) != CC_REGNUM);
|
|
50 })
|
|
51
|
|
52 (define_predicate "const_call_insn_operand"
|
|
53 (match_code "const,symbol_ref,label_ref")
|
|
54 {
|
|
55 enum score_symbol_type symbol_type;
|
|
56
|
|
57 return (score_symbolic_constant_p (op, &symbol_type)
|
|
58 && (symbol_type == SYMBOL_GENERAL));
|
|
59 })
|
|
60
|
|
61 (define_predicate "call_insn_operand"
|
|
62 (ior (match_operand 0 "const_call_insn_operand")
|
|
63 (match_operand 0 "register_operand")))
|
|
64
|
|
65 (define_predicate "hireg_operand"
|
|
66 (and (match_code "reg")
|
|
67 (match_test "REGNO (op) == HI_REGNUM")))
|
|
68
|
|
69 (define_predicate "loreg_operand"
|
|
70 (and (match_code "reg")
|
|
71 (match_test "REGNO (op) == LO_REGNUM")))
|
|
72
|
|
73 (define_predicate "sr0_operand"
|
|
74 (and (match_code "reg")
|
|
75 (match_test "REGNO (op) == CN_REGNUM")))
|
|
76
|
|
77 (define_predicate "g32reg_operand"
|
|
78 (and (match_code "reg")
|
|
79 (match_test "GP_REG_P (REGNO (op))")))
|
|
80
|
|
81 (define_predicate "branch_n_operator"
|
|
82 (match_code "lt,ge"))
|
|
83
|
|
84 (define_predicate "branch_nz_operator"
|
|
85 (match_code "eq,ne,lt,ge"))
|
|
86
|
|
87 (define_predicate "score_load_multiple_operation"
|
|
88 (match_code "parallel")
|
|
89 {
|
|
90 int count = XVECLEN (op, 0);
|
|
91 int dest_regno;
|
|
92 rtx src_addr;
|
|
93 int i;
|
|
94
|
|
95 /* Perform a quick check so we don't blow up below. */
|
|
96 if (count <= 1
|
|
97 || GET_CODE (XVECEXP (op, 0, 0)) != SET
|
|
98 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
|
|
99 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
|
|
100 return 0;
|
|
101
|
|
102 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
|
|
103 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
|
|
104
|
|
105 for (i = 1; i < count; i++)
|
|
106 {
|
|
107 rtx elt = XVECEXP (op, 0, i);
|
|
108
|
|
109 if (GET_CODE (elt) != SET
|
|
110 || GET_CODE (SET_DEST (elt)) != REG
|
|
111 || GET_MODE (SET_DEST (elt)) != SImode
|
|
112 || REGNO (SET_DEST (elt)) != (unsigned) (dest_regno + i)
|
|
113 || GET_CODE (SET_SRC (elt)) != MEM
|
|
114 || GET_MODE (SET_SRC (elt)) != SImode
|
|
115 || GET_CODE (XEXP (SET_SRC (elt), 0)) != POST_INC)
|
|
116 return 0;
|
|
117 }
|
|
118
|
|
119 return 1;
|
|
120 })
|
|
121
|
|
122 (define_predicate "score_store_multiple_operation"
|
|
123 (match_code "parallel")
|
|
124 {
|
|
125 int count = XVECLEN (op, 0);
|
|
126 int src_regno;
|
|
127 rtx dest_addr;
|
|
128 int i;
|
|
129
|
|
130 /* Perform a quick check so we don't blow up below. */
|
|
131 if (count <= 1
|
|
132 || GET_CODE (XVECEXP (op, 0, 0)) != SET
|
|
133 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
|
|
134 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
|
|
135 return 0;
|
|
136
|
|
137 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
|
|
138 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
|
|
139
|
|
140 for (i = 1; i < count; i++)
|
|
141 {
|
|
142 rtx elt = XVECEXP (op, 0, i);
|
|
143
|
|
144 if (GET_CODE (elt) != SET
|
|
145 || GET_CODE (SET_SRC (elt)) != REG
|
|
146 || GET_MODE (SET_SRC (elt)) != SImode
|
|
147 || REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
|
|
148 || GET_CODE (SET_DEST (elt)) != MEM
|
|
149 || GET_MODE (SET_DEST (elt)) != SImode
|
|
150 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PRE_DEC)
|
|
151 return 0;
|
|
152 }
|
|
153
|
|
154 return 1;
|
|
155 })
|
|
156
|