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1 ;; DFA scheduling description for Renesas / SuperH SH.
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2 ;; Copyright (C) 2004, 2006, 2007 Free Software Foundation, Inc.
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3
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4 ;; This file is part of GCC.
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5
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; Load and store instructions save a cycle if they are aligned on a
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21 ;; four byte boundary. Using a function unit for stores encourages
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22 ;; gcc to separate load and store instructions by one instruction,
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23 ;; which makes it more likely that the linker will be able to word
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24 ;; align them when relaxing.
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25
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26 ;; SH-1 scheduling. This is just a conversion of the old scheduling
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27 ;; model, using define_function_unit.
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28
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29 (define_automaton "sh1")
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30 (define_cpu_unit "sh1memory,sh1int,sh1mpy,sh1fp" "sh1")
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31
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32 ;; Loads have a latency of two.
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33 ;; However, call insns can have a delay slot, so that we want one more
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34 ;; insn to be scheduled between the load of the function address and the call.
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35 ;; This is equivalent to a latency of three.
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36 ;; ADJUST_COST can only properly handle reductions of the cost, so we
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37 ;; use a latency of three here.
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38 ;; We only do this for SImode loads of general registers, to make the work
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39 ;; for ADJUST_COST easier.
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40 (define_insn_reservation "sh1_load_si" 3
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41 (and (eq_attr "pipe_model" "sh1")
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42 (eq_attr "type" "load_si,pcload_si"))
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43 "sh1memory*2")
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44
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45 (define_insn_reservation "sh1_load_store" 2
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46 (and (eq_attr "pipe_model" "sh1")
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47 (eq_attr "type" "load,pcload,pload,mem_mac,store,fstore,pstore,mac_mem"))
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48 "sh1memory*2")
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49
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50 (define_insn_reservation "sh1_arith3" 3
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51 (and (eq_attr "pipe_model" "sh1")
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52 (eq_attr "type" "arith3,arith3b"))
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53 "sh1int*3")
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54
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55 (define_insn_reservation "sh1_dyn_shift" 2
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56 (and (eq_attr "pipe_model" "sh1")
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57 (eq_attr "type" "dyn_shift"))
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58 "sh1int*2")
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59
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60 (define_insn_reservation "sh1_int" 1
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61 (and (eq_attr "pipe_model" "sh1")
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62 (eq_attr "type" "!arith3,arith3b,dyn_shift"))
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63 "sh1int")
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64
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65 ;; ??? These are approximations.
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66 (define_insn_reservation "sh1_smpy" 2
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67 (and (eq_attr "pipe_model" "sh1")
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68 (eq_attr "type" "smpy"))
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69 "sh1mpy*2")
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70
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71 (define_insn_reservation "sh1_dmpy" 3
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72 (and (eq_attr "pipe_model" "sh1")
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73 (eq_attr "type" "dmpy"))
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74 "sh1mpy*3")
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75
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76 (define_insn_reservation "sh1_fp" 2
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77 (and (eq_attr "pipe_model" "sh1")
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78 (eq_attr "type" "fp,fpscr_toggle,fp_cmp,fmove"))
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79 "sh1fp")
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80
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81 (define_insn_reservation "sh1_fdiv" 13
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82 (and (eq_attr "pipe_model" "sh1")
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83 (eq_attr "type" "fdiv"))
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84 "sh1fp*12")
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85
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