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1 ;; Scheduling description for HyperSPARC.
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2 ;; Copyright (C) 2002, 2007 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; The HyperSPARC is a dual-issue processor. It is not all that fancy.
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21
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22 ;; ??? There are some things not modelled. For example, sethi+or
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23 ;; ??? coming right after each other are specifically identified and
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24 ;; ??? dual-issued by the processor. Similarly for sethi+ld[reg+lo].
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25 ;; ??? Actually, to be more precise that rule is sort of modelled now.
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26
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27 (define_automaton "hypersparc_0,hypersparc_1")
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28
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29 ;; HyperSPARC/sparclite86x scheduling
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30
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31 (define_cpu_unit "hs_memory,hs_branch,hs_shift,hs_fpalu" "hypersparc_0")
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32 (define_cpu_unit "hs_fpmds" "hypersparc_1")
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33
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34 (define_insn_reservation "hs_load" 1
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35 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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36 (eq_attr "type" "load,sload,fpload"))
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37 "hs_memory")
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38
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39 (define_insn_reservation "hs_store" 2
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40 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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41 (eq_attr "type" "store,fpstore"))
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42 "hs_memory, nothing")
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43
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44 (define_insn_reservation "hs_slbranch" 1
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45 (and (eq_attr "cpu" "sparclite86x")
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46 (eq_attr "type" "branch"))
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47 "hs_branch")
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48
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49 (define_insn_reservation "hs_slshift" 1
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50 (and (eq_attr "cpu" "sparclite86x")
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51 (eq_attr "type" "shift"))
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52 "hs_shift")
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53
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54 (define_insn_reservation "hs_fp_alu" 1
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55 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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56 (eq_attr "type" "fp,fpmove,fpcmp"))
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57 "hs_fpalu")
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58
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59 (define_insn_reservation "hs_fp_mult" 1
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60 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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61 (eq_attr "type" "fpmul"))
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62 "hs_fpmds")
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63
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64 (define_insn_reservation "hs_fp_divs" 8
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65 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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66 (eq_attr "type" "fpdivs"))
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67 "hs_fpmds*6, nothing*2")
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68
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69 (define_insn_reservation "hs_fp_divd" 12
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70 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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71 (eq_attr "type" "fpdivd"))
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72 "hs_fpmds*10, nothing*2")
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73
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74 (define_insn_reservation "hs_fp_sqrt" 17
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75 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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76 (eq_attr "type" "fpsqrts,fpsqrtd"))
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77 "hs_fpmds*15, nothing*2")
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78
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79 (define_insn_reservation "hs_imul" 17
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80 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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81 (eq_attr "type" "imul"))
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82 "hs_fpmds*15, nothing*2")
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