|
0
|
1 ;; Predicate definitions for SPARC.
|
|
|
2 ;; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
|
|
|
3 ;;
|
|
|
4 ;; This file is part of GCC.
|
|
|
5 ;;
|
|
|
6 ;; GCC is free software; you can redistribute it and/or modify
|
|
|
7 ;; it under the terms of the GNU General Public License as published by
|
|
|
8 ;; the Free Software Foundation; either version 3, or (at your option)
|
|
|
9 ;; any later version.
|
|
|
10 ;;
|
|
|
11 ;; GCC is distributed in the hope that it will be useful,
|
|
|
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
14 ;; GNU General Public License for more details.
|
|
|
15 ;;
|
|
|
16 ;; You should have received a copy of the GNU General Public License
|
|
|
17 ;; along with GCC; see the file COPYING3. If not see
|
|
|
18 ;; <http://www.gnu.org/licenses/>.
|
|
|
19
|
|
|
20 ;; Predicates for numerical constants.
|
|
|
21
|
|
|
22 ;; Return true if OP is the zero constant for MODE.
|
|
|
23 (define_predicate "const_zero_operand"
|
|
|
24 (and (match_code "const_int,const_double,const_vector")
|
|
|
25 (match_test "op == CONST0_RTX (mode)")))
|
|
|
26
|
|
|
27 ;; Return true if OP is the one constant for MODE.
|
|
|
28 (define_predicate "const_one_operand"
|
|
|
29 (and (match_code "const_int,const_double,const_vector")
|
|
|
30 (match_test "op == CONST1_RTX (mode)")))
|
|
|
31
|
|
|
32 ;; Return true if OP is the integer constant 4096.
|
|
|
33 (define_predicate "const_4096_operand"
|
|
|
34 (and (match_code "const_int")
|
|
|
35 (match_test "INTVAL (op) == 4096")))
|
|
|
36
|
|
|
37 ;; Return true if OP is a constant that is representable by a 13-bit
|
|
|
38 ;; signed field. This is an acceptable immediate operand for most
|
|
|
39 ;; 3-address instructions.
|
|
|
40 (define_predicate "small_int_operand"
|
|
|
41 (and (match_code "const_int")
|
|
|
42 (match_test "SPARC_SIMM13_P (INTVAL (op))")))
|
|
|
43
|
|
|
44 ;; Return true if OP is a constant operand for the umul instruction. That
|
|
|
45 ;; instruction sign-extends immediate values just like all other SPARC
|
|
|
46 ;; instructions, but interprets the extended result as an unsigned number.
|
|
|
47 (define_predicate "uns_small_int_operand"
|
|
|
48 (match_code "const_int,const_double")
|
|
|
49 {
|
|
|
50 #if HOST_BITS_PER_WIDE_INT == 32
|
|
|
51 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
|
|
|
52 || (GET_CODE (op) == CONST_DOUBLE
|
|
|
53 && CONST_DOUBLE_HIGH (op) == 0
|
|
|
54 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
|
|
|
55 #else
|
|
|
56 return (GET_CODE (op) == CONST_INT
|
|
|
57 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
|
|
|
58 || (INTVAL (op) >= 0xFFFFF000
|
|
|
59 && INTVAL (op) <= 0xFFFFFFFF)));
|
|
|
60 #endif
|
|
|
61 })
|
|
|
62
|
|
|
63 ;; Return true if OP is a constant that can be loaded by the sethi instruction.
|
|
|
64 ;; The first test avoids emitting sethi to load zero for example.
|
|
|
65 (define_predicate "const_high_operand"
|
|
|
66 (and (match_code "const_int")
|
|
|
67 (and (not (match_operand 0 "small_int_operand"))
|
|
|
68 (match_test "SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))"))))
|
|
|
69
|
|
|
70 ;; Return true if OP is a constant whose 1's complement can be loaded by the
|
|
|
71 ;; sethi instruction.
|
|
|
72 (define_predicate "const_compl_high_operand"
|
|
|
73 (and (match_code "const_int")
|
|
|
74 (and (not (match_operand 0 "small_int_operand"))
|
|
|
75 (match_test "SPARC_SETHI_P (~INTVAL (op) & GET_MODE_MASK (mode))"))))
|
|
|
76
|
|
|
77 ;; Return true if OP is a FP constant that needs to be loaded by the sethi/losum
|
|
|
78 ;; pair of instructions.
|
|
|
79 (define_predicate "fp_const_high_losum_operand"
|
|
|
80 (match_operand 0 "const_double_operand")
|
|
|
81 {
|
|
|
82 gcc_assert (mode == SFmode);
|
|
|
83 return fp_high_losum_p (op);
|
|
|
84 })
|
|
|
85
|
|
|
86 ;; Return true if OP is a const_double or const_vector.
|
|
|
87 (define_predicate "const_double_or_vector_operand"
|
|
|
88 (match_code "const_double,const_vector"))
|
|
|
89
|
|
|
90
|
|
|
91 ;; Predicates for symbolic constants.
|
|
|
92
|
|
|
93 ;; Return true if OP is either a symbol reference or a sum of a symbol
|
|
|
94 ;; reference and a constant.
|
|
|
95 (define_predicate "symbolic_operand"
|
|
|
96 (match_code "symbol_ref,label_ref,const")
|
|
|
97 {
|
|
|
98 enum machine_mode omode = GET_MODE (op);
|
|
|
99
|
|
|
100 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
|
|
|
101 return false;
|
|
|
102
|
|
|
103 switch (GET_CODE (op))
|
|
|
104 {
|
|
|
105 case SYMBOL_REF:
|
|
|
106 return !SYMBOL_REF_TLS_MODEL (op);
|
|
|
107
|
|
|
108 case LABEL_REF:
|
|
|
109 return true;
|
|
|
110
|
|
|
111 case CONST:
|
|
|
112 op = XEXP (op, 0);
|
|
|
113 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
|
|
|
114 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
|
|
|
115 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
|
|
|
116 && GET_CODE (XEXP (op, 1)) == CONST_INT);
|
|
|
117
|
|
|
118 default:
|
|
|
119 gcc_unreachable ();
|
|
|
120 }
|
|
|
121 })
|
|
|
122
|
|
|
123 ;; Return true if OP is a symbolic operand for the TLS Global Dynamic model.
|
|
|
124 (define_predicate "tgd_symbolic_operand"
|
|
|
125 (and (match_code "symbol_ref")
|
|
|
126 (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_GLOBAL_DYNAMIC")))
|
|
|
127
|
|
|
128 ;; Return true if OP is a symbolic operand for the TLS Local Dynamic model.
|
|
|
129 (define_predicate "tld_symbolic_operand"
|
|
|
130 (and (match_code "symbol_ref")
|
|
|
131 (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_DYNAMIC")))
|
|
|
132
|
|
|
133 ;; Return true if OP is a symbolic operand for the TLS Initial Exec model.
|
|
|
134 (define_predicate "tie_symbolic_operand"
|
|
|
135 (and (match_code "symbol_ref")
|
|
|
136 (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC")))
|
|
|
137
|
|
|
138 ;; Return true if OP is a symbolic operand for the TLS Local Exec model.
|
|
|
139 (define_predicate "tle_symbolic_operand"
|
|
|
140 (and (match_code "symbol_ref")
|
|
|
141 (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC")))
|
|
|
142
|
|
|
143 ;; Return true if the operand is an argument used in generating PIC references
|
|
|
144 ;; in either the medium/low or embedded medium/anywhere code models on V9.
|
|
|
145 ;; Check for (const (minus (symbol_ref:GOT)
|
|
|
146 ;; (const (minus (label) (pc)))))
|
|
|
147 (define_predicate "medium_pic_operand"
|
|
|
148 (match_code "const")
|
|
|
149 {
|
|
|
150 /* Check for (const (minus (symbol_ref:GOT)
|
|
|
151 (const (minus (label) (pc))))). */
|
|
|
152 op = XEXP (op, 0);
|
|
|
153 return GET_CODE (op) == MINUS
|
|
|
154 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
|
|
|
155 && GET_CODE (XEXP (op, 1)) == CONST
|
|
|
156 && GET_CODE (XEXP (XEXP (op, 1), 0)) == MINUS;
|
|
|
157 })
|
|
|
158
|
|
|
159 ;; Return true if OP is a LABEL_REF of mode MODE.
|
|
|
160 (define_predicate "label_ref_operand"
|
|
|
161 (and (match_code "label_ref")
|
|
|
162 (match_test "GET_MODE (op) == mode")))
|
|
|
163
|
|
|
164 ;; Return true if OP is a data segment reference. This includes the readonly
|
|
|
165 ;; data segment or, in other words, anything but the text segment.
|
|
|
166 ;; This is needed in the embedded medium/anywhere code model on V9. These
|
|
|
167 ;; values are accessed with EMBMEDANY_BASE_REG. */
|
|
|
168 (define_predicate "data_segment_operand"
|
|
|
169 (match_code "symbol_ref,plus,const")
|
|
|
170 {
|
|
|
171 switch (GET_CODE (op))
|
|
|
172 {
|
|
|
173 case SYMBOL_REF :
|
|
|
174 return ! SYMBOL_REF_FUNCTION_P (op);
|
|
|
175 case PLUS :
|
|
|
176 /* Assume canonical format of symbol + constant.
|
|
|
177 Fall through. */
|
|
|
178 case CONST :
|
|
|
179 return data_segment_operand (XEXP (op, 0), VOIDmode);
|
|
|
180 default :
|
|
|
181 gcc_unreachable ();
|
|
|
182 }
|
|
|
183 })
|
|
|
184
|
|
|
185 ;; Return true if OP is a text segment reference.
|
|
|
186 ;; This is needed in the embedded medium/anywhere code model on V9.
|
|
|
187 (define_predicate "text_segment_operand"
|
|
|
188 (match_code "label_ref,symbol_ref,plus,const")
|
|
|
189 {
|
|
|
190 switch (GET_CODE (op))
|
|
|
191 {
|
|
|
192 case LABEL_REF :
|
|
|
193 return true;
|
|
|
194 case SYMBOL_REF :
|
|
|
195 return SYMBOL_REF_FUNCTION_P (op);
|
|
|
196 case PLUS :
|
|
|
197 /* Assume canonical format of symbol + constant.
|
|
|
198 Fall through. */
|
|
|
199 case CONST :
|
|
|
200 return text_segment_operand (XEXP (op, 0), VOIDmode);
|
|
|
201 default :
|
|
|
202 gcc_unreachable ();
|
|
|
203 }
|
|
|
204 })
|
|
|
205
|
|
|
206
|
|
|
207 ;; Predicates for registers.
|
|
|
208
|
|
|
209 ;; Return true if OP is either the zero constant or a register.
|
|
|
210 (define_predicate "register_or_zero_operand"
|
|
|
211 (ior (match_operand 0 "register_operand")
|
|
|
212 (match_operand 0 "const_zero_operand")))
|
|
|
213
|
|
|
214 ;; Return true if OP is a register operand in a floating point register.
|
|
|
215 (define_predicate "fp_register_operand"
|
|
|
216 (match_operand 0 "register_operand")
|
|
|
217 {
|
|
|
218 if (GET_CODE (op) == SUBREG)
|
|
|
219 op = SUBREG_REG (op); /* Possibly a MEM */
|
|
|
220 return REG_P (op) && SPARC_FP_REG_P (REGNO (op));
|
|
|
221 })
|
|
|
222
|
|
|
223 ;; Return true if OP is an integer register.
|
|
|
224 (define_special_predicate "int_register_operand"
|
|
|
225 (ior (match_test "register_operand (op, SImode)")
|
|
|
226 (match_test "TARGET_ARCH64 && register_operand (op, DImode)")))
|
|
|
227
|
|
|
228 ;; Return true if OP is a floating point condition code register.
|
|
|
229 (define_predicate "fcc_register_operand"
|
|
|
230 (match_code "reg")
|
|
|
231 {
|
|
|
232 if (mode != VOIDmode && mode != GET_MODE (op))
|
|
|
233 return false;
|
|
|
234 if (mode == VOIDmode
|
|
|
235 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
|
|
|
236 return false;
|
|
|
237
|
|
|
238 #if 0 /* ??? 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
|
|
|
239 if (reg_renumber == 0)
|
|
|
240 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
|
|
|
241 return REGNO_OK_FOR_CCFP_P (REGNO (op));
|
|
|
242 #else
|
|
|
243 return ((unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG) < 4;
|
|
|
244 #endif
|
|
|
245 })
|
|
|
246
|
|
|
247 ;; Return true if OP is the floating point condition code register fcc0.
|
|
|
248 (define_predicate "fcc0_register_operand"
|
|
|
249 (match_code "reg")
|
|
|
250 {
|
|
|
251 if (mode != VOIDmode && mode != GET_MODE (op))
|
|
|
252 return false;
|
|
|
253 if (mode == VOIDmode
|
|
|
254 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
|
|
|
255 return false;
|
|
|
256
|
|
|
257 return REGNO (op) == SPARC_FCC_REG;
|
|
|
258 })
|
|
|
259
|
|
|
260 ;; Return true if OP is an integer or floating point condition code register.
|
|
|
261 (define_predicate "icc_or_fcc_register_operand"
|
|
|
262 (match_code "reg")
|
|
|
263 {
|
|
|
264 if (REGNO (op) == SPARC_ICC_REG)
|
|
|
265 {
|
|
|
266 if (mode != VOIDmode && mode != GET_MODE (op))
|
|
|
267 return false;
|
|
|
268 if (mode == VOIDmode
|
|
|
269 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
|
|
|
270 return false;
|
|
|
271
|
|
|
272 return true;
|
|
|
273 }
|
|
|
274
|
|
|
275 return fcc_register_operand (op, mode);
|
|
|
276 })
|
|
|
277
|
|
|
278
|
|
|
279 ;; Predicates for arithmetic instructions.
|
|
|
280
|
|
|
281 ;; Return true if OP is a register, or is a constant that is representable
|
|
|
282 ;; by a 13-bit signed field. This is an acceptable operand for most
|
|
|
283 ;; 3-address instructions.
|
|
|
284 (define_predicate "arith_operand"
|
|
|
285 (ior (match_operand 0 "register_operand")
|
|
|
286 (match_operand 0 "small_int_operand")))
|
|
|
287
|
|
|
288 ;; 64-bit: Same as above.
|
|
|
289 ;; 32-bit: Return true if OP is a register, or is a constant that is
|
|
|
290 ;; representable by a couple of 13-bit signed fields. This is an
|
|
|
291 ;; acceptable operand for most 3-address splitters.
|
|
|
292 (define_predicate "arith_double_operand"
|
|
|
293 (match_code "const_int,const_double,reg,subreg")
|
|
|
294 {
|
|
|
295 bool arith_simple_operand = arith_operand (op, mode);
|
|
|
296 HOST_WIDE_INT m1, m2;
|
|
|
297
|
|
|
298 if (TARGET_ARCH64 || arith_simple_operand)
|
|
|
299 return arith_simple_operand;
|
|
|
300
|
|
|
301 #if HOST_BITS_PER_WIDE_INT == 32
|
|
|
302 if (GET_CODE (op) != CONST_DOUBLE)
|
|
|
303 return false;
|
|
|
304 m1 = CONST_DOUBLE_LOW (op);
|
|
|
305 m2 = CONST_DOUBLE_HIGH (op);
|
|
|
306 #else
|
|
|
307 if (GET_CODE (op) != CONST_INT)
|
|
|
308 return false;
|
|
|
309 m1 = trunc_int_for_mode (INTVAL (op), SImode);
|
|
|
310 m2 = trunc_int_for_mode (INTVAL (op) >> 32, SImode);
|
|
|
311 #endif
|
|
|
312
|
|
|
313 return SPARC_SIMM13_P (m1) && SPARC_SIMM13_P (m2);
|
|
|
314 })
|
|
|
315
|
|
|
316 ;; Return true if OP is suitable as second operand for add/sub.
|
|
|
317 (define_predicate "arith_add_operand"
|
|
|
318 (ior (match_operand 0 "arith_operand")
|
|
|
319 (match_operand 0 "const_4096_operand")))
|
|
|
320
|
|
|
321 ;; Return true if OP is suitable as second double operand for add/sub.
|
|
|
322 (define_predicate "arith_double_add_operand"
|
|
|
323 (match_code "const_int,const_double,reg,subreg")
|
|
|
324 {
|
|
|
325 bool _arith_double_operand = arith_double_operand (op, mode);
|
|
|
326
|
|
|
327 if (_arith_double_operand)
|
|
|
328 return true;
|
|
|
329
|
|
|
330 return TARGET_ARCH64 && const_4096_operand (op, mode);
|
|
|
331 })
|
|
|
332
|
|
|
333 ;; Return true if OP is a register, or is a CONST_INT that can fit in a
|
|
|
334 ;; signed 10-bit immediate field. This is an acceptable SImode operand for
|
|
|
335 ;; the movrcc instructions.
|
|
|
336 (define_predicate "arith10_operand"
|
|
|
337 (ior (match_operand 0 "register_operand")
|
|
|
338 (and (match_code "const_int")
|
|
|
339 (match_test "SPARC_SIMM10_P (INTVAL (op))"))))
|
|
|
340
|
|
|
341 ;; Return true if OP is a register, or is a CONST_INT that can fit in a
|
|
|
342 ;; signed 11-bit immediate field. This is an acceptable SImode operand for
|
|
|
343 ;; the movcc instructions.
|
|
|
344 (define_predicate "arith11_operand"
|
|
|
345 (ior (match_operand 0 "register_operand")
|
|
|
346 (and (match_code "const_int")
|
|
|
347 (match_test "SPARC_SIMM11_P (INTVAL (op))"))))
|
|
|
348
|
|
|
349 ;; Return true if OP is a register or a constant for the umul instruction.
|
|
|
350 (define_predicate "uns_arith_operand"
|
|
|
351 (ior (match_operand 0 "register_operand")
|
|
|
352 (match_operand 0 "uns_small_int_operand")))
|
|
|
353
|
|
|
354
|
|
|
355 ;; Predicates for miscellaneous instructions.
|
|
|
356
|
|
|
357 ;; Return true if OP is valid for the lhs of a comparison insn.
|
|
|
358 (define_predicate "compare_operand"
|
|
|
359 (match_code "reg,subreg,zero_extract")
|
|
|
360 {
|
|
|
361 if (GET_CODE (op) == ZERO_EXTRACT)
|
|
|
362 return (register_operand (XEXP (op, 0), mode)
|
|
|
363 && small_int_operand (XEXP (op, 1), mode)
|
|
|
364 && small_int_operand (XEXP (op, 2), mode)
|
|
|
365 /* This matches cmp_zero_extract. */
|
|
|
366 && ((mode == SImode
|
|
|
367 && INTVAL (XEXP (op, 2)) > 19)
|
|
|
368 /* This matches cmp_zero_extract_sp64. */
|
|
|
369 || (TARGET_ARCH64
|
|
|
370 && mode == DImode
|
|
|
371 && INTVAL (XEXP (op, 2)) > 51)));
|
|
|
372 else
|
|
|
373 return register_operand (op, mode);
|
|
|
374 })
|
|
|
375
|
|
|
376 ;; Return true if OP is a valid operand for the source of a move insn.
|
|
|
377 (define_predicate "input_operand"
|
|
|
378 (match_code "const_int,const_double,const_vector,reg,subreg,mem")
|
|
|
379 {
|
|
|
380 enum mode_class mclass;
|
|
|
381
|
|
|
382 /* If both modes are non-void they must be the same. */
|
|
|
383 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
|
|
|
384 return false;
|
|
|
385
|
|
|
386 mclass = GET_MODE_CLASS (mode);
|
|
|
387
|
|
|
388 /* Allow any 1-instruction integer constant. */
|
|
|
389 if (mclass == MODE_INT
|
|
|
390 && (small_int_operand (op, mode) || const_high_operand (op, mode)))
|
|
|
391 return true;
|
|
|
392
|
|
|
393 /* If 32-bit mode and this is a DImode constant, allow it
|
|
|
394 so that the splits can be generated. */
|
|
|
395 if (TARGET_ARCH32
|
|
|
396 && mode == DImode
|
|
|
397 && (GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT))
|
|
|
398 return true;
|
|
|
399
|
|
|
400 if ((mclass == MODE_FLOAT && GET_CODE (op) == CONST_DOUBLE)
|
|
|
401 || (mclass == MODE_VECTOR_INT && GET_CODE (op) == CONST_VECTOR))
|
|
|
402 return true;
|
|
|
403
|
|
|
404 if (register_operand (op, mode))
|
|
|
405 return true;
|
|
|
406
|
|
|
407 /* If this is a SUBREG, look inside so that we handle paradoxical ones. */
|
|
|
408 if (GET_CODE (op) == SUBREG)
|
|
|
409 op = SUBREG_REG (op);
|
|
|
410
|
|
|
411 /* Check for valid MEM forms. */
|
|
|
412 if (GET_CODE (op) == MEM)
|
|
|
413 return memory_address_p (mode, XEXP (op, 0));
|
|
|
414
|
|
|
415 return false;
|
|
|
416 })
|
|
|
417
|
|
|
418 ;; Return true if OP is an address suitable for a call insn.
|
|
|
419 ;; Call insn on SPARC can take a PC-relative constant address
|
|
|
420 ;; or any regular memory address.
|
|
|
421 (define_predicate "call_address_operand"
|
|
|
422 (ior (match_operand 0 "symbolic_operand")
|
|
|
423 (match_test "memory_address_p (Pmode, op)")))
|
|
|
424
|
|
|
425 ;; Return true if OP is an operand suitable for a call insn.
|
|
|
426 (define_predicate "call_operand"
|
|
|
427 (and (match_code "mem")
|
|
|
428 (match_test "call_address_operand (XEXP (op, 0), mode)")))
|
|
|
429
|
|
|
430
|
|
|
431 ;; Predicates for operators.
|
|
|
432
|
|
|
433 ;; Return true if OP is a comparison operator. This allows the use of
|
|
|
434 ;; MATCH_OPERATOR to recognize all the branch insns.
|
|
|
435 (define_predicate "noov_compare_operator"
|
|
|
436 (match_code "ne,eq,ge,gt,le,lt,geu,gtu,leu,ltu")
|
|
|
437 {
|
|
|
438 enum rtx_code code = GET_CODE (op);
|
|
|
439 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
|
|
|
440 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
|
|
|
441 /* These are the only branches which work with CC_NOOVmode. */
|
|
|
442 return (code == EQ || code == NE || code == GE || code == LT);
|
|
|
443 return true;
|
|
|
444 })
|
|
|
445
|
|
|
446 ;; Return true if OP is a 64-bit comparison operator. This allows the use of
|
|
|
447 ;; MATCH_OPERATOR to recognize all the branch insns.
|
|
|
448 (define_predicate "noov_compare64_operator"
|
|
|
449 (and (match_code "ne,eq,ge,gt,le,lt,geu,gtu,leu,ltu")
|
|
|
450 (match_test "TARGET_V9"))
|
|
|
451 {
|
|
|
452 enum rtx_code code = GET_CODE (op);
|
|
|
453 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
|
|
|
454 /* These are the only branches which work with CCX_NOOVmode. */
|
|
|
455 return (code == EQ || code == NE || code == GE || code == LT);
|
|
|
456 return (GET_MODE (XEXP (op, 0)) == CCXmode);
|
|
|
457 })
|
|
|
458
|
|
|
459 ;; Return true if OP is a comparison operator suitable for use in V9
|
|
|
460 ;; conditional move or branch on register contents instructions.
|
|
|
461 (define_predicate "v9_register_compare_operator"
|
|
|
462 (match_code "eq,ne,ge,lt,le,gt"))
|
|
|
463
|
|
|
464 ;; Return true if OP is an operator which can set the condition codes
|
|
|
465 ;; explicitly. We do not include PLUS and MINUS because these
|
|
|
466 ;; require CC_NOOVmode, which we handle explicitly.
|
|
|
467 (define_predicate "cc_arith_operator"
|
|
|
468 (match_code "and,ior,xor"))
|
|
|
469
|
|
|
470 ;; Return true if OP is an operator which can bitwise complement its
|
|
|
471 ;; second operand and set the condition codes explicitly.
|
|
|
472 ;; XOR is not here because combine canonicalizes (xor (not ...) ...)
|
|
|
473 ;; and (xor ... (not ...)) to (not (xor ...)). */
|
|
|
474 (define_predicate "cc_arith_not_operator"
|
|
|
475 (match_code "and,ior"))
|
|
|
476
|
|
|
477 ;; Return true if OP is memory operand with just [%reg] addressing mode.
|
|
|
478 (define_predicate "memory_reg_operand"
|
|
|
479 (and (match_code "mem")
|
|
|
480 (and (match_operand 0 "memory_operand")
|
|
|
481 (match_test "REG_P (XEXP (op, 0))"))))
|
