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1 ;; Scheduling description for UltraSPARC-III.
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2 ;; Copyright (C) 2002, 2004, 2007 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; UltraSPARC-III is a quad-issue processor.
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21 ;;
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22 ;; It is also a much simpler beast than Ultra-I/II, no silly
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23 ;; slotting rules and both integer units are fully symmetric.
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24 ;; It does still have single-issue instructions though.
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25
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26 (define_automaton "ultrasparc3_0,ultrasparc3_1")
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27
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28 (define_cpu_unit "us3_ms,us3_br,us3_fpm" "ultrasparc3_0")
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29 (define_cpu_unit "us3_a0,us3_a1,us3_slot0,\
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30 us3_slot1,us3_slot2,us3_slot3,us3_fpa" "ultrasparc3_1")
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31 (define_cpu_unit "us3_load_writeback" "ultrasparc3_1")
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32
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33 (define_reservation "us3_slotany" "(us3_slot0 | us3_slot1 | us3_slot2 | us3_slot3)")
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34 (define_reservation "us3_single_issue" "us3_slot0 + us3_slot1 + us3_slot2 + us3_slot3")
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35 (define_reservation "us3_ax" "(us3_a0 | us3_a1)")
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36
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37 (define_insn_reservation "us3_single" 1
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38 (and (eq_attr "cpu" "ultrasparc3")
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39 (eq_attr "type" "multi,savew,flushw,iflush,trap"))
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40 "us3_single_issue")
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41
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42 (define_insn_reservation "us3_integer" 1
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43 (and (eq_attr "cpu" "ultrasparc3")
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44 (eq_attr "type" "ialu,shift,compare"))
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45 "us3_ax + us3_slotany")
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46
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47 (define_insn_reservation "us3_ialuX" 5
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48 (and (eq_attr "cpu" "ultrasparc3")
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49 (eq_attr "type" "ialu,shift,compare"))
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50 "us3_single_issue*4, nothing")
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51
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52 (define_insn_reservation "us3_cmove" 2
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53 (and (eq_attr "cpu" "ultrasparc3")
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54 (eq_attr "type" "cmove"))
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55 "us3_ms + us3_br + us3_slotany, nothing")
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56
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57 ;; ??? Not entirely accurate.
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58 ;; ??? It can run from 6 to 9 cycles. The first cycle the MS pipe
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59 ;; ??? is needed, and the instruction group is broken right after
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60 ;; ??? the imul. Then 'helper' instructions are generated to perform
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61 ;; ??? each further stage of the multiplication, each such 'helper' is
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62 ;; ??? single group. So, the reservation aspect is represented accurately
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63 ;; ??? here, but the variable cycles are not.
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64 ;; ??? Currently I have no idea how to determine the variability, but once
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65 ;; ??? known we can simply add a define_bypass or similar to model it.
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66 (define_insn_reservation "us3_imul" 7
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67 (and (eq_attr "cpu" "ultrasparc3")
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68 (eq_attr "type" "imul"))
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69 "us3_ms + us3_slotany, us3_single_issue*4, nothing*2")
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70
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71 (define_insn_reservation "us3_idiv" 72
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72 (and (eq_attr "cpu" "ultrasparc3")
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73 (eq_attr "type" "idiv"))
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74 "us3_ms + us3_slotany, us3_single_issue*69, nothing*2")
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75
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76 ;; UltraSPARC-III has a similar load delay as UltraSPARC-I/II except
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77 ;; that all loads except 32-bit/64-bit unsigned loads take the extra
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78 ;; delay for sign/zero extension.
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79 (define_insn_reservation "us3_2cycle_load" 2
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80 (and (eq_attr "cpu" "ultrasparc3")
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81 (and (eq_attr "type" "load,fpload")
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82 (eq_attr "us3load_type" "2cycle")))
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83 "us3_ms + us3_slotany, us3_load_writeback")
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84
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85 (define_insn_reservation "us3_load_delayed" 3
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86 (and (eq_attr "cpu" "ultrasparc3")
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87 (and (eq_attr "type" "load,sload")
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88 (eq_attr "us3load_type" "3cycle")))
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89 "us3_ms + us3_slotany, nothing, us3_load_writeback")
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90
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91 (define_insn_reservation "us3_store" 1
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92 (and (eq_attr "cpu" "ultrasparc3")
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93 (eq_attr "type" "store,fpstore"))
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94 "us3_ms + us3_slotany")
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95
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96 (define_insn_reservation "us3_branch" 1
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97 (and (eq_attr "cpu" "ultrasparc3")
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98 (eq_attr "type" "branch"))
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99 "us3_br + us3_slotany")
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100
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101 (define_insn_reservation "us3_call_jmpl" 1
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102 (and (eq_attr "cpu" "ultrasparc3")
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103 (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch"))
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104 "us3_br + us3_ms + us3_slotany")
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105
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106 (define_insn_reservation "us3_fmov" 3
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107 (and (eq_attr "cpu" "ultrasparc3")
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108 (eq_attr "type" "fpmove"))
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109 "us3_fpa + us3_slotany, nothing*2")
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110
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111 (define_insn_reservation "us3_fcmov" 3
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112 (and (eq_attr "cpu" "ultrasparc3")
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113 (eq_attr "type" "fpcmove"))
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114 "us3_fpa + us3_br + us3_slotany, nothing*2")
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115
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116 (define_insn_reservation "us3_fcrmov" 3
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117 (and (eq_attr "cpu" "ultrasparc3")
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118 (eq_attr "type" "fpcrmove"))
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119 "us3_fpa + us3_ms + us3_slotany, nothing*2")
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120
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121 (define_insn_reservation "us3_faddsub" 4
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122 (and (eq_attr "cpu" "ultrasparc3")
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123 (eq_attr "type" "fp"))
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124 "us3_fpa + us3_slotany, nothing*3")
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125
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126 (define_insn_reservation "us3_fpcmp" 5
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127 (and (eq_attr "cpu" "ultrasparc3")
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128 (eq_attr "type" "fpcmp"))
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129 "us3_fpa + us3_slotany, nothing*4")
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130
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131 (define_insn_reservation "us3_fmult" 4
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132 (and (eq_attr "cpu" "ultrasparc3")
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133 (eq_attr "type" "fpmul"))
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134 "us3_fpm + us3_slotany, nothing*3")
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135
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136 (define_insn_reservation "us3_fdivs" 17
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137 (and (eq_attr "cpu" "ultrasparc3")
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138 (eq_attr "type" "fpdivs"))
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139 "(us3_fpm + us3_slotany), us3_fpm*14, nothing*2")
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140
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141 (define_insn_reservation "us3_fsqrts" 20
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142 (and (eq_attr "cpu" "ultrasparc3")
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143 (eq_attr "type" "fpsqrts"))
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144 "(us3_fpm + us3_slotany), us3_fpm*17, nothing*2")
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145
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146 (define_insn_reservation "us3_fdivd" 20
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147 (and (eq_attr "cpu" "ultrasparc3")
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148 (eq_attr "type" "fpdivd"))
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149 "(us3_fpm + us3_slotany), us3_fpm*17, nothing*2")
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150
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151 (define_insn_reservation "us3_fsqrtd" 29
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152 (and (eq_attr "cpu" "ultrasparc3")
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153 (eq_attr "type" "fpsqrtd"))
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154 "(us3_fpm + us3_slotany), us3_fpm*26, nothing*2")
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155
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156 ;; Any store may multi issue with the insn creating the source
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157 ;; data as long as that creating insn is not an FPU div/sqrt.
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158 ;; We need a special guard function because this bypass does
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159 ;; not apply to the address inputs of the store.
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160 (define_bypass 0 "us3_integer,us3_faddsub,us3_fmov,us3_fcmov,us3_fmult" "us3_store"
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161 "store_data_bypass_p")
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162
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163 ;; An integer branch may execute in the same cycle as the compare
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164 ;; creating the condition codes.
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165 (define_bypass 0 "us3_integer" "us3_branch")
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166
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167 ;; If FMOVfcc is user of FPCMP, latency is only 1 cycle.
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168 (define_bypass 1 "us3_fpcmp" "us3_fcmov")
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169
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170 ;; VIS scheduling
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171 (define_insn_reservation "us3_fga"
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172 3
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173 (and (eq_attr "cpu" "ultrasparc3")
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174 (eq_attr "type" "fga"))
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175 "us3_fpa + us3_slotany, nothing*2")
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176
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177 (define_insn_reservation "us3_fgm"
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178 4
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179 (and (eq_attr "cpu" "ultrasparc3")
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180 (eq_attr "type" "fgm_pack,fgm_mul,fgm_cmp"))
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181 "us3_fpm + us3_slotany, nothing*3")
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182
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183 (define_insn_reservation "us3_pdist"
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184 4
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185 (and (eq_attr "cpu" "ultrasparc3")
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186 (eq_attr "type" "fgm_pdist"))
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187 "us3_fpm + us3_slotany, nothing*3")
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188
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189 (define_bypass 1 "us3_pdist" "us3_pdist")
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