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1 /* Copyright (C) 2006, 2008, 2009 Free Software Foundation, Inc.
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2
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3 This file is free software; you can redistribute it and/or modify it under
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4 the terms of the GNU General Public License as published by the Free
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5 Software Foundation; either version 3 of the License, or (at your option)
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6 any later version.
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7
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8 This file is distributed in the hope that it will be useful, but WITHOUT
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9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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11 for more details.
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12
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13 Under Section 7 of GPL version 3, you are granted additional
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14 permissions described in the GCC Runtime Library Exception, version
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15 3.1, as published by the Free Software Foundation.
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16
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17 You should have received a copy of the GNU General Public License and
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18 a copy of the GCC Runtime Library Exception along with this program;
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19 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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20 <http://www.gnu.org/licenses/>. */
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21
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22 #ifndef __SPU_MFCIO_H__
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23 #define __SPU_MFCIO_H__ 1
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24
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25 #include <spu_intrinsics.h>
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26 #ifdef __IN_LIBGCC2
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27 typedef unsigned long long uint64_t;
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28 #else
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29 #include <stdint.h>
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30 #endif
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31
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32 #ifdef __cplusplus
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33 extern "C" {
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34 #endif
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35
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36
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37 /****************************************************************/
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38 /* DMA list element structure*/
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39 /****************************************************************/
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40
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41 #ifdef __GNUC__
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42 __extension__
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43 #endif
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44 typedef struct mfc_list_element {
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45 uint64_t notify : 1; /** Stall-and-notify bit */
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46 uint64_t reserved : 16;
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47 uint64_t size : 15; /** Transfer size */
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48 uint64_t eal : 32; /** Lower word of effective address */
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49 } mfc_list_element_t;
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50
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51 /****************************************************************/
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52 /* DMA max/min size definitions. */
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53 /****************************************************************/
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54
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55 #define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
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56 #define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
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57
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58 #define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
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59 #define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
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60
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61 #define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
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62 #define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
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63
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64 #define MFC_MIN_DMA_LIST_ELEMENTS 1
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65 #define MFC_MAX_DMA_LIST_ELEMENTS 2048
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66
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67 #define MFC_MIN_DMA_LIST_SIZE (MFC_MIN_DMA_LIST_ELEMENTS << 3) /* 8 bytes */
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68 #define MFC_MAX_DMA_LIST_SIZE (MFC_MAX_DMA_LIST_ELEMENTS << 3) /* 16K bytes */
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69
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70 /****************************************************************/
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71 /* MFC DMA command modifiers to identify classes of operations. */
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72 /****************************************************************/
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73
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74 /* Note: These commands modifier may be used in conjunction with the base
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75 command types (i.e. MFC_PUT_CMD, MFC_GET_CMD, and MFC_SNDSIG_CMD)
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76 to construct the various command permutations. */
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77
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78 #define MFC_BARRIER_ENABLE 0x0001
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79 #define MFC_FENCE_ENABLE 0x0002
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80 #define MFC_LIST_ENABLE 0x0004
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81 #define MFC_RESULT_ENABLE 0x0010
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82
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83 /****************************************************************/
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84 /* MFC DMA Put Commands */
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85 /****************************************************************/
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86
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87 #define MFC_PUT_CMD 0x0020
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88 #define MFC_PUTB_CMD (MFC_PUT_CMD | MFC_BARRIER_ENABLE)
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89 #define MFC_PUTF_CMD (MFC_PUT_CMD | MFC_FENCE_ENABLE)
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90 #define MFC_PUTL_CMD (MFC_PUT_CMD | MFC_LIST_ENABLE)
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91 #define MFC_PUTLB_CMD (MFC_PUTL_CMD | MFC_BARRIER_ENABLE)
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92 #define MFC_PUTLF_CMD (MFC_PUTL_CMD | MFC_FENCE_ENABLE)
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93
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94 #define MFC_PUTR_CMD (MFC_PUT_CMD | MFC_RESULT_ENABLE)
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95 #define MFC_PUTRB_CMD (MFC_PUTR_CMD | MFC_BARRIER_ENABLE)
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96 #define MFC_PUTRF_CMD (MFC_PUTR_CMD | MFC_FENCE_ENABLE)
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97 #define MFC_PUTRL_CMD (MFC_PUTR_CMD | MFC_LIST_ENABLE)
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98 #define MFC_PUTRLB_CMD (MFC_PUTRL_CMD | MFC_BARRIER_ENABLE)
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99 #define MFC_PUTRLF_CMD (MFC_PUTRL_CMD | MFC_FENCE_ENABLE)
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100
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101 /****************************************************************/
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102 /* MFC DMA Get Commands */
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103 /****************************************************************/
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104
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105 #define MFC_GET_CMD 0x0040
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106 #define MFC_GETB_CMD (MFC_GET_CMD | MFC_BARRIER_ENABLE)
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107 #define MFC_GETF_CMD (MFC_GET_CMD | MFC_FENCE_ENABLE)
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108 #define MFC_GETL_CMD (MFC_GET_CMD | MFC_LIST_ENABLE)
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109 #define MFC_GETLB_CMD (MFC_GETL_CMD | MFC_BARRIER_ENABLE)
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110 #define MFC_GETLF_CMD (MFC_GETL_CMD | MFC_FENCE_ENABLE)
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111
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112 /****************************************************************/
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113 /* MFC Synchronization Commands */
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114 /****************************************************************/
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115
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116 #define MFC_SNDSIG_CMD 0x00A0
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117 #define MFC_SNDSIGB_CMD (MFC_SNDSIG_CMD | MFC_BARRIER_ENABLE)
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118 #define MFC_SNDSIGF_CMD (MFC_SNDSIG_CMD | MFC_FENCE_ENABLE)
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119 #define MFC_BARRIER_CMD 0x00C0
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120 #define MFC_EIEIO_CMD 0x00C8
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121 #define MFC_SYNC_CMD 0x00CC
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122
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123 /****************************************************************/
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124 /* MFC Atomic Commands */
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125 /****************************************************************/
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126
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127 #define MFC_GETLLAR_CMD 0x00D0
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128 #define MFC_PUTLLC_CMD 0x00B4
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129 #define MFC_PUTLLUC_CMD 0x00B0
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130 #define MFC_PUTQLLUC_CMD 0x00B8
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131
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132 /****************************************************************/
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133 /* MFC SL1 Storage Control Commands */
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134 /****************************************************************/
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135
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136 #define MFC_SDCRT_CMD 0x0080
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137 #define MFC_SDCRTST_CMD 0x0081
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138 #define MFC_SDCRZ_CMD 0x0089
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139 #define MFC_SDCRST_CMD 0x008D
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140 #define MFC_SDCRF_CMD 0x008F
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141
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142 /****************************************************************/
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143 /* Channel Defines */
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144 /****************************************************************/
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145
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146 /* Events Defines for channels
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147 * 0 (SPU_RdEventStat),
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148 * 1 (SPU_WrEventMask), and
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149 * 2 (SPU_WrEventAck).
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150 */
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151 #define MFC_TAG_STATUS_UPDATE_EVENT 0x00000001
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152 #define MFC_LIST_STALL_NOTIFY_EVENT 0x00000002
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153 #define MFC_COMMAND_QUEUE_AVAILABLE_EVENT 0x00000008
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154 #define MFC_IN_MBOX_AVAILABLE_EVENT 0x00000010
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155 #define MFC_DECREMENTER_EVENT 0x00000020
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156 #define MFC_OUT_INTR_MBOX_AVAILABLE_EVENT 0x00000040
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157 #define MFC_OUT_MBOX_AVAILABLE_EVENT 0x00000080
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158 #define MFC_SIGNAL_NOTIFY_2_EVENT 0x00000100
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159 #define MFC_SIGNAL_NOTIFY_1_EVENT 0x00000200
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160 #define MFC_LLR_LOST_EVENT 0x00000400
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161 #define MFC_PRIV_ATTN_EVENT 0x00000800
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162 #define MFC_MULTI_SRC_SYNC_EVENT 0x00001000
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163
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164 /* Tag Status Update defines for channel 23 (MFC_WrTagUpdate) */
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165 #define MFC_TAG_UPDATE_IMMEDIATE 0x0
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166 #define MFC_TAG_UPDATE_ANY 0x1
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167 #define MFC_TAG_UPDATE_ALL 0x2
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168
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169 /* Atomic Command Status defines for channel 27 (MFC_RdAtomicStat) */
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170 #define MFC_PUTLLC_STATUS 0x00000001
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171 #define MFC_PUTLLUC_STATUS 0x00000002
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172 #define MFC_GETLLAR_STATUS 0x00000004
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173
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174
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175 /****************************************************************/
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176 /* Definitions for constructing a 32-bit command word */
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177 /* including the transfer and replacement class id and the */
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178 /* command opcode. */
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179 /****************************************************************/
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180 #define MFC_CMD_WORD(_tid, _rid, _cmd) (((_tid)<<24)|((_rid)<<16)|(_cmd))
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181
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182
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183 /* Addressing Utilities */
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184 #define mfc_ea2h(ea) (unsigned int)((unsigned long long)(ea)>>32)
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185 #define mfc_ea2l(ea) (unsigned int)(ea)
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186 #define mfc_hl2ea(h,l) si_to_ullong(si_selb(si_from_uint(h),\
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187 si_rotqbyi(si_from_uint(l), -4),\
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188 si_fsmbi(0x0f0f)))
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189 #define mfc_ceil128(v) (((v) + 127) & ~127)
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190
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191 /* MFC DMA */
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192 #define mfc_put( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUT_CMD))
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193 #define mfc_putf( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTF_CMD))
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194 #define mfc_putb( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTB_CMD))
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195 #define mfc_get( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GET_CMD))
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196 #define mfc_getf( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETF_CMD))
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197 #define mfc_getb( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETB_CMD))
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198
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199 /* MFC list DMA */
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200 #define mfc_putl( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTL_CMD))
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201 #define mfc_putlf( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTLF_CMD))
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202 #define mfc_putlb( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTLB_CMD))
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203 #define mfc_getl( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETL_CMD))
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204 #define mfc_getlf( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETLF_CMD))
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205 #define mfc_getlb( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETLB_CMD))
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206
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207 /* MFC Atomic Update DMA */
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208 #define mfc_getllar( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_GETLLAR_CMD))
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209 #define mfc_putllc( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_PUTLLC_CMD))
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210 #define mfc_putlluc( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_PUTLLUC_CMD))
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211 #define mfc_putqlluc(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128,tag,MFC_CMD_WORD(tid,rid,MFC_PUTQLLUC_CMD))
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212
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213 /* MFC Synchronization Commands */
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214 #define mfc_sndsig( ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIG_CMD))
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215 #define mfc_sndsigb(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIGB_CMD))
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216 #define mfc_sndsigf(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIGF_CMD))
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217 #define mfc_barrier(tag) spu_mfcdma32(0,0,0,tag,MFC_BARRIER_CMD)
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218 #define mfc_eieio(tag,tid,rid) spu_mfcdma32(0,0,0,tag,MFC_CMD_WORD(tid,rid,MFC_EIEIO_CMD))
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219 #define mfc_sync(tag) spu_mfcdma32(0,0,0,tag,MFC_SYNC_CMD)
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220
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221 /* MFC SL1 Storage Control Commands */
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222 #define mfc_sdcrt( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRT_CMD))
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223 #define mfc_sdcrtst(ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRTST_CMD))
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224 #define mfc_sdcrz( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRZ_CMD))
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225 #define mfc_sdcrst( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRST_CMD))
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226 #define mfc_sdcrf( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRF_CMD))
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227
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228 /* DMA Queue */
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229 #define mfc_stat_cmd_queue() spu_readchcnt(MFC_Cmd)
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230
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231 /* MFC Tag-Status */
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232 #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
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233 #define mfc_read_tag_mask() spu_readch(MFC_RdTagMask)
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234
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235 #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
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236 #define mfc_write_tag_update_immediate() mfc_write_tag_update(MFC_TAG_UPDATE_IMMEDIATE)
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237 #define mfc_write_tag_update_any() mfc_write_tag_update(MFC_TAG_UPDATE_ANY)
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238 #define mfc_write_tag_update_all() mfc_write_tag_update(MFC_TAG_UPDATE_ALL)
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239 #define mfc_stat_tag_update() spu_readchcnt(MFC_WrTagUpdate)
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240
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241 #define mfc_read_tag_status() spu_readch(MFC_RdTagStat)
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242 #define mfc_read_tag_status_immediate() (mfc_write_tag_update_immediate(), mfc_read_tag_status())
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243 #define mfc_read_tag_status_any() (mfc_write_tag_update_any(), mfc_read_tag_status())
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244 #define mfc_read_tag_status_all() (mfc_write_tag_update_all(), mfc_read_tag_status())
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245 #define mfc_stat_tag_status() spu_readchcnt(MFC_RdTagStat)
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246
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247 /* MFC List Stall-and-Notify Tag */
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248 #define mfc_read_list_stall_status() spu_readch(MFC_RdListStallStat)
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249 #define mfc_stat_list_stall_status() spu_readchcnt(MFC_RdListStallStat)
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250 #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
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251
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252 /* Atomic DMA */
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253 #define mfc_read_atomic_status() spu_readch(MFC_RdAtomicStat)
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254 #define mfc_stat_atomic_status() spu_readchcnt(MFC_RdAtomicStat)
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255
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256 /* MFC Multi-source Synchronization */
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257 #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
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258 #define mfc_stat_multi_src_sync_request() spu_readchcnt(MFC_WrMSSyncReq)
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259
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260 /* SPU Signal */
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261 #define spu_read_signal1() spu_readch(SPU_RdSigNotify1)
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262 #define spu_stat_signal1() spu_readchcnt(SPU_RdSigNotify1)
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263 #define spu_read_signal2() spu_readch(SPU_RdSigNotify2)
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264 #define spu_stat_signal2() spu_readchcnt(SPU_RdSigNotify2)
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265
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266 /* SPU/PPE Mailbox */
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267 #define spu_read_in_mbox() spu_readch(SPU_RdInMbox)
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268 #define spu_stat_in_mbox() spu_readchcnt(SPU_RdInMbox)
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269 #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
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270 #define spu_stat_out_mbox() spu_readchcnt(SPU_WrOutMbox)
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271 #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
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272 #define spu_stat_out_intr_mbox() spu_readchcnt(SPU_WrOutIntrMbox)
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273
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274 /* SPU Decrementer */
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275 #define spu_read_decrementer() spu_readch(SPU_RdDec)
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276 #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
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277
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278 /* SPU Event */
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279 #define spu_read_event_status() spu_readch(SPU_RdEventStat)
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280 #define spu_stat_event_status() spu_readchcnt(SPU_RdEventStat)
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281 #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
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282 #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
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283 #define spu_read_event_mask() spu_readch(SPU_RdEventMask)
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284
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285 /* SPU State Management */
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286 #define spu_read_machine_status() spu_readch(SPU_RdMachStat)
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287 #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
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288 #define spu_read_srr0() spu_readch(SPU_RdSRR0)
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289
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290 /* Interrupt-Safe Critical Sections */
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291
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292 static __inline__ unsigned int mfc_begin_critical_section (void)
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293 __attribute__ ((__always_inline__));
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294
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295 static __inline__ unsigned int
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296 mfc_begin_critical_section (void)
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297 {
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298 #ifdef SPU_MFCIO_INTERRUPT_SAFE
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299 unsigned int __status = spu_read_machine_status ();
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300 spu_idisable ();
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301 return __status;
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302 #else
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303 return 0;
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304 #endif
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305 }
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306
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307 static __inline__ void mfc_end_critical_section (unsigned int)
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308 __attribute__ ((__always_inline__));
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309
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310 static __inline__ void
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311 mfc_end_critical_section (unsigned int __status __attribute__ ((__unused__)))
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312 {
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313 #ifdef SPU_MFCIO_INTERRUPT_SAFE
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314 if (__status & 1)
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315 spu_ienable ();
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316 #endif
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317 }
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318
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319 /* MFC Tag Manager */
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320
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321 #define MFC_TAG_INVALID 0xFFFFFFFF
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322 #define MFC_TAG_VALID 0x00000000
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323
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324 #define mfc_tag_reserve() \
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325 __mfc_tag_reserve()
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326 #define mfc_tag_release(tag) \
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327 __mfc_tag_release((tag))
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328 #define mfc_multi_tag_reserve(nr_tags) \
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329 __mfc_multi_tag_reserve((nr_tags))
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330 #define mfc_multi_tag_release(tag, nr_tags) \
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331 __mfc_multi_tag_release((tag),(nr_tags))
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332
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333 extern unsigned int __mfc_tag_reserve (void);
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334 extern unsigned int __mfc_tag_release (unsigned int);
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335 extern unsigned int __mfc_multi_tag_reserve (unsigned int);
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336 extern unsigned int __mfc_multi_tag_release (unsigned int, unsigned int);
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337
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338 #ifdef __cplusplus
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339 }
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340 #endif
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341
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342 #endif /* __SPU_MFCIO_H__ */
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