Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/m68hc11/m68hc11.h @ 63:b7f97abdc517 gcc-4.6-20100522
update gcc from gcc-4.5.0 to gcc-4.6
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Mon, 24 May 2010 12:47:05 +0900 |
| parents | 77e2b8dfacca |
| children | f6334be47118 |
| rev | line source |
|---|---|
| 0 | 1 /* Definitions of target machine for GNU compiler. |
| 2 Motorola 68HC11 and 68HC12. | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
3 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 |
| 0 | 4 Free Software Foundation, Inc. |
| 5 Contributed by Stephane Carrez (stcarrez@nerim.fr) | |
| 6 | |
| 7 This file is part of GCC. | |
| 8 | |
| 9 GCC is free software; you can redistribute it and/or modify | |
| 10 it under the terms of the GNU General Public License as published by | |
| 11 the Free Software Foundation; either version 3, or (at your option) | |
| 12 any later version. | |
| 13 | |
| 14 GCC is distributed in the hope that it will be useful, | |
| 15 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 GNU General Public License for more details. | |
| 18 | |
| 19 You should have received a copy of the GNU General Public License | |
| 20 along with GCC; see the file COPYING3. If not see | |
| 21 <http://www.gnu.org/licenses/>. | |
| 22 | |
| 23 Note: | |
| 24 A first 68HC11 port was made by Otto Lind (otto@coactive.com) | |
| 25 on gcc 2.6.3. I have used it as a starting point for this port. | |
| 26 However, this new port is a complete re-write. Its internal | |
| 27 design is completely different. The generated code is not | |
| 28 compatible with the gcc 2.6.3 port. | |
| 29 | |
| 30 The gcc 2.6.3 port is available at: | |
| 31 | |
| 32 ftp.unina.it/pub/electronics/motorola/68hc11/gcc/gcc-6811-fsf.tar.gz | |
| 33 | |
| 34 */ | |
| 35 | |
| 36 /***************************************************************************** | |
| 37 ** | |
| 38 ** Controlling the Compilation Driver, `gcc' | |
| 39 ** | |
| 40 *****************************************************************************/ | |
| 41 | |
| 42 #undef ENDFILE_SPEC | |
| 43 | |
| 44 /* Compile and assemble for a 68hc11 unless there is a -m68hc12 option. */ | |
| 45 #ifndef ASM_SPEC | |
| 46 #define ASM_SPEC \ | |
| 47 "%{m68hc12:-m68hc12}" \ | |
| 48 "%{m68hcs12:-m68hcs12}" \ | |
| 49 "%{!m68hc12:%{!m68hcs12:-m68hc11}} " \ | |
| 50 "%{mshort:-mshort}%{!mshort:-mlong} " \ | |
| 51 "%{fshort-double:-mshort-double}%{!fshort-double:-mlong-double}" | |
| 52 #endif | |
| 53 | |
| 54 /* We need to tell the linker the target elf format. Just pass an | |
| 55 emulation option. This can be overridden by -Wl option of gcc. */ | |
| 56 #ifndef LINK_SPEC | |
| 57 #define LINK_SPEC \ | |
| 58 "%{m68hc12:-m m68hc12elf}" \ | |
| 59 "%{m68hcs12:-m m68hc12elf}" \ | |
| 60 "%{!m68hc12:%{!m68hcs12:-m m68hc11elf}} " \ | |
| 61 "%{!mnorelax:%{!m68hc12:%{!m68hcs12:-relax}}}" | |
| 62 #endif | |
| 63 | |
| 64 #ifndef LIB_SPEC | |
| 65 #define LIB_SPEC "" | |
| 66 #endif | |
| 67 | |
| 68 #ifndef CC1_SPEC | |
| 69 #define CC1_SPEC "" | |
| 70 #endif | |
| 71 | |
| 72 #ifndef CPP_SPEC | |
| 73 #define CPP_SPEC \ | |
| 74 "%{mshort:-D__HAVE_SHORT_INT__ -D__INT__=16}\ | |
| 75 %{!mshort:-D__INT__=32}\ | |
| 76 %{m68hc12:-Dmc6812 -DMC6812 -Dmc68hc12}\ | |
| 77 %{m68hcs12:-Dmc6812 -DMC6812 -Dmc68hcs12}\ | |
| 78 %{!m68hc12:%{!m68hcs12:-Dmc6811 -DMC6811 -Dmc68hc11}}\ | |
| 79 %{fshort-double:-D__HAVE_SHORT_DOUBLE__}\ | |
| 80 %{mlong-calls:-D__USE_RTC__}" | |
| 81 #endif | |
| 82 | |
| 83 #undef STARTFILE_SPEC | |
| 84 #define STARTFILE_SPEC "crt1%O%s" | |
| 85 | |
| 86 /* Names to predefine in the preprocessor for this target machine. */ | |
| 87 #define TARGET_CPU_CPP_BUILTINS() \ | |
| 88 do \ | |
| 89 { \ | |
| 90 builtin_define_std ("mc68hc1x"); \ | |
| 91 } \ | |
| 92 while (0) | |
| 93 | |
| 94 /* As an embedded target, we have no libc. */ | |
| 95 #ifndef inhibit_libc | |
| 96 # define inhibit_libc | |
| 97 #endif | |
| 98 | |
| 99 /* Forward type declaration for prototypes definitions. | |
| 100 rtx_ptr is equivalent to rtx. Can't use the same name. */ | |
| 101 struct rtx_def; | |
| 102 typedef struct rtx_def *rtx_ptr; | |
| 103 | |
| 104 union tree_node; | |
| 105 typedef union tree_node *tree_ptr; | |
| 106 | |
| 107 /* We can't declare enum machine_mode forward nor include 'machmode.h' here. | |
| 108 Prototypes defined here will use an int instead. It's better than no | |
| 109 prototype at all. */ | |
| 110 typedef int enum_machine_mode; | |
| 111 | |
| 112 /***************************************************************************** | |
| 113 ** | |
| 114 ** Run-time Target Specification | |
| 115 ** | |
| 116 *****************************************************************************/ | |
| 117 | |
| 118 /* Run-time compilation parameters selecting different hardware subsets. */ | |
| 119 | |
| 120 extern short *reg_renumber; /* def in local_alloc.c */ | |
| 121 | |
| 122 #define TARGET_OP_TIME (optimize && optimize_size == 0) | |
| 123 #define TARGET_RELAX (TARGET_NO_DIRECT_MODE) | |
| 124 | |
| 125 /* Default target_flags if no switches specified. */ | |
| 126 #ifndef TARGET_DEFAULT | |
| 127 # define TARGET_DEFAULT 0 | |
| 128 #endif | |
| 129 | |
| 130 /* Define this macro as a C expression for the initializer of an | |
| 131 array of string to tell the driver program which options are | |
| 132 defaults for this target and thus do not need to be handled | |
| 133 specially when using `MULTILIB_OPTIONS'. */ | |
| 134 #ifndef MULTILIB_DEFAULTS | |
| 135 # if TARGET_DEFAULT & MASK_M6811 | |
| 136 # define MULTILIB_DEFAULTS { "m68hc11" } | |
| 137 # else | |
| 138 # define MULTILIB_DEFAULTS { "m68hc12" } | |
| 139 # endif | |
| 140 #endif | |
| 141 | |
| 142 /* Print subsidiary information on the compiler version in use. */ | |
| 143 #define TARGET_VERSION fprintf (stderr, " (MC68HC11/MC68HC12/MC68HCS12)") | |
| 144 | |
| 145 /* Sometimes certain combinations of command options do not make | |
| 146 sense on a particular target machine. You can define a macro | |
| 147 `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
| 148 defined, is executed once just after all the command options have | |
| 149 been parsed. | |
| 150 | |
| 151 Don't use this macro to turn on various extra optimizations for | |
| 152 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
| 153 | |
| 154 #define OVERRIDE_OPTIONS m68hc11_override_options () | |
| 155 | |
| 156 | |
| 157 /* Define cost parameters for a given processor variant. */ | |
| 158 struct processor_costs { | |
| 159 const int add; /* cost of an add instruction */ | |
| 160 const int logical; /* cost of a logical instruction */ | |
| 161 const int shift_var; | |
| 162 const int shiftQI_const[8]; | |
| 163 const int shiftHI_const[16]; | |
| 164 const int multQI; | |
| 165 const int multHI; | |
| 166 const int multSI; | |
| 167 const int divQI; | |
| 168 const int divHI; | |
| 169 const int divSI; | |
| 170 }; | |
| 171 | |
| 172 /* Costs for the current processor. */ | |
| 173 extern const struct processor_costs *m68hc11_cost; | |
| 174 | |
| 175 | |
| 176 /* target machine storage layout */ | |
| 177 | |
| 178 /* Define this if most significant byte of a word is the lowest numbered. */ | |
| 179 #define BYTES_BIG_ENDIAN 1 | |
| 180 | |
| 181 /* Define this if most significant bit is lowest numbered | |
| 182 in instructions that operate on numbered bit-fields. */ | |
| 183 #define BITS_BIG_ENDIAN 0 | |
| 184 | |
| 185 /* Define this if most significant word of a multiword number is numbered. */ | |
| 186 #define WORDS_BIG_ENDIAN 1 | |
| 187 | |
| 188 /* Width of a word, in units (bytes). */ | |
| 189 #define UNITS_PER_WORD 2 | |
| 190 | |
| 191 /* Definition of size_t. This is really an unsigned short as the | |
| 192 68hc11 only handles a 64K address space. */ | |
| 193 #define SIZE_TYPE "short unsigned int" | |
| 194 | |
| 195 /* A C expression for a string describing the name of the data type | |
| 196 to use for the result of subtracting two pointers. The typedef | |
| 197 name `ptrdiff_t' is defined using the contents of the string. | |
| 198 The 68hc11 only has a 64K address space. */ | |
| 199 #define PTRDIFF_TYPE "short int" | |
| 200 | |
| 201 /* Allocation boundary (bits) for storing pointers in memory. */ | |
| 202 #define POINTER_BOUNDARY 8 | |
| 203 | |
| 204 /* Normal alignment required for function parameters on the stack, in bits. | |
| 205 This can't be less than BITS_PER_WORD */ | |
| 206 #define PARM_BOUNDARY (BITS_PER_WORD) | |
| 207 | |
| 208 /* Boundary (bits) on which stack pointer should be aligned. */ | |
| 209 #define STACK_BOUNDARY 8 | |
| 210 | |
| 211 /* Allocation boundary (bits) for the code of a function. */ | |
| 212 #define FUNCTION_BOUNDARY 8 | |
| 213 | |
| 214 #define BIGGEST_ALIGNMENT 8 | |
| 215 | |
| 216 /* Alignment of field after `int : 0' in a structure. */ | |
| 217 #define EMPTY_FIELD_BOUNDARY 8 | |
| 218 | |
| 219 /* Every structure's size must be a multiple of this. */ | |
| 220 #define STRUCTURE_SIZE_BOUNDARY 8 | |
| 221 | |
| 222 /* Define this if instructions will fail to work if given data not | |
| 223 on the nominal alignment. If instructions will merely go slower | |
| 224 in that case, do not define this macro. */ | |
| 225 #define STRICT_ALIGNMENT 0 | |
| 226 | |
| 227 /* An integer expression for the size in bits of the largest integer | |
| 228 machine mode that should actually be used. All integer machine modes of | |
| 229 this size or smaller can be used for structures and unions with the | |
| 230 appropriate sizes. */ | |
| 231 #define MAX_FIXED_MODE_SIZE 64 | |
| 232 | |
| 233 /* target machine storage layout */ | |
| 234 | |
| 235 /* Size (bits) of the type "int" on target machine | |
| 236 (If undefined, default is BITS_PER_WORD). */ | |
| 237 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) | |
| 238 | |
| 239 /* Size (bits) of the type "short" on target machine */ | |
| 240 #define SHORT_TYPE_SIZE 16 | |
| 241 | |
| 242 /* Size (bits) of the type "long" on target machine */ | |
| 243 #define LONG_TYPE_SIZE 32 | |
| 244 | |
| 245 /* Size (bits) of the type "long long" on target machine */ | |
| 246 #define LONG_LONG_TYPE_SIZE 64 | |
| 247 | |
| 248 /* A C expression for the size in bits of the type `float' on the | |
| 249 target machine. If you don't define this, the default is one word. | |
| 250 Don't use default: a word is only 16. */ | |
| 251 #define FLOAT_TYPE_SIZE 32 | |
| 252 | |
| 253 /* A C expression for the size in bits of the type double on the target | |
| 254 machine. If you don't define this, the default is two words. | |
| 255 Be IEEE compliant. */ | |
| 256 #define DOUBLE_TYPE_SIZE 64 | |
| 257 | |
| 258 #define LONG_DOUBLE_TYPE_SIZE 64 | |
| 259 | |
| 260 /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
| 261 #define DEFAULT_SIGNED_CHAR 0 | |
| 262 | |
| 263 /* Define these to avoid dependence on meaning of `int'. | |
| 264 Note that WCHAR_TYPE_SIZE is used in cexp.y, | |
| 265 where TARGET_SHORT is not available. */ | |
| 266 #define WCHAR_TYPE "short int" | |
| 267 #define WCHAR_TYPE_SIZE 16 | |
| 268 | |
| 269 | |
| 270 /* Standard register usage. */ | |
| 271 | |
| 272 #define HARD_REG_SIZE (UNITS_PER_WORD) | |
| 273 | |
| 274 /* Assign names to real MC68HC11 registers. | |
| 275 A and B registers are not really used (A+B = D) | |
| 276 X register is first so that GCC allocates X+D for 32-bit integers and | |
| 277 the lowpart of that integer will be D. Having the lower part in D is | |
| 278 better for 32<->16bit conversions and for many arithmetic operations. */ | |
| 279 #define HARD_X_REGNUM 0 | |
| 280 #define HARD_D_REGNUM 1 | |
| 281 #define HARD_Y_REGNUM 2 | |
| 282 #define HARD_SP_REGNUM 3 | |
| 283 #define HARD_PC_REGNUM 4 | |
| 284 #define HARD_A_REGNUM 5 | |
| 285 #define HARD_B_REGNUM 6 | |
| 286 #define HARD_CCR_REGNUM 7 | |
| 287 | |
| 288 /* The Z register does not really exist in the 68HC11. This a fake register | |
| 289 for GCC. It is treated exactly as an index register (X or Y). It is only | |
| 290 in the A_REGS class, which is the BASE_REG_CLASS for GCC. Defining this | |
| 291 register helps the reload pass of GCC. Otherwise, the reload often dies | |
| 292 with register spill failures. | |
| 293 | |
| 294 The Z register is replaced by either X or Y during the machine specific | |
| 295 reorg (m68hc11_reorg). It is saved in the SOFT_Z_REGNUM soft-register | |
| 296 when this is necessary. | |
| 297 | |
| 298 It's possible to tell GCC not to use this register with -ffixed-z. */ | |
| 299 #define HARD_Z_REGNUM 8 | |
| 300 | |
| 301 /* The frame pointer is a soft-register. It's treated as such by GCC: | |
| 302 it is not and must not be part of the BASE_REG_CLASS. */ | |
| 303 #define DEFAULT_HARD_FP_REGNUM (9) | |
| 304 #define HARD_FP_REGNUM (9) | |
| 305 #define HARD_AP_REGNUM (HARD_FP_REGNUM) | |
| 306 | |
| 307 /* Temporary soft-register used in some cases when an operand came | |
| 308 up into a bad register class (D, X, Y, SP) and gcc failed to | |
| 309 recognize this. This register is never allocated by GCC. */ | |
| 310 #define SOFT_TMP_REGNUM 10 | |
| 311 | |
| 312 /* The soft-register which is used to save the Z register | |
| 313 (see Z register replacement notes in m68hc11.c). */ | |
| 314 #define SOFT_Z_REGNUM 11 | |
| 315 | |
| 316 /* The soft-register which is used to save either X or Y. */ | |
| 317 #define SOFT_SAVED_XY_REGNUM 12 | |
| 318 | |
| 319 /* A fake clobber register for 68HC12 patterns. */ | |
| 320 #define FAKE_CLOBBER_REGNUM (13) | |
| 321 | |
| 322 /* Define 32 soft-registers of 16-bit each. By default, | |
| 323 only 12 of them are enabled and can be used by GCC. The | |
| 324 -msoft-reg-count=<n> option allows to control the number of valid | |
| 325 soft-registers. GCC can put 32-bit values in them | |
| 326 by allocating consecutive registers. The first 3 soft-registers | |
| 327 are never allocated by GCC. They are used in case the insn template needs | |
| 328 a temporary register, or for the Z register replacement. */ | |
| 329 | |
| 330 #define MAX_SOFT_REG_COUNT (32) | |
| 331 #define SOFT_REG_FIXED 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 332 0, 0, 0, 0, 1, 1, 1, 1, \ | |
| 333 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 334 1, 1, 1, 1, 1, 1, 1, 1 | |
| 335 #define SOFT_REG_USED 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 336 0, 0, 0, 0, 1, 1, 1, 1, \ | |
| 337 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 338 1, 1, 1, 1, 1, 1, 1, 1 | |
| 339 #define SOFT_REG_ORDER \ | |
| 340 SOFT_REG_FIRST, SOFT_REG_FIRST+1,SOFT_REG_FIRST+2,SOFT_REG_FIRST+3,\ | |
| 341 SOFT_REG_FIRST+4, SOFT_REG_FIRST+5,SOFT_REG_FIRST+6,SOFT_REG_FIRST+7,\ | |
| 342 SOFT_REG_FIRST+8, SOFT_REG_FIRST+9,SOFT_REG_FIRST+10,SOFT_REG_FIRST+11,\ | |
| 343 SOFT_REG_FIRST+12, SOFT_REG_FIRST+13,SOFT_REG_FIRST+14,SOFT_REG_FIRST+15,\ | |
| 344 SOFT_REG_FIRST+16, SOFT_REG_FIRST+17,SOFT_REG_FIRST+18,SOFT_REG_FIRST+19,\ | |
| 345 SOFT_REG_FIRST+20, SOFT_REG_FIRST+21,SOFT_REG_FIRST+22,SOFT_REG_FIRST+23,\ | |
| 346 SOFT_REG_FIRST+24, SOFT_REG_FIRST+25,SOFT_REG_FIRST+26,SOFT_REG_FIRST+27,\ | |
| 347 SOFT_REG_FIRST+28, SOFT_REG_FIRST+29,SOFT_REG_FIRST+30,SOFT_REG_FIRST+31 | |
| 348 | |
| 349 #define SOFT_REG_NAMES \ | |
| 350 "*_.d1", "*_.d2", "*_.d3", "*_.d4", \ | |
| 351 "*_.d5", "*_.d6", "*_.d7", "*_.d8", \ | |
| 352 "*_.d9", "*_.d10", "*_.d11", "*_.d12", \ | |
| 353 "*_.d13", "*_.d14", "*_.d15", "*_.d16", \ | |
| 354 "*_.d17", "*_.d18", "*_.d19", "*_.d20", \ | |
| 355 "*_.d21", "*_.d22", "*_.d23", "*_.d24", \ | |
| 356 "*_.d25", "*_.d26", "*_.d27", "*_.d28", \ | |
| 357 "*_.d29", "*_.d30", "*_.d31", "*_.d32" | |
| 358 | |
| 359 /* First available soft-register for GCC. */ | |
| 360 #define SOFT_REG_FIRST (SOFT_SAVED_XY_REGNUM+2) | |
| 361 | |
| 362 /* Last available soft-register for GCC. */ | |
| 363 #define SOFT_REG_LAST (SOFT_REG_FIRST+MAX_SOFT_REG_COUNT) | |
| 364 #define SOFT_FP_REGNUM (SOFT_REG_LAST) | |
| 365 #define SOFT_AP_REGNUM (SOFT_FP_REGNUM+1) | |
| 366 | |
| 367 /* Number of actual hardware registers. The hardware registers are assigned | |
| 368 numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. | |
| 369 All registers that the compiler knows about must be given numbers, even | |
| 370 those that are not normally considered general registers. */ | |
| 371 #define FIRST_PSEUDO_REGISTER (SOFT_REG_LAST+2) | |
| 372 | |
| 373 /* 1 for registers that have pervasive standard uses and are not available | |
| 374 for the register allocator. */ | |
| 375 #define FIXED_REGISTERS \ | |
| 376 {0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,1, 1, SOFT_REG_FIXED, 1, 1} | |
| 377 /* X, D, Y, SP,PC,A, B, CCR, Z, FP,ZTMP,ZR,XYR, FK, D1 - D32, SOFT-FP, AP */ | |
| 378 | |
| 379 /* 1 for registers not available across function calls. For our pseudo | |
| 380 registers, all are available. */ | |
| 381 #define CALL_USED_REGISTERS \ | |
| 382 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1, 1, SOFT_REG_USED, 1, 1} | |
| 383 /* X, D, Y, SP,PC,A, B, CCR, Z, FP, ZTMP,ZR,XYR, D1 - 32, SOFT-FP, AP */ | |
| 384 | |
| 385 | |
| 386 /* Define this macro to change register usage conditional on target flags. | |
| 387 | |
| 388 The soft-registers are disabled or enabled according to the | |
| 389 -msoft-reg-count=<n> option. */ | |
| 390 | |
| 391 | |
| 392 #define CONDITIONAL_REGISTER_USAGE (m68hc11_conditional_register_usage ()) | |
| 393 | |
| 394 /* List the order in which to allocate registers. Each register must be | |
| 395 listed once, even those in FIXED_REGISTERS. */ | |
| 396 #define REG_ALLOC_ORDER \ | |
| 397 { HARD_D_REGNUM, HARD_X_REGNUM, HARD_Y_REGNUM, \ | |
| 398 SOFT_REG_ORDER, HARD_Z_REGNUM, HARD_PC_REGNUM, HARD_A_REGNUM, \ | |
| 399 HARD_B_REGNUM, HARD_CCR_REGNUM, HARD_FP_REGNUM, SOFT_FP_REGNUM, \ | |
| 400 HARD_SP_REGNUM, SOFT_TMP_REGNUM, SOFT_Z_REGNUM, SOFT_SAVED_XY_REGNUM, \ | |
| 401 SOFT_AP_REGNUM, FAKE_CLOBBER_REGNUM } | |
| 402 | |
| 403 /* A C expression for the number of consecutive hard registers, | |
| 404 starting at register number REGNO, required to hold a value of | |
| 405 mode MODE. */ | |
| 406 #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
| 407 ((Q_REGNO_P (REGNO)) ? (GET_MODE_SIZE (MODE)) : \ | |
| 408 ((GET_MODE_SIZE (MODE) + HARD_REG_SIZE - 1) / HARD_REG_SIZE)) | |
| 409 | |
| 410 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
| 411 - 8-bit values are stored anywhere (except the SP register). | |
| 412 - 16-bit values can be stored in any register whose mode is 16 | |
| 413 - 32-bit values can be stored in D, X registers or in a soft register | |
| 414 (except the last one because we need 2 soft registers) | |
| 415 - Values whose size is > 32 bit are not stored in real hard | |
| 416 registers. They may be stored in soft registers if there are | |
| 417 enough of them. */ | |
| 418 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
| 419 hard_regno_mode_ok (REGNO,MODE) | |
| 420 | |
| 421 /* Value is 1 if it is a good idea to tie two pseudo registers when one has | |
| 422 mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce | |
| 423 different values for MODE1 and MODE2, for any hard reg, then this must be | |
| 424 0 for correct output. | |
| 425 | |
| 426 All modes are tieable except QImode. */ | |
| 427 #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
| 428 (((MODE1) == (MODE2)) \ | |
| 429 || ((MODE1) != QImode && (MODE2) != QImode)) | |
| 430 | |
| 431 | |
| 432 /* Define the classes of registers for register constraints in the | |
| 433 machine description. Also define ranges of constants. | |
| 434 | |
| 435 One of the classes must always be named ALL_REGS and include all hard regs. | |
| 436 If there is more than one class, another class must be named NO_REGS | |
| 437 and contain no registers. | |
| 438 | |
| 439 The name GENERAL_REGS must be the name of a class (or an alias for | |
| 440 another name such as ALL_REGS). This is the class of registers | |
| 441 that is allowed by "g" or "r" in a register constraint. | |
| 442 Also, registers outside this class are allocated only when | |
| 443 instructions express preferences for them. | |
| 444 | |
| 445 The classes must be numbered in nondecreasing order; that is, | |
| 446 a larger-numbered class must never be contained completely | |
| 447 in a smaller-numbered class. | |
| 448 | |
| 449 For any two classes, it is very desirable that there be another | |
| 450 class that represents their union. */ | |
| 451 | |
| 452 /* The M68hc11 has so few registers that it's not possible for GCC to | |
| 453 do any register allocation without breaking. We extend the processor | |
| 454 registers by having soft registers. These registers are treated as | |
| 455 hard registers by GCC but they are located in memory and accessed by page0 | |
| 456 accesses (IND mode). */ | |
| 457 enum reg_class | |
| 458 { | |
| 459 NO_REGS, | |
| 460 D_REGS, /* 16-bit data register */ | |
| 461 X_REGS, /* 16-bit X register */ | |
| 462 Y_REGS, /* 16-bit Y register */ | |
| 463 SP_REGS, /* 16-bit stack pointer */ | |
| 464 DA_REGS, /* 8-bit A reg. */ | |
| 465 DB_REGS, /* 8-bit B reg. */ | |
| 466 Z_REGS, /* 16-bit fake Z register */ | |
| 467 D8_REGS, /* 8-bit A or B reg. */ | |
| 468 Q_REGS, /* 8-bit (byte (QI)) data (A, B or D) */ | |
| 469 D_OR_X_REGS, /* D or X register */ | |
| 470 D_OR_Y_REGS, /* D or Y register */ | |
| 471 D_OR_SP_REGS, /* D or SP register */ | |
| 472 X_OR_Y_REGS, /* IX or Y register */ | |
| 473 A_REGS, /* 16-bit address register (X, Y, Z) */ | |
| 474 X_OR_SP_REGS, /* X or SP register */ | |
| 475 Y_OR_SP_REGS, /* Y or SP register */ | |
| 476 X_OR_Y_OR_D_REGS, /* X, Y or D */ | |
| 477 A_OR_D_REGS, /* X, Y, Z or D */ | |
| 478 A_OR_SP_REGS, /* X, Y, Z or SP */ | |
| 479 H_REGS, /* 16-bit hard register (D, X, Y, Z, SP) */ | |
| 480 S_REGS, /* 16-bit soft register */ | |
| 481 D_OR_S_REGS, /* 16-bit soft register or D register */ | |
| 482 X_OR_S_REGS, /* 16-bit soft register or X register */ | |
| 483 Y_OR_S_REGS, /* 16-bit soft register or Y register */ | |
| 484 Z_OR_S_REGS, /* 16-bit soft register or Z register */ | |
| 485 SP_OR_S_REGS, /* 16-bit soft register or SP register */ | |
| 486 D_OR_X_OR_S_REGS, /* 16-bit soft register or D or X register */ | |
| 487 D_OR_Y_OR_S_REGS, /* 16-bit soft register or D or Y register */ | |
| 488 D_OR_SP_OR_S_REGS, /* 16-bit soft register or D or SP register */ | |
| 489 A_OR_S_REGS, /* 16-bit soft register or X, Y registers */ | |
| 490 D_OR_A_OR_S_REGS, /* 16-bit soft register or D, X, Y registers */ | |
| 491 TMP_REGS, /* 16-bit fake scratch register */ | |
| 492 D_OR_A_OR_TMP_REGS, /* General scratch register */ | |
| 493 G_REGS, /* 16-bit general register | |
| 494 (H_REGS + soft registers) */ | |
| 495 ALL_REGS, | |
| 496 LIM_REG_CLASSES | |
| 497 }; | |
| 498 | |
| 499 /* alias GENERAL_REGS to G_REGS. */ | |
| 500 #define GENERAL_REGS G_REGS | |
| 501 | |
| 502 #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
| 503 | |
| 504 /* Give names of register classes as strings for dump file. */ | |
| 505 #define REG_CLASS_NAMES \ | |
| 506 { "NO_REGS", \ | |
| 507 "D_REGS", \ | |
| 508 "X_REGS", \ | |
| 509 "Y_REGS", \ | |
| 510 "SP_REGS", \ | |
| 511 "DA_REGS", \ | |
| 512 "DB_REGS", \ | |
| 513 "D8_REGS", \ | |
| 514 "Z_REGS", \ | |
| 515 "Q_REGS", \ | |
| 516 "D_OR_X_REGS", \ | |
| 517 "D_OR_Y_REGS", \ | |
| 518 "D_OR_SP_REGS", \ | |
| 519 "X_OR_Y_REGS", \ | |
| 520 "A_REGS", \ | |
| 521 "X_OR_SP_REGS", \ | |
| 522 "Y_OR_SP_REGS", \ | |
| 523 "X_OR_Y_OR_D_REGS", \ | |
| 524 "A_OR_D_REGS", \ | |
| 525 "A_OR_SP_REGS", \ | |
| 526 "H_REGS", \ | |
| 527 "S_REGS", \ | |
| 528 "D_OR_S_REGS", \ | |
| 529 "X_OR_S_REGS", \ | |
| 530 "Y_OR_S_REGS", \ | |
| 531 "Z_OR_S_REGS", \ | |
| 532 "SP_OR_S_REGS", \ | |
| 533 "D_OR_X_OR_S_REGS", \ | |
| 534 "D_OR_Y_OR_S_REGS", \ | |
| 535 "D_OR_SP_OR_S_REGS", \ | |
| 536 "A_OR_S_REGS", \ | |
| 537 "D_OR_A_OR_S_REGS", \ | |
| 538 "TMP_REGS", \ | |
| 539 "D_OR_A_OR_TMP_REGS", \ | |
| 540 "G_REGS", \ | |
| 541 "ALL_REGS" } | |
| 542 | |
| 543 /* An initializer containing the contents of the register classes, | |
| 544 as integers which are bit masks. The Nth integer specifies the | |
| 545 contents of class N. The way the integer MASK is interpreted is | |
| 546 that register R is in the class if `MASK & (1 << R)' is 1. */ | |
| 547 | |
| 548 /*-------------------------------------------------------------- | |
| 549 X 0x00000001 | |
| 550 D 0x00000002 | |
| 551 Y 0x00000004 | |
| 552 SP 0x00000008 | |
| 553 PC 0x00000010 | |
| 554 A 0x00000020 | |
| 555 B 0x00000040 | |
| 556 CCR 0x00000080 | |
| 557 Z 0x00000100 | |
| 558 FRAME 0x00000200 | |
| 559 ZTMP 0x00000400 | |
| 560 ZREG 0x00000800 | |
| 561 XYREG 0x00001000 | |
| 562 FAKE 0x00002000 | |
| 563 Di 0xFFFFc000, 0x03FFF | |
| 564 SFRAME 0x00000000, 0x04000 | |
| 565 AP 0x00000000, 0x08000 | |
| 566 | |
| 567 D_OR_X_REGS represents D+X. It is used for 32-bits numbers. | |
| 568 A_REGS represents a valid base register for indexing. It represents | |
| 569 X,Y and the Z register. | |
| 570 S_REGS represents the soft-registers. This includes the hard frame | |
| 571 and soft frame registers. | |
| 572 --------------------------------------------------------------*/ | |
| 573 | |
| 574 #define REG_CLASS_CONTENTS \ | |
| 575 /* NO_REGS */ {{ 0x00000000, 0x00000000 }, \ | |
| 576 /* D_REGS */ { 0x00000002, 0x00000000 }, /* D */ \ | |
| 577 /* X_REGS */ { 0x00000001, 0x00000000 }, /* X */ \ | |
| 578 /* Y_REGS */ { 0x00000004, 0x00000000 }, /* Y */ \ | |
| 579 /* SP_REGS */ { 0x00000008, 0x00000000 }, /* SP */ \ | |
| 580 /* DA_REGS */ { 0x00000020, 0x00000000 }, /* A */ \ | |
| 581 /* DB_REGS */ { 0x00000040, 0x00000000 }, /* B */ \ | |
| 582 /* Z_REGS */ { 0x00000100, 0x00000000 }, /* Z */ \ | |
| 583 /* D8_REGS */ { 0x00000060, 0x00000000 }, /* A B */ \ | |
| 584 /* Q_REGS */ { 0x00000062, 0x00000000 }, /* A B D */ \ | |
| 585 /* D_OR_X_REGS */ { 0x00000003, 0x00000000 }, /* D X */ \ | |
| 586 /* D_OR_Y_REGS */ { 0x00000006, 0x00000000 }, /* D Y */ \ | |
| 587 /* D_OR_SP_REGS */ { 0x0000000A, 0x00000000 }, /* D SP */ \ | |
| 588 /* X_OR_Y_REGS */ { 0x00000005, 0x00000000 }, /* X Y */ \ | |
| 589 /* A_REGS */ { 0x00000105, 0x00000000 }, /* X Y Z */ \ | |
| 590 /* X_OR_SP_REGS */ { 0x00000009, 0x00000000 }, /* X SP */ \ | |
| 591 /* Y_OR_SP_REGS */ { 0x0000000C, 0x00000000 }, /* Y SP */ \ | |
| 592 /* X_OR_Y_OR_D_REGS */ { 0x00000007, 0x00000000 }, /* D X Y */ \ | |
| 593 /* A_OR_D_REGS */ { 0x00000107, 0x00000000 }, /* D X Y Z */ \ | |
| 594 /* A_OR_SP_REGS */ { 0x0000010D, 0x00000000 }, /* X Y SP */ \ | |
| 595 /* H_REGS */ { 0x0000010F, 0x00000000 }, /* D X Y SP */ \ | |
| 596 /* S_REGS */ { 0xFFFFDE00, 0x00007FFF }, /* _.D,..,FP,Z* */ \ | |
| 597 /* D_OR_S_REGS */ { 0xFFFFDE02, 0x00007FFF }, /* D _.D */ \ | |
| 598 /* X_OR_S_REGS */ { 0xFFFFDE01, 0x00007FFF }, /* X _.D */ \ | |
| 599 /* Y_OR_S_REGS */ { 0xFFFFDE04, 0x00007FFF }, /* Y _.D */ \ | |
| 600 /* Z_OR_S_REGS */ { 0xFFFFDF00, 0x00007FFF }, /* Z _.D */ \ | |
| 601 /* SP_OR_S_REGS */ { 0xFFFFDE08, 0x00007FFF }, /* SP _.D */ \ | |
| 602 /* D_OR_X_OR_S_REGS */ { 0xFFFFDE03, 0x00007FFF }, /* D X _.D */ \ | |
| 603 /* D_OR_Y_OR_S_REGS */ { 0xFFFFDE06, 0x00007FFF }, /* D Y _.D */ \ | |
| 604 /* D_OR_SP_OR_S_REGS */ { 0xFFFFDE0A, 0x00007FFF }, /* D SP _.D */ \ | |
| 605 /* A_OR_S_REGS */ { 0xFFFFDF05, 0x00007FFF }, /* X Y _.D */ \ | |
| 606 /* D_OR_A_OR_S_REGS */ { 0xFFFFDF07, 0x00007FFF }, /* D X Y _.D */ \ | |
| 607 /* TMP_REGS */ { 0x00002000, 0x00000000 }, /* FAKE */ \ | |
| 608 /* D_OR_A_OR_TMP_REGS*/ { 0x00002107, 0x00000000 }, /* D X Y Z Fake */ \ | |
| 609 /* G_REGS */ { 0xFFFFFF1F, 0x00007FFF }, /* ? _.D D X Y */ \ | |
| 610 /* ALL_REGS*/ { 0xFFFFFFFF, 0x00007FFF }} | |
| 611 | |
| 612 | |
| 613 /* set up a C expression whose value is a register class containing hard | |
| 614 register REGNO */ | |
| 615 #define Q_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM \ | |
| 616 || (REGNO) == HARD_B_REGNUM) | |
| 617 #define Q_REG_P(X) (REG_P (X) && Q_REGNO_P (REGNO (X))) | |
| 618 | |
| 619 #define D_REGNO_P(REGNO) ((REGNO) == HARD_D_REGNUM) | |
| 620 #define D_REG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X))) | |
| 621 | |
| 622 #define DB_REGNO_P(REGNO) ((REGNO) == HARD_B_REGNUM) | |
| 623 #define DB_REG_P(X) (REG_P (X) && DB_REGNO_P (REGNO (X))) | |
| 624 #define DA_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM) | |
| 625 #define DA_REG_P(X) (REG_P (X) && DA_REGNO_P (REGNO (X))) | |
| 626 | |
| 627 #define X_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM) | |
| 628 #define X_REG_P(X) (REG_P (X) && X_REGNO_P (REGNO (X))) | |
| 629 | |
| 630 #define Y_REGNO_P(REGNO) ((REGNO) == HARD_Y_REGNUM) | |
| 631 #define Y_REG_P(X) (REG_P (X) && Y_REGNO_P (REGNO (X))) | |
| 632 | |
| 633 #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM) | |
| 634 #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X))) | |
| 635 | |
| 636 #define SP_REGNO_P(REGNO) ((REGNO) == HARD_SP_REGNUM) | |
| 637 #define SP_REG_P(X) (REG_P (X) && SP_REGNO_P (REGNO (X))) | |
| 638 | |
| 639 /* Address register. */ | |
| 640 #define A_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM \ | |
| 641 || (REGNO) == HARD_Y_REGNUM \ | |
| 642 || (REGNO) == HARD_Z_REGNUM) | |
| 643 #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X))) | |
| 644 | |
| 645 /* M68hc11 hard registers. */ | |
| 646 #define H_REGNO_P(REGNO) (D_REGNO_P (REGNO) || A_REGNO_P (REGNO) \ | |
| 647 || SP_REGNO_P (REGNO) || Q_REGNO_P (REGNO)) | |
| 648 #define H_REG_P(X) (REG_P (X) && H_REGNO_P (REGNO (X))) | |
| 649 | |
| 650 #define FAKE_REGNO_P(REGNO) ((REGNO) == FAKE_CLOBBER_REGNUM) | |
| 651 #define FAKE_REG_P(X) (REG_P (X) && FAKE_REGNO_P (REGNO (X))) | |
| 652 | |
| 653 /* Soft registers (or register emulation for gcc). The temporary register | |
| 654 used by insn template must be part of the S_REGS class so that it | |
| 655 matches the 'u' constraint. */ | |
| 656 #define S_REGNO_P(REGNO) ((REGNO) >= SOFT_TMP_REGNUM \ | |
| 657 && (REGNO) <= SOFT_REG_LAST \ | |
| 658 && (REGNO) != FAKE_CLOBBER_REGNUM) | |
| 659 #define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X))) | |
| 660 | |
| 661 #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM) | |
| 662 #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X))) | |
| 663 | |
| 664 /* General register. */ | |
| 665 #define G_REGNO_P(REGNO) (H_REGNO_P (REGNO) || S_REGNO_P (REGNO) \ | |
| 666 || ((REGNO) == HARD_PC_REGNUM) \ | |
| 667 || ((REGNO) == HARD_FP_REGNUM) \ | |
| 668 || ((REGNO) == SOFT_FP_REGNUM) \ | |
| 669 || ((REGNO) == FAKE_CLOBBER_REGNUM) \ | |
| 670 || ((REGNO) == SOFT_AP_REGNUM)) | |
| 671 | |
| 672 #define G_REG_P(X) (REG_P (X) && G_REGNO_P (REGNO (X))) | |
| 673 | |
| 674 #define REGNO_REG_CLASS(REGNO) \ | |
| 675 (D_REGNO_P (REGNO) ? D_REGS : \ | |
| 676 (X_REGNO_P (REGNO) ? X_REGS : \ | |
| 677 (Y_REGNO_P (REGNO) ? Y_REGS : \ | |
| 678 (SP_REGNO_P (REGNO) ? SP_REGS : \ | |
| 679 (Z_REGNO_P (REGNO) ? Z_REGS : \ | |
| 680 (H_REGNO_P (REGNO) ? H_REGS : \ | |
| 681 (FAKE_REGNO_P (REGNO) ? TMP_REGS : \ | |
| 682 (S_REGNO_P (REGNO) ? S_REGS : \ | |
| 683 (DA_REGNO_P (REGNO) ? DA_REGS: \ | |
| 684 (DB_REGNO_P (REGNO) ? DB_REGS: \ | |
| 685 (G_REGNO_P (REGNO) ? G_REGS : ALL_REGS))))))))))) | |
| 686 | |
| 687 | |
| 688 /* Get reg_class from a letter in the machine description. */ | |
| 689 | |
| 690 extern enum reg_class m68hc11_tmp_regs_class; | |
| 691 #define REG_CLASS_FROM_LETTER(C) \ | |
| 692 ((C) == 'a' ? DA_REGS : \ | |
| 693 (C) == 'A' ? A_REGS : \ | |
| 694 (C) == 'b' ? DB_REGS : \ | |
| 695 (C) == 'B' ? X_OR_Y_REGS : \ | |
| 696 (C) == 'd' ? D_REGS : \ | |
| 697 (C) == 'D' ? D_OR_X_REGS : \ | |
| 698 (C) == 'q' ? Q_REGS : \ | |
| 699 (C) == 'h' ? H_REGS : \ | |
| 700 (C) == 't' ? TMP_REGS : \ | |
| 701 (C) == 'u' ? S_REGS : \ | |
| 702 (C) == 'v' ? m68hc11_tmp_regs_class : \ | |
| 703 (C) == 'w' ? SP_REGS : \ | |
| 704 (C) == 'x' ? X_REGS : \ | |
| 705 (C) == 'y' ? Y_REGS : \ | |
| 706 (C) == 'z' ? Z_REGS : NO_REGS) | |
| 707 | |
| 708 #define PREFERRED_RELOAD_CLASS(X,CLASS) preferred_reload_class(X,CLASS) | |
| 709 | |
|
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
710 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true |
| 0 | 711 |
| 712 /* A C expression that is nonzero if hard register number REGNO2 can be | |
| 713 considered for use as a rename register for REGNO1 */ | |
| 714 | |
| 715 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \ | |
| 716 m68hc11_hard_regno_rename_ok ((REGNO1), (REGNO2)) | |
| 717 | |
| 718 /* A C expression whose value is nonzero if pseudos that have been | |
| 719 assigned to registers of class CLASS would likely be spilled | |
| 720 because registers of CLASS are needed for spill registers. | |
| 721 | |
| 722 The default value of this macro returns 1 if CLASS has exactly one | |
| 723 register and zero otherwise. On most machines, this default | |
| 724 should be used. Only define this macro to some other expression | |
| 725 if pseudo allocated by `local-alloc.c' end up in memory because | |
| 726 their hard registers were needed for spill registers. If this | |
| 727 macro returns nonzero for those classes, those pseudos will only | |
| 728 be allocated by `global.c', which knows how to reallocate the | |
| 729 pseudo to another register. If there would not be another | |
| 730 register available for reallocation, you should not change the | |
| 731 definition of this macro since the only effect of such a | |
| 732 definition would be to slow down register allocation. */ | |
| 733 | |
| 734 #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
| 735 (((CLASS) == D_REGS) \ | |
| 736 || ((CLASS) == X_REGS) \ | |
| 737 || ((CLASS) == Y_REGS) \ | |
| 738 || ((CLASS) == A_REGS) \ | |
| 739 || ((CLASS) == SP_REGS) \ | |
| 740 || ((CLASS) == D_OR_X_REGS) \ | |
| 741 || ((CLASS) == D_OR_Y_REGS) \ | |
| 742 || ((CLASS) == X_OR_SP_REGS) \ | |
| 743 || ((CLASS) == Y_OR_SP_REGS) \ | |
| 744 || ((CLASS) == D_OR_SP_REGS)) | |
| 745 | |
| 746 /* Return the maximum number of consecutive registers needed to represent | |
| 747 mode MODE in a register of class CLASS. */ | |
| 748 #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
| 749 (((CLASS) == DA_REGS || (CLASS) == DB_REGS \ | |
| 750 || (CLASS) == D8_REGS || (CLASS) == Q_REGS) ? GET_MODE_SIZE (MODE) \ | |
| 751 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
| 752 | |
| 753 /* The letters I, J, K, L and M in a register constraint string | |
| 754 can be used to stand for particular ranges of immediate operands. | |
| 755 This macro defines what the ranges are. | |
| 756 C is the letter, and VALUE is a constant value. | |
| 757 Return 1 if VALUE is in the range specified by C. | |
| 758 | |
| 759 `K' is for 0. | |
| 760 `L' is for range -65536 to 65536 | |
| 761 `M' is for values whose 16-bit low part is 0 | |
| 762 'N' is for +1 or -1. | |
| 763 'O' is for 16 (for rotate using swap). | |
| 764 'P' is for range -8 to 2 (used by addhi_sp) | |
| 765 | |
| 766 'I', 'J' are not used. */ | |
| 767 | |
| 768 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
| 769 ((C) == 'K' ? (VALUE) == 0 : \ | |
| 770 (C) == 'L' ? ((VALUE) >= -65536 && (VALUE) <= 65535) : \ | |
| 771 (C) == 'M' ? ((VALUE) & 0x0ffffL) == 0 : \ | |
| 772 (C) == 'N' ? ((VALUE) == 1 || (VALUE) == -1) : \ | |
| 773 (C) == 'I' ? ((VALUE) >= -2 && (VALUE) <= 2) : \ | |
| 774 (C) == 'O' ? (VALUE) == 16 : \ | |
| 775 (C) == 'P' ? ((VALUE) <= 2 && (VALUE) >= -8) : 0) | |
| 776 | |
| 777 /* Similar, but for floating constants, and defining letters G and H. | |
| 778 | |
| 779 `G' is for 0.0. */ | |
| 780 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
| 781 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \ | |
| 782 && VALUE == CONST0_RTX (GET_MODE (VALUE))) : 0) | |
| 783 | |
| 784 /* 'U' represents certain kind of memory indexed operand for 68HC12. | |
| 785 and any memory operand for 68HC11. | |
| 786 'R' represents indexed addressing mode or access to page0 for 68HC11. | |
| 787 For 68HC12, it represents any memory operand. */ | |
| 788 #define EXTRA_CONSTRAINT(OP, C) \ | |
| 789 ((C) == 'U' ? m68hc11_small_indexed_indirect_p (OP, GET_MODE (OP)) \ | |
| 790 : (C) == 'Q' ? m68hc11_symbolic_p (OP, GET_MODE (OP)) \ | |
| 791 : (C) == 'R' ? m68hc11_indirect_p (OP, GET_MODE (OP)) \ | |
| 792 : (C) == 'S' ? (memory_operand (OP, GET_MODE (OP)) \ | |
| 793 && non_push_operand (OP, GET_MODE (OP))) : 0) | |
| 794 | |
| 795 | |
| 796 /* Stack layout; function entry, exit and calling. */ | |
| 797 | |
| 798 /* Define this if pushing a word on the stack | |
| 799 makes the stack pointer a smaller address. */ | |
| 800 #define STACK_GROWS_DOWNWARD | |
| 801 | |
| 802 /* Define this to nonzero if the nominal address of the stack frame | |
| 803 is at the high-address end of the local variables; | |
| 804 that is, each additional local variable allocated | |
| 805 goes at a more negative offset in the frame. | |
| 806 | |
| 807 Define to 0 for 68HC11, the frame pointer is the bottom | |
| 808 of local variables. */ | |
| 809 #define FRAME_GROWS_DOWNWARD 0 | |
| 810 | |
| 811 /* Define this if successive arguments to a function occupy decreasing | |
| 812 addresses in the stack. */ | |
| 813 /* #define ARGS_GROW_DOWNWARD */ | |
| 814 | |
| 815 /* Offset within stack frame to start allocating local variables at. | |
| 816 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
| 817 first local allocated. Otherwise, it is the offset to the BEGINNING | |
| 818 of the first local allocated. */ | |
| 819 #define STARTING_FRAME_OFFSET 0 | |
| 820 | |
| 821 /* Offset of first parameter from the argument pointer register value. */ | |
| 822 | |
| 823 #define FIRST_PARM_OFFSET(FNDECL) 2 | |
| 824 | |
| 825 /* After the prologue, RA is at 0(AP) in the current frame. */ | |
| 826 #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
| 827 ((COUNT) == 0 \ | |
| 828 ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \ | |
| 829 : 0) | |
| 830 | |
| 831 /* Before the prologue, the top of the frame is at 2(sp). */ | |
| 832 #define INCOMING_FRAME_SP_OFFSET 2 | |
| 833 | |
| 834 /* Define this if functions should assume that stack space has been | |
| 835 allocated for arguments even when their values are passed in | |
| 836 registers. | |
| 837 | |
| 838 The value of this macro is the size, in bytes, of the area reserved for | |
| 839 arguments passed in registers. | |
| 840 | |
| 841 This space can either be allocated by the caller or be a part of the | |
| 842 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' | |
| 843 says which. */ | |
| 844 /* #define REG_PARM_STACK_SPACE(FNDECL) 2 */ | |
| 845 | |
| 846 /* Define this macro if REG_PARM_STACK_SPACE is defined but stack | |
| 847 parameters don't skip the area specified by REG_PARM_STACK_SPACE. | |
| 848 Normally, when a parameter is not passed in registers, it is placed on | |
| 849 the stack beyond the REG_PARM_STACK_SPACE area. Defining this macro | |
| 850 suppresses this behavior and causes the parameter to be passed on the | |
| 851 stack in its natural location. */ | |
| 852 /* #define STACK_PARMS_IN_REG_PARM_AREA */ | |
| 853 | |
| 854 /* Register to use for pushing function arguments. */ | |
| 855 #define STACK_POINTER_REGNUM HARD_SP_REGNUM | |
| 856 | |
| 857 /* Base register for access to local variables of the function. */ | |
| 858 #define FRAME_POINTER_REGNUM SOFT_FP_REGNUM | |
| 859 | |
| 860 #define HARD_FRAME_POINTER_REGNUM HARD_FP_REGNUM | |
| 861 | |
| 862 /* Base register for access to arguments of the function. */ | |
| 863 #define ARG_POINTER_REGNUM SOFT_AP_REGNUM | |
| 864 | |
| 865 /* Register in which static-chain is passed to a function. */ | |
| 866 #define STATIC_CHAIN_REGNUM SOFT_Z_REGNUM | |
| 867 | |
| 868 | |
| 869 /* Definitions for register eliminations. | |
| 870 | |
| 871 This is an array of structures. Each structure initializes one pair | |
| 872 of eliminable registers. The "from" register number is given first, | |
| 873 followed by "to". Eliminations of the same "from" register are listed | |
| 874 in order of preference. | |
| 875 | |
| 876 We have two registers that are eliminated on the 6811. The pseudo arg | |
| 877 pointer and pseudo frame pointer registers can always be eliminated; | |
| 878 they are replaced with either the stack or the real frame pointer. */ | |
| 879 | |
| 880 #define ELIMINABLE_REGS \ | |
| 881 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 882 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
| 883 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 884 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
| 885 | |
| 886 /* Define the offset between two registers, one to be eliminated, and the other | |
| 887 its replacement, at the start of a routine. */ | |
| 888 | |
| 889 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
| 890 { OFFSET = m68hc11_initial_elimination_offset (FROM, TO); } | |
| 891 | |
| 892 | |
| 893 /* Passing Function Arguments on the Stack. */ | |
| 894 | |
| 895 /* If we generate an insn to push BYTES bytes, this says how many the | |
| 896 stack pointer really advances by. No rounding or alignment needed | |
| 897 for MC6811. */ | |
| 898 #define PUSH_ROUNDING(BYTES) (BYTES) | |
| 899 | |
| 900 /* Value is 1 if returning from a function call automatically pops the | |
| 901 arguments described by the number-of-args field in the call. FUNTYPE is | |
| 902 the data type of the function (as a tree), or for a library call it is | |
| 903 an identifier node for the subroutine name. | |
| 904 | |
| 905 The standard MC6811 call, with arg count word, includes popping the | |
| 906 args as part of the call template. */ | |
| 907 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 | |
| 908 | |
| 909 /* Passing Arguments in Registers. */ | |
| 910 | |
| 911 /* Define a data type for recording info about an argument list | |
| 912 during the scan of that argument list. This data type should | |
| 913 hold all necessary information about the function itself | |
| 914 and about the args processed so far, enough to enable macros | |
| 915 such as FUNCTION_ARG to determine where the next arg should go. */ | |
| 916 | |
| 917 typedef struct m68hc11_args | |
| 918 { | |
| 919 int words; | |
| 920 int nregs; | |
| 921 } CUMULATIVE_ARGS; | |
| 922 | |
| 923 /* If defined, a C expression which determines whether, and in which direction, | |
| 924 to pad out an argument with extra space. The value should be of type | |
| 925 `enum direction': either `upward' to pad above the argument, | |
| 926 `downward' to pad below, or `none' to inhibit padding. | |
| 927 | |
| 928 Structures are stored left shifted in their argument slot. */ | |
| 929 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ | |
| 930 m68hc11_function_arg_padding ((MODE), (TYPE)) | |
| 931 | |
| 932 #undef PAD_VARARGS_DOWN | |
| 933 #define PAD_VARARGS_DOWN \ | |
| 934 (m68hc11_function_arg_padding (TYPE_MODE (type), type) == downward) | |
| 935 | |
| 936 /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a | |
| 937 function whose data type is FNTYPE. For a library call, FNTYPE is 0. */ | |
| 938 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ | |
| 939 (m68hc11_init_cumulative_args (&CUM, FNTYPE, LIBNAME)) | |
| 940 | |
| 941 /* Update the data in CUM to advance over an argument of mode MODE and data | |
| 942 type TYPE. (TYPE is null for libcalls where that information may not be | |
| 943 available.) */ | |
| 944 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
| 945 (m68hc11_function_arg_advance (&CUM, MODE, TYPE, NAMED)) | |
| 946 | |
| 947 /* Define where to put the arguments to a function. | |
| 948 Value is zero to push the argument on the stack, | |
| 949 or a hard register in which to store the argument. | |
| 950 | |
| 951 MODE is the argument's machine mode. | |
| 952 TYPE is the data type of the argument (as a tree). | |
| 953 This is null for libcalls where that information may | |
| 954 not be available. | |
| 955 CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
| 956 the preceding args and about the function being called. | |
| 957 NAMED is nonzero if this argument is a named parameter | |
| 958 (otherwise it is an extra parameter matching an ellipsis). */ | |
| 959 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
| 960 (m68hc11_function_arg (&CUM, MODE, TYPE, NAMED)) | |
| 961 | |
| 962 /* Define the profitability of saving registers around calls. | |
| 963 | |
| 964 Disable this because the saving instructions generated by | |
| 965 caller-save need a reload and the way it is implemented, | |
| 966 it forbids all spill registers at that point. Enabling | |
| 967 caller saving results in spill failure. */ | |
| 968 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0 | |
| 969 | |
| 970 /* 1 if N is a possible register number for function argument passing. | |
| 971 D is for 16-bit values, X is for 32-bit (X+D). */ | |
| 972 #define FUNCTION_ARG_REGNO_P(N) \ | |
| 973 (((N) == HARD_D_REGNUM) || ((N) == HARD_X_REGNUM)) | |
| 974 | |
| 975 /* All return values are in the D or X+D registers: | |
| 976 - 8 and 16-bit values are returned in D. | |
| 977 BLKmode are passed in D as pointer. | |
| 978 - 32-bit values are returned in X + D. | |
| 979 The high part is passed in X and the low part in D. | |
| 980 For GCC, the register number must be HARD_X_REGNUM. */ | |
| 981 #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
| 982 gen_rtx_REG (TYPE_MODE (VALTYPE), \ | |
| 983 ((TYPE_MODE (VALTYPE) == BLKmode \ | |
| 984 || GET_MODE_SIZE (TYPE_MODE (VALTYPE)) <= 2) \ | |
| 985 ? HARD_D_REGNUM : HARD_X_REGNUM)) | |
| 986 | |
| 987 #define LIBCALL_VALUE(MODE) \ | |
| 988 gen_rtx_REG (MODE, \ | |
| 989 (((MODE) == BLKmode || GET_MODE_SIZE (MODE) <= 2) \ | |
| 990 ? HARD_D_REGNUM : HARD_X_REGNUM)) | |
| 991 | |
| 992 /* 1 if N is a possible register number for a function value. */ | |
| 993 #define FUNCTION_VALUE_REGNO_P(N) \ | |
| 994 ((N) == HARD_D_REGNUM || (N) == HARD_X_REGNUM) | |
| 995 | |
| 996 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
| 997 the stack pointer does not matter. The value is tested only in functions | |
| 998 that have frame pointers. No definition is equivalent to always zero. */ | |
| 999 #define EXIT_IGNORE_STACK 0 | |
| 1000 | |
| 1001 | |
| 1002 /* Generating Code for Profiling. */ | |
| 1003 | |
| 1004 /* Output assembler code to FILE to increment profiler label # LABELNO | |
| 1005 for profiling a function entry. */ | |
| 1006 #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
| 1007 fprintf (FILE, "\tldy\t.LP%d\n\tjsr mcount\n", (LABELNO)) | |
|
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parents:
0
diff
changeset
|
1008 |
| 0 | 1009 /* Length in units of the trampoline for entering a nested function. */ |
| 1010 #define TRAMPOLINE_SIZE (TARGET_M6811 ? 11 : 9) | |
| 1011 | |
| 1012 | |
| 1013 /* Addressing modes, and classification of registers for them. */ | |
| 1014 | |
| 1015 #define ADDR_STRICT 0x01 /* Accept only registers in class A_REGS */ | |
| 1016 #define ADDR_INCDEC 0x02 /* Post/Pre inc/dec */ | |
| 1017 #define ADDR_INDEXED 0x04 /* D-reg index */ | |
| 1018 #define ADDR_OFFSET 0x08 | |
| 1019 #define ADDR_INDIRECT 0x10 /* Accept (mem (mem ...)) for [n,X] */ | |
| 1020 #define ADDR_CONST 0x20 /* Accept const and symbol_ref */ | |
| 1021 | |
| 1022 /* The 68HC12 has all the post/pre increment/decrement modes. */ | |
| 1023 #define HAVE_POST_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) | |
| 1024 #define HAVE_PRE_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) | |
| 1025 #define HAVE_POST_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) | |
| 1026 #define HAVE_PRE_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) | |
| 1027 | |
| 1028 /* The class value for base registers. This depends on the target: | |
| 1029 A_REGS for 68HC11 and A_OR_SP_REGS for 68HC12. The class value | |
| 1030 is stored at init time. */ | |
| 1031 extern enum reg_class m68hc11_base_reg_class; | |
| 1032 #define BASE_REG_CLASS m68hc11_base_reg_class | |
| 1033 | |
| 1034 /* The class value for index registers. This is NO_REGS for 68HC11. */ | |
| 1035 | |
| 1036 extern enum reg_class m68hc11_index_reg_class; | |
| 1037 #define INDEX_REG_CLASS m68hc11_index_reg_class | |
| 1038 | |
| 1039 /* These assume that REGNO is a hard or pseudo reg number. They give nonzero | |
| 1040 only if REGNO is a hard reg of the suitable class or a pseudo reg currently | |
| 1041 allocated to a suitable hard reg. Since they use reg_renumber, they are | |
| 1042 safe only once reg_renumber has been allocated, which happens in | |
| 1043 local-alloc.c. */ | |
| 1044 | |
| 1045 | |
| 1046 extern unsigned char m68hc11_reg_valid_for_base[FIRST_PSEUDO_REGISTER]; | |
| 1047 #define REG_VALID_FOR_BASE_P(REGNO) \ | |
| 1048 ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
| 1049 && m68hc11_reg_valid_for_base[REGNO]) | |
| 1050 | |
| 1051 /* Internal macro, return 1 if REGNO is a valid index register. */ | |
| 1052 extern unsigned char m68hc11_reg_valid_for_index[FIRST_PSEUDO_REGISTER]; | |
| 1053 #define REG_VALID_FOR_INDEX_P(REGNO) \ | |
| 1054 ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
| 1055 && m68hc11_reg_valid_for_index[REGNO]) | |
| 1056 | |
| 1057 /* Internal macro, the nonstrict definition for REGNO_OK_FOR_BASE_P. */ | |
| 1058 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \ | |
| 1059 ((REGNO) >= FIRST_PSEUDO_REGISTER \ | |
| 1060 || REG_VALID_FOR_BASE_P (REGNO) \ | |
| 1061 || (REGNO) == FRAME_POINTER_REGNUM \ | |
| 1062 || (REGNO) == HARD_FRAME_POINTER_REGNUM \ | |
| 1063 || (REGNO) == ARG_POINTER_REGNUM \ | |
| 1064 || (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO]))) | |
| 1065 | |
| 1066 /* Internal macro, the nonstrict definition for REGNO_OK_FOR_INDEX_P. */ | |
| 1067 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \ | |
| 1068 (TARGET_M6812 \ | |
| 1069 && ((REGNO) >= FIRST_PSEUDO_REGISTER \ | |
| 1070 || REG_VALID_FOR_INDEX_P (REGNO) \ | |
| 1071 || (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO])))) | |
| 1072 | |
| 1073 /* Internal macro, the strict definition for REGNO_OK_FOR_BASE_P. */ | |
| 1074 #define REGNO_OK_FOR_BASE_STRICT_P(REGNO) \ | |
| 1075 ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_BASE_P (REGNO) \ | |
| 1076 : (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO]))) | |
| 1077 | |
| 1078 /* Internal macro, the strict definition for REGNO_OK_FOR_INDEX_P. */ | |
| 1079 #define REGNO_OK_FOR_INDEX_STRICT_P(REGNO) \ | |
| 1080 (TARGET_M6812 \ | |
| 1081 && ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_INDEX_P (REGNO) \ | |
| 1082 : (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO])))) | |
| 1083 | |
| 1084 #define REGNO_OK_FOR_BASE_P2(REGNO,STRICT) \ | |
| 1085 ((STRICT) ? (REGNO_OK_FOR_BASE_STRICT_P (REGNO)) \ | |
| 1086 : (REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO))) | |
| 1087 | |
| 1088 #define REGNO_OK_FOR_INDEX_P2(REGNO,STRICT) \ | |
| 1089 ((STRICT) ? (REGNO_OK_FOR_INDEX_STRICT_P (REGNO)) \ | |
| 1090 : (REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO))) | |
| 1091 | |
| 1092 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_BASE_STRICT_P (REGNO) | |
| 1093 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_INDEX_STRICT_P (REGNO) | |
| 1094 | |
| 1095 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_STRICT_P (REGNO (X)) | |
| 1096 #define REG_OK_FOR_BASE_NONSTRICT_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (X)) | |
| 1097 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_STRICT_P (REGNO (X)) | |
| 1098 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (X)) | |
| 1099 | |
| 1100 /* see PUSH_POP_ADDRESS_P() below for an explanation of this. */ | |
| 1101 #define IS_STACK_PUSH(operand) \ | |
| 1102 ((GET_CODE (operand) == MEM) \ | |
| 1103 && (GET_CODE (XEXP (operand, 0)) == PRE_DEC) \ | |
| 1104 && (SP_REG_P (XEXP (XEXP (operand, 0), 0)))) | |
| 1105 | |
| 1106 #define IS_STACK_POP(operand) \ | |
| 1107 ((GET_CODE (operand) == MEM) \ | |
| 1108 && (GET_CODE (XEXP (operand, 0)) == POST_INC) \ | |
| 1109 && (SP_REG_P (XEXP (XEXP (operand, 0), 0)))) | |
| 1110 | |
| 1111 /* Maximum number of registers that can appear in a valid memory address */ | |
| 1112 #define MAX_REGS_PER_ADDRESS 2 | |
| 1113 | |
|
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parents:
0
diff
changeset
|
1114 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression that is a |
| 0 | 1115 valid memory address for an instruction. The MODE argument is the |
| 1116 machine mode for the MEM expression that wants to use this address. */ | |
| 1117 | |
| 1118 /*-------------------------------------------------------------- | |
| 1119 Valid addresses are either direct or indirect (MEM) versions | |
| 1120 of the following forms: | |
| 1121 constant N | |
| 1122 register ,X | |
| 1123 indexed N,X | |
| 1124 --------------------------------------------------------------*/ | |
| 1125 | |
| 1126 /* The range of index that is allowed by indirect addressing. */ | |
| 1127 | |
| 1128 #define VALID_MIN_OFFSET m68hc11_min_offset | |
| 1129 #define VALID_MAX_OFFSET m68hc11_max_offset | |
| 1130 | |
| 1131 /* The offset values which are allowed by the n,x and n,y addressing modes. | |
| 1132 Take into account the size of the mode because we may have to add | |
| 1133 a mode offset to access the lowest part of the data. | |
| 1134 (For example, for an SImode, the last valid offset is 252.) */ | |
| 1135 #define VALID_CONSTANT_OFFSET_P(X,MODE) \ | |
| 1136 (((GET_CODE (X) == CONST_INT) && \ | |
| 1137 ((INTVAL (X) >= VALID_MIN_OFFSET) \ | |
| 1138 && ((INTVAL (X) <= VALID_MAX_OFFSET \ | |
| 1139 - (HOST_WIDE_INT) (GET_MODE_SIZE (MODE) + 1))))) \ | |
| 1140 || (TARGET_M6812 \ | |
| 1141 && ((GET_CODE (X) == SYMBOL_REF) \ | |
| 1142 || GET_CODE (X) == LABEL_REF \ | |
| 1143 || GET_CODE (X) == CONST))) | |
| 1144 | |
| 1145 /* This is included to allow stack push/pop operations. Special hacks in the | |
| 1146 md and m6811.c files exist to support this. */ | |
| 1147 #define PUSH_POP_ADDRESS_P(X) \ | |
| 1148 (((GET_CODE (X) == PRE_DEC) || (GET_CODE (X) == POST_INC)) \ | |
| 1149 && SP_REG_P (XEXP (X, 0))) | |
| 1150 | |
| 1151 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its | |
| 1152 validity for a certain class. We have two alternate definitions for each | |
| 1153 of them. The usual definition accepts all pseudo regs; the other rejects | |
| 1154 them unless they have been allocated suitable hard regs. The symbol | |
| 1155 REG_OK_STRICT causes the latter definition to be used. | |
| 1156 | |
| 1157 Most source files want to accept pseudo regs in the hope that they will | |
| 1158 get allocated to the class that the insn wants them to be in. Source files | |
| 1159 for reload pass need to be strict. After reload, it makes no difference, | |
| 1160 since pseudo regs have been eliminated by then. */ | |
| 1161 | |
| 1162 #ifndef REG_OK_STRICT | |
| 1163 /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
| 1164 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X) | |
| 1165 | |
| 1166 /* Nonzero if X is a hard reg that can be used as an index. */ | |
| 1167 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X) | |
| 1168 #else | |
| 1169 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X) | |
| 1170 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X) | |
| 1171 #endif | |
| 1172 | |
| 1173 | |
| 1174 /* Nonzero if the constant value X is a legitimate general operand. | |
| 1175 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
| 1176 | |
| 1177 #define LEGITIMATE_CONSTANT_P(X) 1 | |
| 1178 | |
| 1179 | |
| 1180 /* Tell final.c how to eliminate redundant test instructions. */ | |
| 1181 | |
| 1182 #define NOTICE_UPDATE_CC(EXP, INSN) \ | |
| 1183 m68hc11_notice_update_cc ((EXP), (INSN)) | |
| 1184 | |
| 1185 /* Move costs between classes of registers */ | |
| 1186 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ | |
| 1187 (m68hc11_register_move_cost (MODE, CLASS1, CLASS2)) | |
| 1188 | |
| 1189 /* Move cost between register and memory. | |
| 1190 - Move to a 16-bit register is reasonable, | |
| 1191 - Move to a soft register can be expensive. */ | |
| 1192 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \ | |
| 1193 m68hc11_memory_move_cost ((MODE),(CLASS),(IN)) | |
| 1194 | |
| 1195 /* A C expression for the cost of a branch instruction. A value of 1 | |
| 1196 is the default; other values are interpreted relative to that. | |
| 1197 | |
| 1198 Pretend branches are cheap because GCC generates sub-optimal code | |
| 1199 for the default value. */ | |
| 1200 #define BRANCH_COST(speed_p, predictable_p) 0 | |
| 1201 | |
| 1202 /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
| 1203 #define SLOW_BYTE_ACCESS 0 | |
| 1204 | |
| 1205 /* It is as good to call a constant function address as to call an address | |
| 1206 kept in a register. */ | |
| 1207 #define NO_FUNCTION_CSE | |
| 1208 | |
| 1209 /* Try a machine-dependent way of reloading an illegitimate address | |
| 1210 operand. If we find one, push the reload and jump to WIN. This | |
| 1211 macro is used in only one place: `find_reloads_address' in reload.c. | |
| 1212 | |
| 1213 For M68HC11, we handle large displacements of a base register | |
| 1214 by splitting the addend across an addhi3 insn. | |
| 1215 | |
| 1216 For M68HC12, the 64K offset range is available. | |
| 1217 */ | |
| 1218 | |
| 1219 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
| 1220 do { \ | |
| 1221 /* We must recognize output that we have already generated ourselves. */ \ | |
| 1222 if (GET_CODE (X) == PLUS \ | |
| 1223 && GET_CODE (XEXP (X, 0)) == PLUS \ | |
| 1224 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ | |
| 1225 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ | |
| 1226 && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
| 1227 { \ | |
| 1228 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ | |
| 1229 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ | |
| 1230 OPNUM, TYPE); \ | |
| 1231 goto WIN; \ | |
| 1232 } \ | |
| 1233 if (GET_CODE (X) == PLUS \ | |
| 1234 && GET_CODE (XEXP (X, 0)) == REG \ | |
| 1235 && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
| 1236 && !VALID_CONSTANT_OFFSET_P (XEXP (X, 1), MODE)) \ | |
| 1237 { \ | |
| 1238 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
| 1239 HOST_WIDE_INT low, high; \ | |
| 1240 high = val & (~0x0FF); \ | |
| 1241 low = val & 0x00FF; \ | |
| 1242 if (low >= 256-15) { high += 16; low -= 16; } \ | |
| 1243 /* Reload the high part into a base reg; leave the low part \ | |
| 1244 in the mem directly. */ \ | |
| 1245 \ | |
| 1246 X = gen_rtx_PLUS (Pmode, \ | |
| 1247 gen_rtx_PLUS (Pmode, XEXP (X, 0), \ | |
| 1248 GEN_INT (high)), \ | |
| 1249 GEN_INT (low)); \ | |
| 1250 \ | |
| 1251 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ | |
| 1252 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ | |
| 1253 OPNUM, TYPE); \ | |
| 1254 goto WIN; \ | |
| 1255 } \ | |
| 1256 } while (0) | |
| 1257 | |
| 1258 | |
| 1259 /* Defining the Output Assembler Language. */ | |
| 1260 | |
| 1261 /* A default list of other sections which we might be "in" at any given | |
| 1262 time. For targets that use additional sections (e.g. .tdesc) you | |
| 1263 should override this definition in the target-specific file which | |
| 1264 includes this file. */ | |
| 1265 | |
| 1266 /* Output before read-only data. */ | |
| 1267 #define TEXT_SECTION_ASM_OP ("\t.sect\t.text") | |
| 1268 | |
| 1269 /* Output before writable data. */ | |
| 1270 #define DATA_SECTION_ASM_OP ("\t.sect\t.data") | |
| 1271 | |
| 1272 /* Output before uninitialized data. */ | |
| 1273 #define BSS_SECTION_ASM_OP ("\t.sect\t.bss") | |
| 1274 | |
| 1275 /* Define the pseudo-ops used to switch to the .ctors and .dtors sections. | |
| 1276 | |
| 1277 Same as config/elfos.h but don't mark these section SHF_WRITE since | |
| 1278 there is no shared library problem. */ | |
| 1279 #undef CTORS_SECTION_ASM_OP | |
| 1280 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\"" | |
| 1281 | |
| 1282 #undef DTORS_SECTION_ASM_OP | |
| 1283 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\"" | |
| 1284 | |
| 1285 #define TARGET_ASM_CONSTRUCTOR m68hc11_asm_out_constructor | |
| 1286 #define TARGET_ASM_DESTRUCTOR m68hc11_asm_out_destructor | |
| 1287 | |
| 1288 /* Comment character */ | |
| 1289 #define ASM_COMMENT_START ";" | |
| 1290 | |
| 1291 /* Output to assembler file text saying following lines | |
| 1292 may contain character constants, extra white space, comments, etc. */ | |
| 1293 #define ASM_APP_ON "; Begin inline assembler code\n#APP\n" | |
| 1294 | |
| 1295 /* Output to assembler file text saying following lines | |
| 1296 no longer contain unusual constructs. */ | |
| 1297 #define ASM_APP_OFF "; End of inline assembler code\n#NO_APP\n" | |
| 1298 | |
| 1299 /* Write the extra assembler code needed to declare a function properly. | |
| 1300 Some svr4 assemblers need to also have something extra said about the | |
| 1301 function's return value. We allow for that here. | |
| 1302 | |
| 1303 For 68HC12 we mark functions that return with 'rtc'. The linker | |
| 1304 will ensure that a 'call' is really made (instead of 'jsr'). | |
| 1305 The debugger needs this information to correctly compute the stack frame. | |
| 1306 | |
| 1307 For 68HC11/68HC12 we also mark interrupt handlers for gdb to | |
| 1308 compute the correct stack frame. */ | |
| 1309 | |
| 1310 #undef ASM_DECLARE_FUNCTION_NAME | |
| 1311 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ | |
| 1312 do \ | |
| 1313 { \ | |
| 1314 fprintf (FILE, "%s", TYPE_ASM_OP); \ | |
| 1315 assemble_name (FILE, NAME); \ | |
| 1316 putc (',', FILE); \ | |
| 1317 fprintf (FILE, TYPE_OPERAND_FMT, "function"); \ | |
| 1318 putc ('\n', FILE); \ | |
| 1319 \ | |
| 1320 if (current_function_far) \ | |
| 1321 { \ | |
| 1322 fprintf (FILE, "\t.far\t"); \ | |
| 1323 assemble_name (FILE, NAME); \ | |
| 1324 putc ('\n', FILE); \ | |
| 1325 } \ | |
| 1326 else if (current_function_interrupt \ | |
| 1327 || current_function_trap) \ | |
| 1328 { \ | |
| 1329 fprintf (FILE, "\t.interrupt\t"); \ | |
| 1330 assemble_name (FILE, NAME); \ | |
| 1331 putc ('\n', FILE); \ | |
| 1332 } \ | |
| 1333 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ | |
| 1334 ASM_OUTPUT_LABEL(FILE, NAME); \ | |
| 1335 } \ | |
| 1336 while (0) | |
| 1337 | |
| 1338 /* Output #ident as a .ident. */ | |
| 1339 | |
| 1340 /* output external reference */ | |
| 1341 #undef ASM_OUTPUT_EXTERNAL | |
| 1342 #define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) \ | |
| 1343 {fputs ("\t; extern\t", FILE); \ | |
| 1344 assemble_name (FILE, NAME); \ | |
| 1345 fputs ("\n", FILE);} | |
| 1346 | |
| 1347 /* How to refer to registers in assembler output. This sequence is indexed | |
| 1348 by compiler's hard-register-number (see above). */ | |
| 1349 #define REGISTER_NAMES \ | |
| 1350 { "x", "d", "y", "sp", "pc", "a", "b", "ccr", "z", \ | |
| 1351 "*_.frame", "*_.tmp", "*_.z", "*_.xy", "*fake clobber", \ | |
| 1352 SOFT_REG_NAMES, "*sframe", "*ap"} | |
| 1353 | |
| 1354 /* Print an instruction operand X on file FILE. CODE is the code from the | |
| 1355 %-spec for printing this operand. If `%z3' was used to print operand | |
| 1356 3, then CODE is 'z'. */ | |
| 1357 | |
| 1358 #define PRINT_OPERAND(FILE, X, CODE) \ | |
| 1359 print_operand (FILE, X, CODE) | |
| 1360 | |
| 1361 /* Print a memory operand whose address is X, on file FILE. */ | |
| 1362 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
| 1363 print_operand_address (FILE, ADDR) | |
| 1364 | |
| 1365 /* This is how to output an insn to push/pop a register on the stack. | |
| 1366 It need not be very fast code. | |
| 1367 | |
| 1368 Don't define because we don't know how to handle that with | |
| 1369 the STATIC_CHAIN_REGNUM (soft register). Saving the static | |
| 1370 chain must be made inside FUNCTION_PROFILER. */ | |
| 1371 | |
| 1372 #undef ASM_OUTPUT_REG_PUSH | |
| 1373 #undef ASM_OUTPUT_REG_POP | |
| 1374 | |
| 1375 /* This is how to output an element of a case-vector that is relative. */ | |
| 1376 | |
| 1377 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
| 1378 fprintf (FILE, "\t%s\tL%d-L%d\n", integer_asm_op (2, TRUE), VALUE, REL) | |
| 1379 | |
| 1380 /* This is how to output an element of a case-vector that is absolute. */ | |
| 1381 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
| 1382 fprintf (FILE, "\t%s\t.L%d\n", integer_asm_op (2, TRUE), VALUE) | |
| 1383 | |
| 1384 /* This is how to output an assembler line that says to advance the | |
| 1385 location counter to a multiple of 2**LOG bytes. */ | |
| 1386 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
| 1387 do { \ | |
| 1388 if ((LOG) > 1) \ | |
| 1389 fprintf ((FILE), "%s\n", ALIGN_ASM_OP); \ | |
| 1390 } while (0) | |
| 1391 | |
| 1392 | |
| 1393 /* Assembler Commands for Exception Regions. */ | |
| 1394 | |
| 1395 /* Default values provided by GCC should be ok. Assuming that DWARF-2 | |
| 1396 frame unwind info is ok for this platform. */ | |
| 1397 | |
| 1398 #undef PREFERRED_DEBUGGING_TYPE | |
| 1399 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG | |
| 1400 | |
| 1401 /* For the support of memory banks we need addresses that indicate | |
| 1402 the page number. */ | |
| 1403 #define DWARF2_ADDR_SIZE 4 | |
| 1404 | |
| 1405 /* SCz 2003-07-08: Don't use as dwarf2 .file/.loc directives because | |
| 1406 the linker is doing relaxation and it does not adjust the debug_line | |
| 1407 sections when it shrinks the code. This results in invalid addresses | |
| 1408 when debugging. This does not bless too much the HC11/HC12 as most | |
| 1409 applications are embedded and small, hence a reasonable debug info. | |
| 1410 This problem is known for binutils 2.13, 2.14 and mainline. */ | |
| 1411 #undef HAVE_AS_DWARF2_DEBUG_LINE | |
| 1412 | |
| 1413 /* The prefix for local labels. You should be able to define this as | |
| 1414 an empty string, or any arbitrary string (such as ".", ".L%", etc) | |
| 1415 without having to make any other changes to account for the specific | |
| 1416 definition. Note it is a string literal, not interpreted by printf | |
| 1417 and friends. */ | |
| 1418 #define LOCAL_LABEL_PREFIX "." | |
| 1419 | |
| 1420 /* The prefix for immediate operands. */ | |
| 1421 #define IMMEDIATE_PREFIX "#" | |
| 1422 #define GLOBAL_ASM_OP "\t.globl\t" | |
| 1423 | |
| 1424 | |
| 1425 /* Miscellaneous Parameters. */ | |
| 1426 | |
| 1427 /* Specify the machine mode that this machine uses | |
| 1428 for the index in the tablejump instruction. */ | |
| 1429 #define CASE_VECTOR_MODE Pmode | |
| 1430 | |
| 1431 /* This flag, if defined, says the same insns that convert to a signed fixnum | |
| 1432 also convert validly to an unsigned one. */ | |
| 1433 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC | |
| 1434 | |
| 1435 /* Max number of bytes we can move from memory to memory in one | |
| 1436 reasonably fast instruction. */ | |
| 1437 #define MOVE_MAX 2 | |
| 1438 | |
| 1439 /* MOVE_RATIO is the number of move instructions that is better than a | |
| 1440 block move. Make this small on 6811, since the code size grows very | |
| 1441 large with each move. */ | |
| 1442 #define MOVE_RATIO(speed) 3 | |
| 1443 | |
| 1444 /* Define if shifts truncate the shift count which implies one can omit | |
| 1445 a sign-extension or zero-extension of a shift count. */ | |
| 1446 #define SHIFT_COUNT_TRUNCATED 1 | |
| 1447 | |
| 1448 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
| 1449 is done just by pretending it is already truncated. */ | |
| 1450 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
| 1451 | |
| 1452 /* Specify the machine mode that pointers have. After generation of rtl, the | |
| 1453 compiler makes no further distinction between pointers and any other | |
| 1454 objects of this machine mode. */ | |
| 1455 #define Pmode HImode | |
| 1456 | |
| 1457 /* A function address in a call instruction is a byte address (for indexing | |
| 1458 purposes) so give the MEM rtx a byte's mode. */ | |
| 1459 #define FUNCTION_MODE QImode | |
| 1460 | |
| 1461 extern int debug_m6811; | |
| 1462 extern int z_replacement_completed; | |
| 1463 extern int current_function_interrupt; | |
| 1464 extern int current_function_trap; | |
| 1465 extern int current_function_far; | |
| 1466 | |
| 1467 extern GTY(()) rtx m68hc11_soft_tmp_reg; | |
| 1468 extern GTY(()) rtx ix_reg; | |
| 1469 extern GTY(()) rtx iy_reg; | |
| 1470 extern GTY(()) rtx d_reg; |