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annotate gcc/config/rs6000/constraints.md @ 63:b7f97abdc517 gcc-4.6-20100522
update gcc from gcc-4.5.0 to gcc-4.6
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Mon, 24 May 2010 12:47:05 +0900 |
| parents | 77e2b8dfacca |
| children | f6334be47118 |
| rev | line source |
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| 0 | 1 ;; Constraint definitions for RS6000 |
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2 ;; Copyright (C) 2006, 2007, 2009, 2010 Free Software Foundation, Inc. |
| 0 | 3 ;; |
| 4 ;; This file is part of GCC. | |
| 5 ;; | |
| 6 ;; GCC is free software; you can redistribute it and/or modify | |
| 7 ;; it under the terms of the GNU General Public License as published by | |
| 8 ;; the Free Software Foundation; either version 3, or (at your option) | |
| 9 ;; any later version. | |
| 10 ;; | |
| 11 ;; GCC is distributed in the hope that it will be useful, | |
| 12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 ;; GNU General Public License for more details. | |
| 15 ;; | |
| 16 ;; You should have received a copy of the GNU General Public License | |
| 17 ;; along with GCC; see the file COPYING3. If not see | |
| 18 ;; <http://www.gnu.org/licenses/>. | |
| 19 | |
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20 ;; Available constraint letters: "e", "k", "u", "A", "B", "C", "D" |
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21 |
| 0 | 22 ;; Register constraints |
| 23 | |
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24 (define_register_constraint "f" "rs6000_constraints[RS6000_CONSTRAINT_f]" |
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25 "@internal") |
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26 |
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27 (define_register_constraint "d" "rs6000_constraints[RS6000_CONSTRAINT_d]" |
| 0 | 28 "@internal") |
| 29 | |
| 30 (define_register_constraint "b" "BASE_REGS" | |
| 31 "@internal") | |
| 32 | |
| 33 (define_register_constraint "h" "SPECIAL_REGS" | |
| 34 "@internal") | |
| 35 | |
| 36 (define_register_constraint "q" "MQ_REGS" | |
| 37 "@internal") | |
| 38 | |
| 39 (define_register_constraint "c" "CTR_REGS" | |
| 40 "@internal") | |
| 41 | |
| 42 (define_register_constraint "l" "LINK_REGS" | |
| 43 "@internal") | |
| 44 | |
| 45 (define_register_constraint "v" "ALTIVEC_REGS" | |
| 46 "@internal") | |
| 47 | |
| 48 (define_register_constraint "x" "CR0_REGS" | |
| 49 "@internal") | |
| 50 | |
| 51 (define_register_constraint "y" "CR_REGS" | |
| 52 "@internal") | |
| 53 | |
| 54 (define_register_constraint "z" "XER_REGS" | |
| 55 "@internal") | |
| 56 | |
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57 ;; Use w as a prefix to add VSX modes |
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58 ;; vector double (V2DF) |
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59 (define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]" |
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60 "@internal") |
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61 |
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62 ;; vector float (V4SF) |
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63 (define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]" |
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64 "@internal") |
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65 |
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66 ;; scalar double (DF) |
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67 (define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]" |
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68 "@internal") |
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69 |
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70 ;; any VSX register |
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71 (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]" |
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72 "@internal") |
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73 |
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74 ;; Altivec style load/store that ignores the bottom bits of the address |
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75 (define_memory_constraint "wZ" |
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76 "Indexed or indirect memory operand, ignoring the bottom 4 bits" |
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77 (match_operand 0 "altivec_indexed_or_indirect_operand")) |
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78 |
| 0 | 79 ;; Integer constraints |
| 80 | |
| 81 (define_constraint "I" | |
| 82 "A signed 16-bit constant" | |
| 83 (and (match_code "const_int") | |
| 84 (match_test "(unsigned HOST_WIDE_INT) (ival + 0x8000) < 0x10000"))) | |
| 85 | |
| 86 (define_constraint "J" | |
| 87 "high-order 16 bits nonzero" | |
| 88 (and (match_code "const_int") | |
| 89 (match_test "(ival & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0"))) | |
| 90 | |
| 91 (define_constraint "K" | |
| 92 "low-order 16 bits nonzero" | |
| 93 (and (match_code "const_int") | |
| 94 (match_test "(ival & (~ (HOST_WIDE_INT) 0xffff)) == 0"))) | |
| 95 | |
| 96 (define_constraint "L" | |
| 97 "signed 16-bit constant shifted left 16 bits" | |
| 98 (and (match_code "const_int") | |
| 99 (match_test "((ival & 0xffff) == 0 | |
| 100 && (ival >> 31 == -1 || ival >> 31 == 0))"))) | |
| 101 | |
| 102 (define_constraint "M" | |
| 103 "constant greater than 31" | |
| 104 (and (match_code "const_int") | |
| 105 (match_test "ival > 31"))) | |
| 106 | |
| 107 (define_constraint "N" | |
| 108 "positive constant that is an exact power of two" | |
| 109 (and (match_code "const_int") | |
| 110 (match_test "ival > 0 && exact_log2 (ival) >= 0"))) | |
| 111 | |
| 112 (define_constraint "O" | |
| 113 "constant zero" | |
| 114 (and (match_code "const_int") | |
| 115 (match_test "ival == 0"))) | |
| 116 | |
| 117 (define_constraint "P" | |
| 118 "constant whose negation is signed 16-bit constant" | |
| 119 (and (match_code "const_int") | |
| 120 (match_test "(unsigned HOST_WIDE_INT) ((- ival) + 0x8000) < 0x10000"))) | |
| 121 | |
| 122 ;; Floating-point constraints | |
| 123 | |
| 124 (define_constraint "G" | |
| 125 "Constant that can be copied into GPR with two insns for DF/DI | |
| 126 and one for SF." | |
| 127 (and (match_code "const_double") | |
| 128 (match_test "num_insns_constant (op, mode) | |
| 129 == (mode == SFmode ? 1 : 2)"))) | |
| 130 | |
| 131 (define_constraint "H" | |
| 132 "DF/DI constant that takes three insns." | |
| 133 (and (match_code "const_double") | |
| 134 (match_test "num_insns_constant (op, mode) == 3"))) | |
| 135 | |
| 136 ;; Memory constraints | |
| 137 | |
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138 (define_memory_constraint "es" |
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139 "A ``stable'' memory operand; that is, one which does not include any |
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140 automodification of the base register. Unlike @samp{m}, this constraint |
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141 can be used in @code{asm} statements that might access the operand |
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142 several times, or that might not access it at all." |
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143 (and (match_code "mem") |
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144 (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC"))) |
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145 |
| 0 | 146 (define_memory_constraint "Q" |
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147 "Memory operand that is an offset from a register (it is usually better |
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148 to use @samp{m} or @samp{es} in @code{asm} statements)" |
| 0 | 149 (and (match_code "mem") |
| 150 (match_test "GET_CODE (XEXP (op, 0)) == REG"))) | |
| 151 | |
| 152 (define_memory_constraint "Y" | |
| 153 "Indexed or word-aligned displacement memory operand" | |
| 154 (match_operand 0 "word_offset_memref_operand")) | |
| 155 | |
| 156 (define_memory_constraint "Z" | |
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157 "Memory operand that is an indexed or indirect from a register (it is |
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158 usually better to use @samp{m} or @samp{es} in @code{asm} statements)" |
| 0 | 159 (match_operand 0 "indexed_or_indirect_operand")) |
| 160 | |
| 161 ;; Address constraints | |
| 162 | |
| 163 (define_address_constraint "a" | |
| 164 "Indexed or indirect address operand" | |
| 165 (match_operand 0 "indexed_or_indirect_address")) | |
| 166 | |
| 167 (define_constraint "R" | |
| 168 "AIX TOC entry" | |
| 169 (match_test "legitimate_constant_pool_address_p (op)")) | |
| 170 | |
| 171 ;; General constraints | |
| 172 | |
| 173 (define_constraint "S" | |
| 174 "Constant that can be placed into a 64-bit mask operand" | |
| 175 (match_operand 0 "mask64_operand")) | |
| 176 | |
| 177 (define_constraint "T" | |
| 178 "Constant that can be placed into a 32-bit mask operand" | |
| 179 (match_operand 0 "mask_operand")) | |
| 180 | |
| 181 (define_constraint "U" | |
| 182 "V.4 small data reference" | |
| 183 (and (match_test "DEFAULT_ABI == ABI_V4") | |
| 184 (match_operand 0 "small_data_operand"))) | |
| 185 | |
| 186 (define_constraint "t" | |
| 187 "AND masks that can be performed by two rldic{l,r} insns | |
| 188 (but excluding those that could match other constraints of anddi3)" | |
| 189 (and (and (and (match_operand 0 "mask64_2_operand") | |
| 190 (match_test "(fixed_regs[CR0_REGNO] | |
| 191 || !logical_operand (op, DImode))")) | |
| 192 (not (match_operand 0 "mask_operand"))) | |
| 193 (not (match_operand 0 "mask64_operand")))) | |
| 194 | |
| 195 (define_constraint "W" | |
| 196 "vector constant that does not require memory" | |
| 197 (match_operand 0 "easy_vector_constant")) | |
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198 |
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199 (define_constraint "j" |
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200 "Zero vector constant" |
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201 (match_test "(op == const0_rtx || op == CONST0_RTX (GET_MODE (op)))")) |