Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/xtensa/xtensa.c @ 63:b7f97abdc517 gcc-4.6-20100522
update gcc from gcc-4.5.0 to gcc-4.6
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Mon, 24 May 2010 12:47:05 +0900 |
| parents | 77e2b8dfacca |
| children | f6334be47118 |
| rev | line source |
|---|---|
| 0 | 1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture. |
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2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
| 0 | 3 Free Software Foundation, Inc. |
| 4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. | |
| 5 | |
| 6 This file is part of GCC. | |
| 7 | |
| 8 GCC is free software; you can redistribute it and/or modify it under | |
| 9 the terms of the GNU General Public License as published by the Free | |
| 10 Software Foundation; either version 3, or (at your option) any later | |
| 11 version. | |
| 12 | |
| 13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 14 WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 16 for more details. | |
| 17 | |
| 18 You should have received a copy of the GNU General Public License | |
| 19 along with GCC; see the file COPYING3. If not see | |
| 20 <http://www.gnu.org/licenses/>. */ | |
| 21 | |
| 22 #include "config.h" | |
| 23 #include "system.h" | |
| 24 #include "coretypes.h" | |
| 25 #include "tm.h" | |
| 26 #include "rtl.h" | |
| 27 #include "regs.h" | |
| 28 #include "hard-reg-set.h" | |
| 29 #include "basic-block.h" | |
| 30 #include "insn-config.h" | |
| 31 #include "conditions.h" | |
| 32 #include "insn-flags.h" | |
| 33 #include "insn-attr.h" | |
| 34 #include "insn-codes.h" | |
| 35 #include "recog.h" | |
| 36 #include "output.h" | |
| 37 #include "tree.h" | |
| 38 #include "expr.h" | |
| 39 #include "flags.h" | |
| 40 #include "reload.h" | |
| 41 #include "tm_p.h" | |
| 42 #include "function.h" | |
| 43 #include "toplev.h" | |
| 44 #include "optabs.h" | |
| 45 #include "libfuncs.h" | |
| 46 #include "ggc.h" | |
| 47 #include "target.h" | |
| 48 #include "target-def.h" | |
| 49 #include "langhooks.h" | |
| 50 #include "gimple.h" | |
| 51 #include "df.h" | |
| 52 | |
| 53 | |
| 54 /* Enumeration for all of the relational tests, so that we can build | |
| 55 arrays indexed by the test type, and not worry about the order | |
| 56 of EQ, NE, etc. */ | |
| 57 | |
| 58 enum internal_test | |
| 59 { | |
| 60 ITEST_EQ, | |
| 61 ITEST_NE, | |
| 62 ITEST_GT, | |
| 63 ITEST_GE, | |
| 64 ITEST_LT, | |
| 65 ITEST_LE, | |
| 66 ITEST_GTU, | |
| 67 ITEST_GEU, | |
| 68 ITEST_LTU, | |
| 69 ITEST_LEU, | |
| 70 ITEST_MAX | |
| 71 }; | |
| 72 | |
| 73 /* Array giving truth value on whether or not a given hard register | |
| 74 can support a given mode. */ | |
| 75 char xtensa_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; | |
| 76 | |
| 77 /* Current frame size calculated by compute_frame_size. */ | |
| 78 unsigned xtensa_current_frame_size; | |
| 79 | |
| 80 /* Largest block move to handle in-line. */ | |
| 81 #define LARGEST_MOVE_RATIO 15 | |
| 82 | |
| 83 /* Define the structure for the machine field in struct function. */ | |
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84 struct GTY(()) machine_function |
| 0 | 85 { |
| 86 int accesses_prev_frame; | |
| 87 bool need_a7_copy; | |
| 88 bool vararg_a7; | |
| 89 rtx vararg_a7_copy; | |
| 90 rtx set_frame_ptr_insn; | |
| 91 }; | |
| 92 | |
| 93 /* Vector, indexed by hard register number, which contains 1 for a | |
| 94 register that is allowable in a candidate for leaf function | |
| 95 treatment. */ | |
| 96 | |
| 97 const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] = | |
| 98 { | |
| 99 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, | |
| 100 1, 1, 1, | |
| 101 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, | |
| 102 1 | |
| 103 }; | |
| 104 | |
| 105 /* Map hard register number to register class */ | |
| 106 const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER] = | |
| 107 { | |
| 108 RL_REGS, SP_REG, RL_REGS, RL_REGS, | |
| 109 RL_REGS, RL_REGS, RL_REGS, GR_REGS, | |
| 110 RL_REGS, RL_REGS, RL_REGS, RL_REGS, | |
| 111 RL_REGS, RL_REGS, RL_REGS, RL_REGS, | |
| 112 AR_REGS, AR_REGS, BR_REGS, | |
| 113 FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
| 114 FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
| 115 FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
| 116 FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
| 117 ACC_REG, | |
| 118 }; | |
| 119 | |
| 120 static enum internal_test map_test_to_internal_test (enum rtx_code); | |
| 121 static rtx gen_int_relational (enum rtx_code, rtx, rtx, int *); | |
| 122 static rtx gen_float_relational (enum rtx_code, rtx, rtx); | |
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123 static rtx gen_conditional_move (enum rtx_code, enum machine_mode, rtx, rtx); |
| 0 | 124 static rtx fixup_subreg_mem (rtx); |
| 125 static struct machine_function * xtensa_init_machine_status (void); | |
| 126 static rtx xtensa_legitimize_tls_address (rtx); | |
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127 static rtx xtensa_legitimize_address (rtx, rtx, enum machine_mode); |
| 0 | 128 static bool xtensa_return_in_msb (const_tree); |
| 129 static void printx (FILE *, signed int); | |
| 130 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT); | |
| 131 static rtx xtensa_builtin_saveregs (void); | |
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132 static bool xtensa_legitimate_address_p (enum machine_mode, rtx, bool); |
| 0 | 133 static unsigned int xtensa_multibss_section_type_flags (tree, const char *, |
| 134 int) ATTRIBUTE_UNUSED; | |
| 135 static section *xtensa_select_rtx_section (enum machine_mode, rtx, | |
| 136 unsigned HOST_WIDE_INT); | |
| 137 static bool xtensa_rtx_costs (rtx, int, int, int *, bool); | |
| 138 static tree xtensa_build_builtin_va_list (void); | |
| 139 static bool xtensa_return_in_memory (const_tree, const_tree); | |
| 140 static tree xtensa_gimplify_va_arg_expr (tree, tree, gimple_seq *, | |
| 141 gimple_seq *); | |
| 142 static rtx xtensa_function_value (const_tree, const_tree, bool); | |
| 143 static void xtensa_init_builtins (void); | |
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144 static tree xtensa_fold_builtin (tree, int, tree *, bool); |
| 0 | 145 static rtx xtensa_expand_builtin (tree, rtx, rtx, enum machine_mode, int); |
| 146 static void xtensa_va_start (tree, rtx); | |
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147 static bool xtensa_frame_pointer_required (void); |
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148 static rtx xtensa_static_chain (const_tree, bool); |
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149 static void xtensa_asm_trampoline_template (FILE *); |
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150 static void xtensa_trampoline_init (rtx, tree, rtx); |
| 0 | 151 |
| 152 static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] = | |
| 153 REG_ALLOC_ORDER; | |
| 154 | |
| 155 | |
| 156 /* This macro generates the assembly code for function exit, | |
| 157 on machines that need it. If FUNCTION_EPILOGUE is not defined | |
| 158 then individual return instructions are generated for each | |
| 159 return statement. Args are same as for FUNCTION_PROLOGUE. */ | |
| 160 | |
| 161 #undef TARGET_ASM_FUNCTION_EPILOGUE | |
| 162 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue | |
| 163 | |
| 164 /* These hooks specify assembly directives for creating certain kinds | |
| 165 of integer object. */ | |
| 166 | |
| 167 #undef TARGET_ASM_ALIGNED_SI_OP | |
| 168 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
| 169 | |
| 170 #undef TARGET_ASM_SELECT_RTX_SECTION | |
| 171 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section | |
| 172 | |
| 173 #undef TARGET_DEFAULT_TARGET_FLAGS | |
| 174 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD) | |
| 175 | |
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176 #undef TARGET_LEGITIMIZE_ADDRESS |
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177 #define TARGET_LEGITIMIZE_ADDRESS xtensa_legitimize_address |
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178 |
| 0 | 179 #undef TARGET_RTX_COSTS |
| 180 #define TARGET_RTX_COSTS xtensa_rtx_costs | |
| 181 #undef TARGET_ADDRESS_COST | |
| 182 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0 | |
| 183 | |
| 184 #undef TARGET_BUILD_BUILTIN_VA_LIST | |
| 185 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list | |
| 186 | |
| 187 #undef TARGET_EXPAND_BUILTIN_VA_START | |
| 188 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start | |
| 189 | |
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190 #undef TARGET_PROMOTE_FUNCTION_MODE |
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191 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote |
| 0 | 192 #undef TARGET_PROMOTE_PROTOTYPES |
| 193 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true | |
| 194 | |
| 195 #undef TARGET_RETURN_IN_MEMORY | |
| 196 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory | |
| 197 #undef TARGET_FUNCTION_VALUE | |
| 198 #define TARGET_FUNCTION_VALUE xtensa_function_value | |
| 199 #undef TARGET_SPLIT_COMPLEX_ARG | |
| 200 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true | |
| 201 #undef TARGET_MUST_PASS_IN_STACK | |
| 202 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
| 203 | |
| 204 #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
| 205 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs | |
| 206 #undef TARGET_GIMPLIFY_VA_ARG_EXPR | |
| 207 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr | |
| 208 | |
| 209 #undef TARGET_RETURN_IN_MSB | |
| 210 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb | |
| 211 | |
| 212 #undef TARGET_INIT_BUILTINS | |
| 213 #define TARGET_INIT_BUILTINS xtensa_init_builtins | |
| 214 #undef TARGET_FOLD_BUILTIN | |
| 215 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin | |
| 216 #undef TARGET_EXPAND_BUILTIN | |
| 217 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin | |
| 218 | |
| 219 #undef TARGET_SECONDARY_RELOAD | |
| 220 #define TARGET_SECONDARY_RELOAD xtensa_secondary_reload | |
| 221 | |
| 222 #undef TARGET_HAVE_TLS | |
| 223 #define TARGET_HAVE_TLS (TARGET_THREADPTR && HAVE_AS_TLS) | |
| 224 | |
| 225 #undef TARGET_CANNOT_FORCE_CONST_MEM | |
| 226 #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_tls_referenced_p | |
| 227 | |
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228 #undef TARGET_LEGITIMATE_ADDRESS_P |
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229 #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p |
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230 |
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231 #undef TARGET_FRAME_POINTER_REQUIRED |
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232 #define TARGET_FRAME_POINTER_REQUIRED xtensa_frame_pointer_required |
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233 |
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234 #undef TARGET_STATIC_CHAIN |
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235 #define TARGET_STATIC_CHAIN xtensa_static_chain |
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236 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
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237 #define TARGET_ASM_TRAMPOLINE_TEMPLATE xtensa_asm_trampoline_template |
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238 #undef TARGET_TRAMPOLINE_INIT |
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239 #define TARGET_TRAMPOLINE_INIT xtensa_trampoline_init |
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240 |
| 0 | 241 struct gcc_target targetm = TARGET_INITIALIZER; |
| 242 | |
| 243 | |
| 244 /* Functions to test Xtensa immediate operand validity. */ | |
| 245 | |
| 246 bool | |
| 247 xtensa_simm8 (HOST_WIDE_INT v) | |
| 248 { | |
| 249 return v >= -128 && v <= 127; | |
| 250 } | |
| 251 | |
| 252 | |
| 253 bool | |
| 254 xtensa_simm8x256 (HOST_WIDE_INT v) | |
| 255 { | |
| 256 return (v & 255) == 0 && (v >= -32768 && v <= 32512); | |
| 257 } | |
| 258 | |
| 259 | |
| 260 bool | |
| 261 xtensa_simm12b (HOST_WIDE_INT v) | |
| 262 { | |
| 263 return v >= -2048 && v <= 2047; | |
| 264 } | |
| 265 | |
| 266 | |
| 267 static bool | |
| 268 xtensa_uimm8 (HOST_WIDE_INT v) | |
| 269 { | |
| 270 return v >= 0 && v <= 255; | |
| 271 } | |
| 272 | |
| 273 | |
| 274 static bool | |
| 275 xtensa_uimm8x2 (HOST_WIDE_INT v) | |
| 276 { | |
| 277 return (v & 1) == 0 && (v >= 0 && v <= 510); | |
| 278 } | |
| 279 | |
| 280 | |
| 281 static bool | |
| 282 xtensa_uimm8x4 (HOST_WIDE_INT v) | |
| 283 { | |
| 284 return (v & 3) == 0 && (v >= 0 && v <= 1020); | |
| 285 } | |
| 286 | |
| 287 | |
| 288 static bool | |
| 289 xtensa_b4const (HOST_WIDE_INT v) | |
| 290 { | |
| 291 switch (v) | |
| 292 { | |
| 293 case -1: | |
| 294 case 1: | |
| 295 case 2: | |
| 296 case 3: | |
| 297 case 4: | |
| 298 case 5: | |
| 299 case 6: | |
| 300 case 7: | |
| 301 case 8: | |
| 302 case 10: | |
| 303 case 12: | |
| 304 case 16: | |
| 305 case 32: | |
| 306 case 64: | |
| 307 case 128: | |
| 308 case 256: | |
| 309 return true; | |
| 310 } | |
| 311 return false; | |
| 312 } | |
| 313 | |
| 314 | |
| 315 bool | |
| 316 xtensa_b4const_or_zero (HOST_WIDE_INT v) | |
| 317 { | |
| 318 if (v == 0) | |
| 319 return true; | |
| 320 return xtensa_b4const (v); | |
| 321 } | |
| 322 | |
| 323 | |
| 324 bool | |
| 325 xtensa_b4constu (HOST_WIDE_INT v) | |
| 326 { | |
| 327 switch (v) | |
| 328 { | |
| 329 case 32768: | |
| 330 case 65536: | |
| 331 case 2: | |
| 332 case 3: | |
| 333 case 4: | |
| 334 case 5: | |
| 335 case 6: | |
| 336 case 7: | |
| 337 case 8: | |
| 338 case 10: | |
| 339 case 12: | |
| 340 case 16: | |
| 341 case 32: | |
| 342 case 64: | |
| 343 case 128: | |
| 344 case 256: | |
| 345 return true; | |
| 346 } | |
| 347 return false; | |
| 348 } | |
| 349 | |
| 350 | |
| 351 bool | |
| 352 xtensa_mask_immediate (HOST_WIDE_INT v) | |
| 353 { | |
| 354 #define MAX_MASK_SIZE 16 | |
| 355 int mask_size; | |
| 356 | |
| 357 for (mask_size = 1; mask_size <= MAX_MASK_SIZE; mask_size++) | |
| 358 { | |
| 359 if ((v & 1) == 0) | |
| 360 return false; | |
| 361 v = v >> 1; | |
| 362 if (v == 0) | |
| 363 return true; | |
| 364 } | |
| 365 | |
| 366 return false; | |
| 367 } | |
| 368 | |
| 369 | |
| 370 /* This is just like the standard true_regnum() function except that it | |
| 371 works even when reg_renumber is not initialized. */ | |
| 372 | |
| 373 int | |
| 374 xt_true_regnum (rtx x) | |
| 375 { | |
| 376 if (GET_CODE (x) == REG) | |
| 377 { | |
| 378 if (reg_renumber | |
| 379 && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
| 380 && reg_renumber[REGNO (x)] >= 0) | |
| 381 return reg_renumber[REGNO (x)]; | |
| 382 return REGNO (x); | |
| 383 } | |
| 384 if (GET_CODE (x) == SUBREG) | |
| 385 { | |
| 386 int base = xt_true_regnum (SUBREG_REG (x)); | |
| 387 if (base >= 0 && base < FIRST_PSEUDO_REGISTER) | |
| 388 return base + subreg_regno_offset (REGNO (SUBREG_REG (x)), | |
| 389 GET_MODE (SUBREG_REG (x)), | |
| 390 SUBREG_BYTE (x), GET_MODE (x)); | |
| 391 } | |
| 392 return -1; | |
| 393 } | |
| 394 | |
| 395 | |
| 396 int | |
| 397 xtensa_valid_move (enum machine_mode mode, rtx *operands) | |
| 398 { | |
| 399 /* Either the destination or source must be a register, and the | |
| 400 MAC16 accumulator doesn't count. */ | |
| 401 | |
| 402 if (register_operand (operands[0], mode)) | |
| 403 { | |
| 404 int dst_regnum = xt_true_regnum (operands[0]); | |
| 405 | |
| 406 /* The stack pointer can only be assigned with a MOVSP opcode. */ | |
| 407 if (dst_regnum == STACK_POINTER_REGNUM) | |
| 408 return (mode == SImode | |
| 409 && register_operand (operands[1], mode) | |
| 410 && !ACC_REG_P (xt_true_regnum (operands[1]))); | |
| 411 | |
| 412 if (!ACC_REG_P (dst_regnum)) | |
| 413 return true; | |
| 414 } | |
| 415 if (register_operand (operands[1], mode)) | |
| 416 { | |
| 417 int src_regnum = xt_true_regnum (operands[1]); | |
| 418 if (!ACC_REG_P (src_regnum)) | |
| 419 return true; | |
| 420 } | |
| 421 return FALSE; | |
| 422 } | |
| 423 | |
| 424 | |
| 425 int | |
| 426 smalloffset_mem_p (rtx op) | |
| 427 { | |
| 428 if (GET_CODE (op) == MEM) | |
| 429 { | |
| 430 rtx addr = XEXP (op, 0); | |
| 431 if (GET_CODE (addr) == REG) | |
| 432 return BASE_REG_P (addr, 0); | |
| 433 if (GET_CODE (addr) == PLUS) | |
| 434 { | |
| 435 rtx offset = XEXP (addr, 0); | |
| 436 HOST_WIDE_INT val; | |
| 437 if (GET_CODE (offset) != CONST_INT) | |
| 438 offset = XEXP (addr, 1); | |
| 439 if (GET_CODE (offset) != CONST_INT) | |
| 440 return FALSE; | |
| 441 | |
| 442 val = INTVAL (offset); | |
| 443 return (val & 3) == 0 && (val >= 0 && val <= 60); | |
| 444 } | |
| 445 } | |
| 446 return FALSE; | |
| 447 } | |
| 448 | |
| 449 | |
| 450 int | |
| 451 constantpool_address_p (rtx addr) | |
| 452 { | |
| 453 rtx sym = addr; | |
| 454 | |
| 455 if (GET_CODE (addr) == CONST) | |
| 456 { | |
| 457 rtx offset; | |
| 458 | |
| 459 /* Only handle (PLUS (SYM, OFFSET)) form. */ | |
| 460 addr = XEXP (addr, 0); | |
| 461 if (GET_CODE (addr) != PLUS) | |
| 462 return FALSE; | |
| 463 | |
| 464 /* Make sure the address is word aligned. */ | |
| 465 offset = XEXP (addr, 1); | |
| 466 if ((GET_CODE (offset) != CONST_INT) | |
| 467 || ((INTVAL (offset) & 3) != 0)) | |
| 468 return FALSE; | |
| 469 | |
| 470 sym = XEXP (addr, 0); | |
| 471 } | |
| 472 | |
| 473 if ((GET_CODE (sym) == SYMBOL_REF) | |
| 474 && CONSTANT_POOL_ADDRESS_P (sym)) | |
| 475 return TRUE; | |
| 476 return FALSE; | |
| 477 } | |
| 478 | |
| 479 | |
| 480 int | |
| 481 constantpool_mem_p (rtx op) | |
| 482 { | |
| 483 if (GET_CODE (op) == SUBREG) | |
| 484 op = SUBREG_REG (op); | |
| 485 if (GET_CODE (op) == MEM) | |
| 486 return constantpool_address_p (XEXP (op, 0)); | |
| 487 return FALSE; | |
| 488 } | |
| 489 | |
| 490 | |
| 491 /* Return TRUE if X is a thread-local symbol. */ | |
| 492 | |
| 493 static bool | |
| 494 xtensa_tls_symbol_p (rtx x) | |
| 495 { | |
| 496 if (! TARGET_HAVE_TLS) | |
| 497 return false; | |
| 498 | |
| 499 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0; | |
| 500 } | |
| 501 | |
| 502 | |
| 503 void | |
| 504 xtensa_extend_reg (rtx dst, rtx src) | |
| 505 { | |
| 506 rtx temp = gen_reg_rtx (SImode); | |
| 507 rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src))); | |
| 508 | |
| 509 /* Generate paradoxical subregs as needed so that the modes match. */ | |
| 510 src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0); | |
| 511 dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0); | |
| 512 | |
| 513 emit_insn (gen_ashlsi3 (temp, src, shift)); | |
| 514 emit_insn (gen_ashrsi3 (dst, temp, shift)); | |
| 515 } | |
| 516 | |
| 517 | |
| 518 bool | |
| 519 xtensa_mem_offset (unsigned v, enum machine_mode mode) | |
| 520 { | |
| 521 switch (mode) | |
| 522 { | |
| 523 case BLKmode: | |
| 524 /* Handle the worst case for block moves. See xtensa_expand_block_move | |
| 525 where we emit an optimized block move operation if the block can be | |
| 526 moved in < "move_ratio" pieces. The worst case is when the block is | |
| 527 aligned but has a size of (3 mod 4) (does this happen?) so that the | |
| 528 last piece requires a byte load/store. */ | |
| 529 return (xtensa_uimm8 (v) | |
| 530 && xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO)); | |
| 531 | |
| 532 case QImode: | |
| 533 return xtensa_uimm8 (v); | |
| 534 | |
| 535 case HImode: | |
| 536 return xtensa_uimm8x2 (v); | |
| 537 | |
| 538 case DFmode: | |
| 539 return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4)); | |
| 540 | |
| 541 default: | |
| 542 break; | |
| 543 } | |
| 544 | |
| 545 return xtensa_uimm8x4 (v); | |
| 546 } | |
| 547 | |
| 548 | |
| 549 /* Make normal rtx_code into something we can index from an array. */ | |
| 550 | |
| 551 static enum internal_test | |
| 552 map_test_to_internal_test (enum rtx_code test_code) | |
| 553 { | |
| 554 enum internal_test test = ITEST_MAX; | |
| 555 | |
| 556 switch (test_code) | |
| 557 { | |
| 558 default: break; | |
| 559 case EQ: test = ITEST_EQ; break; | |
| 560 case NE: test = ITEST_NE; break; | |
| 561 case GT: test = ITEST_GT; break; | |
| 562 case GE: test = ITEST_GE; break; | |
| 563 case LT: test = ITEST_LT; break; | |
| 564 case LE: test = ITEST_LE; break; | |
| 565 case GTU: test = ITEST_GTU; break; | |
| 566 case GEU: test = ITEST_GEU; break; | |
| 567 case LTU: test = ITEST_LTU; break; | |
| 568 case LEU: test = ITEST_LEU; break; | |
| 569 } | |
| 570 | |
| 571 return test; | |
| 572 } | |
| 573 | |
| 574 | |
| 575 /* Generate the code to compare two integer values. The return value is | |
| 576 the comparison expression. */ | |
| 577 | |
| 578 static rtx | |
| 579 gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */ | |
| 580 rtx cmp0, /* first operand to compare */ | |
| 581 rtx cmp1, /* second operand to compare */ | |
| 582 int *p_invert /* whether branch needs to reverse test */) | |
| 583 { | |
| 584 struct cmp_info | |
| 585 { | |
| 586 enum rtx_code test_code; /* test code to use in insn */ | |
| 587 bool (*const_range_p) (HOST_WIDE_INT); /* range check function */ | |
| 588 int const_add; /* constant to add (convert LE -> LT) */ | |
| 589 int reverse_regs; /* reverse registers in test */ | |
| 590 int invert_const; /* != 0 if invert value if cmp1 is constant */ | |
| 591 int invert_reg; /* != 0 if invert value if cmp1 is register */ | |
| 592 int unsignedp; /* != 0 for unsigned comparisons. */ | |
| 593 }; | |
| 594 | |
| 595 static struct cmp_info info[ (int)ITEST_MAX ] = { | |
| 596 | |
| 597 { EQ, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* EQ */ | |
| 598 { NE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* NE */ | |
| 599 | |
| 600 { LT, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* GT */ | |
| 601 { GE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* GE */ | |
| 602 { LT, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* LT */ | |
| 603 { GE, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* LE */ | |
| 604 | |
| 605 { LTU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* GTU */ | |
| 606 { GEU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* GEU */ | |
| 607 { LTU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* LTU */ | |
| 608 { GEU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* LEU */ | |
| 609 }; | |
| 610 | |
| 611 enum internal_test test; | |
| 612 enum machine_mode mode; | |
| 613 struct cmp_info *p_info; | |
| 614 | |
| 615 test = map_test_to_internal_test (test_code); | |
| 616 gcc_assert (test != ITEST_MAX); | |
| 617 | |
| 618 p_info = &info[ (int)test ]; | |
| 619 | |
| 620 mode = GET_MODE (cmp0); | |
| 621 if (mode == VOIDmode) | |
| 622 mode = GET_MODE (cmp1); | |
| 623 | |
| 624 /* Make sure we can handle any constants given to us. */ | |
| 625 if (GET_CODE (cmp1) == CONST_INT) | |
| 626 { | |
| 627 HOST_WIDE_INT value = INTVAL (cmp1); | |
| 628 unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value; | |
| 629 | |
| 630 /* if the immediate overflows or does not fit in the immediate field, | |
| 631 spill it to a register */ | |
| 632 | |
| 633 if ((p_info->unsignedp ? | |
| 634 (uvalue + p_info->const_add > uvalue) : | |
| 635 (value + p_info->const_add > value)) != (p_info->const_add > 0)) | |
| 636 { | |
| 637 cmp1 = force_reg (mode, cmp1); | |
| 638 } | |
| 639 else if (!(p_info->const_range_p) (value + p_info->const_add)) | |
| 640 { | |
| 641 cmp1 = force_reg (mode, cmp1); | |
| 642 } | |
| 643 } | |
| 644 else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG)) | |
| 645 { | |
| 646 cmp1 = force_reg (mode, cmp1); | |
| 647 } | |
| 648 | |
| 649 /* See if we need to invert the result. */ | |
| 650 *p_invert = ((GET_CODE (cmp1) == CONST_INT) | |
| 651 ? p_info->invert_const | |
| 652 : p_info->invert_reg); | |
| 653 | |
| 654 /* Comparison to constants, may involve adding 1 to change a LT into LE. | |
| 655 Comparison between two registers, may involve switching operands. */ | |
| 656 if (GET_CODE (cmp1) == CONST_INT) | |
| 657 { | |
| 658 if (p_info->const_add != 0) | |
| 659 cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add); | |
| 660 | |
| 661 } | |
| 662 else if (p_info->reverse_regs) | |
| 663 { | |
| 664 rtx temp = cmp0; | |
| 665 cmp0 = cmp1; | |
| 666 cmp1 = temp; | |
| 667 } | |
| 668 | |
| 669 return gen_rtx_fmt_ee (p_info->test_code, VOIDmode, cmp0, cmp1); | |
| 670 } | |
| 671 | |
| 672 | |
| 673 /* Generate the code to compare two float values. The return value is | |
| 674 the comparison expression. */ | |
| 675 | |
| 676 static rtx | |
| 677 gen_float_relational (enum rtx_code test_code, /* relational test (EQ, etc) */ | |
| 678 rtx cmp0, /* first operand to compare */ | |
| 679 rtx cmp1 /* second operand to compare */) | |
| 680 { | |
| 681 rtx (*gen_fn) (rtx, rtx, rtx); | |
| 682 rtx brtmp; | |
| 683 int reverse_regs, invert; | |
| 684 | |
| 685 switch (test_code) | |
| 686 { | |
| 687 case EQ: reverse_regs = 0; invert = 0; gen_fn = gen_seq_sf; break; | |
| 688 case NE: reverse_regs = 0; invert = 1; gen_fn = gen_seq_sf; break; | |
| 689 case LE: reverse_regs = 0; invert = 0; gen_fn = gen_sle_sf; break; | |
| 690 case GT: reverse_regs = 1; invert = 0; gen_fn = gen_slt_sf; break; | |
| 691 case LT: reverse_regs = 0; invert = 0; gen_fn = gen_slt_sf; break; | |
| 692 case GE: reverse_regs = 1; invert = 0; gen_fn = gen_sle_sf; break; | |
| 693 case UNEQ: reverse_regs = 0; invert = 0; gen_fn = gen_suneq_sf; break; | |
| 694 case LTGT: reverse_regs = 0; invert = 1; gen_fn = gen_suneq_sf; break; | |
| 695 case UNLE: reverse_regs = 0; invert = 0; gen_fn = gen_sunle_sf; break; | |
| 696 case UNGT: reverse_regs = 1; invert = 0; gen_fn = gen_sunlt_sf; break; | |
| 697 case UNLT: reverse_regs = 0; invert = 0; gen_fn = gen_sunlt_sf; break; | |
| 698 case UNGE: reverse_regs = 1; invert = 0; gen_fn = gen_sunle_sf; break; | |
| 699 case UNORDERED: | |
| 700 reverse_regs = 0; invert = 0; gen_fn = gen_sunordered_sf; break; | |
| 701 case ORDERED: | |
| 702 reverse_regs = 0; invert = 1; gen_fn = gen_sunordered_sf; break; | |
| 703 default: | |
| 704 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1)); | |
| 705 reverse_regs = 0; invert = 0; gen_fn = 0; /* avoid compiler warnings */ | |
| 706 } | |
| 707 | |
| 708 if (reverse_regs) | |
| 709 { | |
| 710 rtx temp = cmp0; | |
| 711 cmp0 = cmp1; | |
| 712 cmp1 = temp; | |
| 713 } | |
| 714 | |
| 715 brtmp = gen_rtx_REG (CCmode, FPCC_REGNUM); | |
| 716 emit_insn (gen_fn (brtmp, cmp0, cmp1)); | |
| 717 | |
| 718 return gen_rtx_fmt_ee (invert ? EQ : NE, VOIDmode, brtmp, const0_rtx); | |
| 719 } | |
| 720 | |
| 721 | |
| 722 void | |
|
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723 xtensa_expand_conditional_branch (rtx *operands, enum machine_mode mode) |
| 0 | 724 { |
|
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725 enum rtx_code test_code = GET_CODE (operands[0]); |
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726 rtx cmp0 = operands[1]; |
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727 rtx cmp1 = operands[2]; |
| 0 | 728 rtx cmp; |
| 729 int invert; | |
| 730 rtx label1, label2; | |
| 731 | |
|
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732 switch (mode) |
| 0 | 733 { |
|
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734 case DFmode: |
| 0 | 735 default: |
| 736 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1)); | |
| 737 | |
|
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738 case SImode: |
| 0 | 739 invert = FALSE; |
| 740 cmp = gen_int_relational (test_code, cmp0, cmp1, &invert); | |
| 741 break; | |
| 742 | |
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743 case SFmode: |
| 0 | 744 if (!TARGET_HARD_FLOAT) |
| 745 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, | |
| 746 cmp0, cmp1)); | |
| 747 invert = FALSE; | |
| 748 cmp = gen_float_relational (test_code, cmp0, cmp1); | |
| 749 break; | |
| 750 } | |
| 751 | |
| 752 /* Generate the branch. */ | |
| 753 | |
|
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754 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[3]); |
| 0 | 755 label2 = pc_rtx; |
| 756 | |
| 757 if (invert) | |
| 758 { | |
| 759 label2 = label1; | |
| 760 label1 = pc_rtx; | |
| 761 } | |
| 762 | |
| 763 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
| 764 gen_rtx_IF_THEN_ELSE (VOIDmode, cmp, | |
| 765 label1, | |
| 766 label2))); | |
| 767 } | |
| 768 | |
| 769 | |
| 770 static rtx | |
|
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771 gen_conditional_move (enum rtx_code code, enum machine_mode mode, |
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772 rtx op0, rtx op1) |
| 0 | 773 { |
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774 if (mode == SImode) |
| 0 | 775 { |
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776 rtx cmp; |
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777 |
| 0 | 778 /* Jump optimization calls get_condition() which canonicalizes |
| 779 comparisons like (GE x <const>) to (GT x <const-1>). | |
| 780 Transform those comparisons back to GE, since that is the | |
| 781 comparison supported in Xtensa. We shouldn't have to | |
| 782 transform <LE x const> comparisons, because neither | |
| 783 xtensa_expand_conditional_branch() nor get_condition() will | |
| 784 produce them. */ | |
| 785 | |
| 786 if ((code == GT) && (op1 == constm1_rtx)) | |
| 787 { | |
| 788 code = GE; | |
| 789 op1 = const0_rtx; | |
| 790 } | |
| 791 cmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx); | |
| 792 | |
| 793 if (boolean_operator (cmp, VOIDmode)) | |
| 794 { | |
| 795 /* Swap the operands to make const0 second. */ | |
| 796 if (op0 == const0_rtx) | |
| 797 { | |
| 798 op0 = op1; | |
| 799 op1 = const0_rtx; | |
| 800 } | |
| 801 | |
| 802 /* If not comparing against zero, emit a comparison (subtract). */ | |
| 803 if (op1 != const0_rtx) | |
| 804 { | |
| 805 op0 = expand_binop (SImode, sub_optab, op0, op1, | |
| 806 0, 0, OPTAB_LIB_WIDEN); | |
| 807 op1 = const0_rtx; | |
| 808 } | |
| 809 } | |
| 810 else if (branch_operator (cmp, VOIDmode)) | |
| 811 { | |
| 812 /* Swap the operands to make const0 second. */ | |
| 813 if (op0 == const0_rtx) | |
| 814 { | |
| 815 op0 = op1; | |
| 816 op1 = const0_rtx; | |
| 817 | |
| 818 switch (code) | |
| 819 { | |
| 820 case LT: code = GE; break; | |
| 821 case GE: code = LT; break; | |
| 822 default: gcc_unreachable (); | |
| 823 } | |
| 824 } | |
| 825 | |
| 826 if (op1 != const0_rtx) | |
| 827 return 0; | |
| 828 } | |
| 829 else | |
| 830 return 0; | |
| 831 | |
| 832 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1); | |
| 833 } | |
| 834 | |
|
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835 if (TARGET_HARD_FLOAT && mode == SFmode) |
| 0 | 836 return gen_float_relational (code, op0, op1); |
| 837 | |
| 838 return 0; | |
| 839 } | |
| 840 | |
| 841 | |
| 842 int | |
| 843 xtensa_expand_conditional_move (rtx *operands, int isflt) | |
| 844 { | |
|
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845 rtx dest = operands[0]; |
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846 rtx cmp = operands[1]; |
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847 enum machine_mode cmp_mode = GET_MODE (XEXP (cmp, 0)); |
| 0 | 848 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx); |
| 849 | |
|
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850 if (!(cmp = gen_conditional_move (GET_CODE (cmp), cmp_mode, |
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851 XEXP (cmp, 0), XEXP (cmp, 1)))) |
| 0 | 852 return 0; |
| 853 | |
| 854 if (isflt) | |
|
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855 gen_fn = (cmp_mode == SImode |
| 0 | 856 ? gen_movsfcc_internal0 |
| 857 : gen_movsfcc_internal1); | |
| 858 else | |
|
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859 gen_fn = (cmp_mode == SImode |
| 0 | 860 ? gen_movsicc_internal0 |
| 861 : gen_movsicc_internal1); | |
| 862 | |
|
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863 emit_insn (gen_fn (dest, XEXP (cmp, 0), operands[2], operands[3], cmp)); |
| 0 | 864 return 1; |
| 865 } | |
| 866 | |
| 867 | |
| 868 int | |
|
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869 xtensa_expand_scc (rtx operands[4], enum machine_mode cmp_mode) |
| 0 | 870 { |
| 871 rtx dest = operands[0]; | |
|
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872 rtx cmp; |
| 0 | 873 rtx one_tmp, zero_tmp; |
| 874 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx); | |
| 875 | |
|
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876 if (!(cmp = gen_conditional_move (GET_CODE (operands[1]), cmp_mode, |
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877 operands[2], operands[3]))) |
| 0 | 878 return 0; |
| 879 | |
| 880 one_tmp = gen_reg_rtx (SImode); | |
| 881 zero_tmp = gen_reg_rtx (SImode); | |
| 882 emit_insn (gen_movsi (one_tmp, const_true_rtx)); | |
| 883 emit_insn (gen_movsi (zero_tmp, const0_rtx)); | |
| 884 | |
|
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885 gen_fn = (cmp_mode == SImode |
| 0 | 886 ? gen_movsicc_internal0 |
| 887 : gen_movsicc_internal1); | |
| 888 emit_insn (gen_fn (dest, XEXP (cmp, 0), one_tmp, zero_tmp, cmp)); | |
| 889 return 1; | |
| 890 } | |
| 891 | |
| 892 | |
| 893 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is | |
| 894 for the output, i.e., the input operands are twice as big as MODE. */ | |
| 895 | |
| 896 void | |
| 897 xtensa_split_operand_pair (rtx operands[4], enum machine_mode mode) | |
| 898 { | |
| 899 switch (GET_CODE (operands[1])) | |
| 900 { | |
| 901 case REG: | |
| 902 operands[3] = gen_rtx_REG (mode, REGNO (operands[1]) + 1); | |
| 903 operands[2] = gen_rtx_REG (mode, REGNO (operands[1])); | |
| 904 break; | |
| 905 | |
| 906 case MEM: | |
| 907 operands[3] = adjust_address (operands[1], mode, GET_MODE_SIZE (mode)); | |
| 908 operands[2] = adjust_address (operands[1], mode, 0); | |
| 909 break; | |
| 910 | |
| 911 case CONST_INT: | |
| 912 case CONST_DOUBLE: | |
| 913 split_double (operands[1], &operands[2], &operands[3]); | |
| 914 break; | |
| 915 | |
| 916 default: | |
| 917 gcc_unreachable (); | |
| 918 } | |
| 919 | |
| 920 switch (GET_CODE (operands[0])) | |
| 921 { | |
| 922 case REG: | |
| 923 operands[1] = gen_rtx_REG (mode, REGNO (operands[0]) + 1); | |
| 924 operands[0] = gen_rtx_REG (mode, REGNO (operands[0])); | |
| 925 break; | |
| 926 | |
| 927 case MEM: | |
| 928 operands[1] = adjust_address (operands[0], mode, GET_MODE_SIZE (mode)); | |
| 929 operands[0] = adjust_address (operands[0], mode, 0); | |
| 930 break; | |
| 931 | |
| 932 default: | |
| 933 gcc_unreachable (); | |
| 934 } | |
| 935 } | |
| 936 | |
| 937 | |
| 938 /* Emit insns to move operands[1] into operands[0]. | |
| 939 Return 1 if we have written out everything that needs to be done to | |
| 940 do the move. Otherwise, return 0 and the caller will emit the move | |
| 941 normally. */ | |
| 942 | |
| 943 int | |
| 944 xtensa_emit_move_sequence (rtx *operands, enum machine_mode mode) | |
| 945 { | |
| 946 rtx src = operands[1]; | |
| 947 | |
| 948 if (CONSTANT_P (src) | |
| 949 && (GET_CODE (src) != CONST_INT || ! xtensa_simm12b (INTVAL (src)))) | |
| 950 { | |
| 951 rtx dst = operands[0]; | |
| 952 | |
| 953 if (xtensa_tls_referenced_p (src)) | |
| 954 { | |
| 955 rtx addend = NULL; | |
| 956 | |
| 957 if (GET_CODE (src) == CONST && GET_CODE (XEXP (src, 0)) == PLUS) | |
| 958 { | |
| 959 addend = XEXP (XEXP (src, 0), 1); | |
| 960 src = XEXP (XEXP (src, 0), 0); | |
| 961 } | |
| 962 | |
| 963 src = xtensa_legitimize_tls_address (src); | |
| 964 if (addend) | |
| 965 { | |
| 966 src = gen_rtx_PLUS (mode, src, addend); | |
| 967 src = force_operand (src, dst); | |
| 968 } | |
| 969 emit_move_insn (dst, src); | |
| 970 return 1; | |
| 971 } | |
| 972 | |
| 973 if (! TARGET_CONST16) | |
| 974 { | |
| 975 src = force_const_mem (SImode, src); | |
| 976 operands[1] = src; | |
| 977 } | |
| 978 | |
| 979 /* PC-relative loads are always SImode, and CONST16 is only | |
| 980 supported in the movsi pattern, so add a SUBREG for any other | |
| 981 (smaller) mode. */ | |
| 982 | |
| 983 if (mode != SImode) | |
| 984 { | |
| 985 if (register_operand (dst, mode)) | |
| 986 { | |
| 987 emit_move_insn (simplify_gen_subreg (SImode, dst, mode, 0), src); | |
| 988 return 1; | |
| 989 } | |
| 990 else | |
| 991 { | |
| 992 src = force_reg (SImode, src); | |
| 993 src = gen_lowpart_SUBREG (mode, src); | |
| 994 operands[1] = src; | |
| 995 } | |
| 996 } | |
| 997 } | |
| 998 | |
| 999 if (!(reload_in_progress | reload_completed) | |
| 1000 && !xtensa_valid_move (mode, operands)) | |
| 1001 operands[1] = force_reg (mode, operands[1]); | |
| 1002 | |
| 1003 operands[1] = xtensa_copy_incoming_a7 (operands[1]); | |
| 1004 | |
| 1005 /* During reload we don't want to emit (subreg:X (mem:Y)) since that | |
| 1006 instruction won't be recognized after reload, so we remove the | |
| 1007 subreg and adjust mem accordingly. */ | |
| 1008 if (reload_in_progress) | |
| 1009 { | |
| 1010 operands[0] = fixup_subreg_mem (operands[0]); | |
| 1011 operands[1] = fixup_subreg_mem (operands[1]); | |
| 1012 } | |
| 1013 return 0; | |
| 1014 } | |
| 1015 | |
| 1016 | |
| 1017 static rtx | |
| 1018 fixup_subreg_mem (rtx x) | |
| 1019 { | |
| 1020 if (GET_CODE (x) == SUBREG | |
| 1021 && GET_CODE (SUBREG_REG (x)) == REG | |
| 1022 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER) | |
| 1023 { | |
| 1024 rtx temp = | |
| 1025 gen_rtx_SUBREG (GET_MODE (x), | |
| 1026 reg_equiv_mem [REGNO (SUBREG_REG (x))], | |
| 1027 SUBREG_BYTE (x)); | |
| 1028 x = alter_subreg (&temp); | |
| 1029 } | |
| 1030 return x; | |
| 1031 } | |
| 1032 | |
| 1033 | |
| 1034 /* Check if an incoming argument in a7 is expected to be used soon and | |
| 1035 if OPND is a register or register pair that includes a7. If so, | |
| 1036 create a new pseudo and copy a7 into that pseudo at the very | |
| 1037 beginning of the function, followed by the special "set_frame_ptr" | |
| 1038 unspec_volatile insn. The return value is either the original | |
| 1039 operand, if it is not a7, or the new pseudo containing a copy of | |
| 1040 the incoming argument. This is necessary because the register | |
| 1041 allocator will ignore conflicts with a7 and may either assign some | |
| 1042 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering | |
| 1043 the incoming argument in a7. By copying the argument out of a7 as | |
| 1044 the very first thing, and then immediately following that with an | |
| 1045 unspec_volatile to keep the scheduler away, we should avoid any | |
| 1046 problems. Putting the set_frame_ptr insn at the beginning, with | |
| 1047 only the a7 copy before it, also makes it easier for the prologue | |
| 1048 expander to initialize the frame pointer after the a7 copy and to | |
| 1049 fix up the a7 copy to use the stack pointer instead of the frame | |
| 1050 pointer. */ | |
| 1051 | |
| 1052 rtx | |
| 1053 xtensa_copy_incoming_a7 (rtx opnd) | |
| 1054 { | |
| 1055 rtx entry_insns = 0; | |
| 1056 rtx reg, tmp; | |
| 1057 enum machine_mode mode; | |
| 1058 | |
| 1059 if (!cfun->machine->need_a7_copy) | |
| 1060 return opnd; | |
| 1061 | |
| 1062 /* This function should never be called again once a7 has been copied. */ | |
| 1063 gcc_assert (!cfun->machine->set_frame_ptr_insn); | |
| 1064 | |
| 1065 mode = GET_MODE (opnd); | |
| 1066 | |
| 1067 /* The operand using a7 may come in a later instruction, so just return | |
| 1068 the original operand if it doesn't use a7. */ | |
| 1069 reg = opnd; | |
| 1070 if (GET_CODE (reg) == SUBREG) | |
| 1071 { | |
| 1072 gcc_assert (SUBREG_BYTE (reg) == 0); | |
| 1073 reg = SUBREG_REG (reg); | |
| 1074 } | |
| 1075 if (GET_CODE (reg) != REG | |
| 1076 || REGNO (reg) > A7_REG | |
| 1077 || REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) <= A7_REG) | |
| 1078 return opnd; | |
| 1079 | |
| 1080 /* 1-word args will always be in a7; 2-word args in a6/a7. */ | |
| 1081 gcc_assert (REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) - 1 == A7_REG); | |
| 1082 | |
| 1083 cfun->machine->need_a7_copy = false; | |
| 1084 | |
| 1085 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to | |
| 1086 create the REG for a7 so that hard_frame_pointer_rtx is not used. */ | |
| 1087 | |
| 1088 start_sequence (); | |
| 1089 tmp = gen_reg_rtx (mode); | |
| 1090 | |
| 1091 switch (mode) | |
| 1092 { | |
| 1093 case DFmode: | |
| 1094 case DImode: | |
| 1095 /* Copy the value out of A7 here but keep the first word in A6 until | |
| 1096 after the set_frame_ptr insn. Otherwise, the register allocator | |
| 1097 may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming | |
| 1098 value. */ | |
| 1099 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 4), | |
| 1100 gen_raw_REG (SImode, A7_REG))); | |
| 1101 break; | |
| 1102 case SFmode: | |
| 1103 emit_insn (gen_movsf_internal (tmp, gen_raw_REG (mode, A7_REG))); | |
| 1104 break; | |
| 1105 case SImode: | |
| 1106 emit_insn (gen_movsi_internal (tmp, gen_raw_REG (mode, A7_REG))); | |
| 1107 break; | |
| 1108 case HImode: | |
| 1109 emit_insn (gen_movhi_internal (tmp, gen_raw_REG (mode, A7_REG))); | |
| 1110 break; | |
| 1111 case QImode: | |
| 1112 emit_insn (gen_movqi_internal (tmp, gen_raw_REG (mode, A7_REG))); | |
| 1113 break; | |
| 1114 default: | |
| 1115 gcc_unreachable (); | |
| 1116 } | |
| 1117 | |
| 1118 cfun->machine->set_frame_ptr_insn = emit_insn (gen_set_frame_ptr ()); | |
| 1119 | |
| 1120 /* For DF and DI mode arguments, copy the incoming value in A6 now. */ | |
| 1121 if (mode == DFmode || mode == DImode) | |
| 1122 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 0), | |
| 1123 gen_rtx_REG (SImode, A7_REG - 1))); | |
| 1124 entry_insns = get_insns (); | |
| 1125 end_sequence (); | |
| 1126 | |
| 1127 if (cfun->machine->vararg_a7) | |
| 1128 { | |
| 1129 /* This is called from within builtin_saveregs, which will insert the | |
| 1130 saveregs code at the function entry, ahead of anything placed at | |
| 1131 the function entry now. Instead, save the sequence to be inserted | |
| 1132 at the beginning of the saveregs code. */ | |
| 1133 cfun->machine->vararg_a7_copy = entry_insns; | |
| 1134 } | |
| 1135 else | |
| 1136 { | |
| 1137 /* Put entry_insns after the NOTE that starts the function. If | |
| 1138 this is inside a start_sequence, make the outer-level insn | |
| 1139 chain current, so the code is placed at the start of the | |
| 1140 function. */ | |
| 1141 push_topmost_sequence (); | |
| 1142 /* Do not use entry_of_function() here. This is called from within | |
| 1143 expand_function_start, when the CFG still holds GIMPLE. */ | |
| 1144 emit_insn_after (entry_insns, get_insns ()); | |
| 1145 pop_topmost_sequence (); | |
| 1146 } | |
| 1147 | |
| 1148 return tmp; | |
| 1149 } | |
| 1150 | |
| 1151 | |
| 1152 /* Try to expand a block move operation to a sequence of RTL move | |
| 1153 instructions. If not optimizing, or if the block size is not a | |
| 1154 constant, or if the block is too large, the expansion fails and GCC | |
| 1155 falls back to calling memcpy(). | |
| 1156 | |
| 1157 operands[0] is the destination | |
| 1158 operands[1] is the source | |
| 1159 operands[2] is the length | |
| 1160 operands[3] is the alignment */ | |
| 1161 | |
| 1162 int | |
| 1163 xtensa_expand_block_move (rtx *operands) | |
| 1164 { | |
| 1165 static const enum machine_mode mode_from_align[] = | |
| 1166 { | |
| 1167 VOIDmode, QImode, HImode, VOIDmode, SImode, | |
| 1168 }; | |
| 1169 | |
| 1170 rtx dst_mem = operands[0]; | |
| 1171 rtx src_mem = operands[1]; | |
| 1172 HOST_WIDE_INT bytes, align; | |
| 1173 int num_pieces, move_ratio; | |
| 1174 rtx temp[2]; | |
| 1175 enum machine_mode mode[2]; | |
| 1176 int amount[2]; | |
| 1177 bool active[2]; | |
| 1178 int phase = 0; | |
| 1179 int next; | |
| 1180 int offset_ld = 0; | |
| 1181 int offset_st = 0; | |
| 1182 rtx x; | |
| 1183 | |
| 1184 /* If this is not a fixed size move, just call memcpy. */ | |
| 1185 if (!optimize || (GET_CODE (operands[2]) != CONST_INT)) | |
| 1186 return 0; | |
| 1187 | |
| 1188 bytes = INTVAL (operands[2]); | |
| 1189 align = INTVAL (operands[3]); | |
| 1190 | |
| 1191 /* Anything to move? */ | |
| 1192 if (bytes <= 0) | |
| 1193 return 0; | |
| 1194 | |
| 1195 if (align > MOVE_MAX) | |
| 1196 align = MOVE_MAX; | |
| 1197 | |
| 1198 /* Decide whether to expand inline based on the optimization level. */ | |
| 1199 move_ratio = 4; | |
| 1200 if (optimize > 2) | |
| 1201 move_ratio = LARGEST_MOVE_RATIO; | |
| 1202 num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */ | |
| 1203 if (num_pieces > move_ratio) | |
| 1204 return 0; | |
| 1205 | |
| 1206 x = XEXP (dst_mem, 0); | |
| 1207 if (!REG_P (x)) | |
| 1208 { | |
| 1209 x = force_reg (Pmode, x); | |
| 1210 dst_mem = replace_equiv_address (dst_mem, x); | |
| 1211 } | |
| 1212 | |
| 1213 x = XEXP (src_mem, 0); | |
| 1214 if (!REG_P (x)) | |
| 1215 { | |
| 1216 x = force_reg (Pmode, x); | |
| 1217 src_mem = replace_equiv_address (src_mem, x); | |
| 1218 } | |
| 1219 | |
| 1220 active[0] = active[1] = false; | |
| 1221 | |
| 1222 do | |
| 1223 { | |
| 1224 next = phase; | |
| 1225 phase ^= 1; | |
| 1226 | |
| 1227 if (bytes > 0) | |
| 1228 { | |
| 1229 int next_amount; | |
| 1230 | |
| 1231 next_amount = (bytes >= 4 ? 4 : (bytes >= 2 ? 2 : 1)); | |
| 1232 next_amount = MIN (next_amount, align); | |
| 1233 | |
| 1234 amount[next] = next_amount; | |
| 1235 mode[next] = mode_from_align[next_amount]; | |
| 1236 temp[next] = gen_reg_rtx (mode[next]); | |
| 1237 | |
| 1238 x = adjust_address (src_mem, mode[next], offset_ld); | |
| 1239 emit_insn (gen_rtx_SET (VOIDmode, temp[next], x)); | |
| 1240 | |
| 1241 offset_ld += next_amount; | |
| 1242 bytes -= next_amount; | |
| 1243 active[next] = true; | |
| 1244 } | |
| 1245 | |
| 1246 if (active[phase]) | |
| 1247 { | |
| 1248 active[phase] = false; | |
| 1249 | |
| 1250 x = adjust_address (dst_mem, mode[phase], offset_st); | |
| 1251 emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase])); | |
| 1252 | |
| 1253 offset_st += amount[phase]; | |
| 1254 } | |
| 1255 } | |
| 1256 while (active[next]); | |
| 1257 | |
| 1258 return 1; | |
| 1259 } | |
| 1260 | |
| 1261 | |
| 1262 void | |
| 1263 xtensa_expand_nonlocal_goto (rtx *operands) | |
| 1264 { | |
| 1265 rtx goto_handler = operands[1]; | |
| 1266 rtx containing_fp = operands[3]; | |
| 1267 | |
| 1268 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code | |
| 1269 is too big to generate in-line. */ | |
| 1270 | |
| 1271 if (GET_CODE (containing_fp) != REG) | |
| 1272 containing_fp = force_reg (Pmode, containing_fp); | |
| 1273 | |
| 1274 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"), | |
| 1275 0, VOIDmode, 2, | |
| 1276 containing_fp, Pmode, | |
| 1277 goto_handler, Pmode); | |
| 1278 } | |
| 1279 | |
| 1280 | |
| 1281 static struct machine_function * | |
| 1282 xtensa_init_machine_status (void) | |
| 1283 { | |
| 1284 return GGC_CNEW (struct machine_function); | |
| 1285 } | |
| 1286 | |
| 1287 | |
| 1288 /* Shift VAL of mode MODE left by COUNT bits. */ | |
| 1289 | |
| 1290 static inline rtx | |
| 1291 xtensa_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count) | |
| 1292 { | |
| 1293 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)), | |
| 1294 NULL_RTX, 1, OPTAB_DIRECT); | |
| 1295 return expand_simple_binop (SImode, ASHIFT, val, count, | |
| 1296 NULL_RTX, 1, OPTAB_DIRECT); | |
| 1297 } | |
| 1298 | |
| 1299 | |
| 1300 /* Structure to hold the initial parameters for a compare_and_swap operation | |
| 1301 in HImode and QImode. */ | |
| 1302 | |
| 1303 struct alignment_context | |
| 1304 { | |
| 1305 rtx memsi; /* SI aligned memory location. */ | |
| 1306 rtx shift; /* Bit offset with regard to lsb. */ | |
| 1307 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */ | |
| 1308 rtx modemaski; /* ~modemask */ | |
| 1309 }; | |
| 1310 | |
| 1311 | |
| 1312 /* Initialize structure AC for word access to HI and QI mode memory. */ | |
| 1313 | |
| 1314 static void | |
| 1315 init_alignment_context (struct alignment_context *ac, rtx mem) | |
| 1316 { | |
| 1317 enum machine_mode mode = GET_MODE (mem); | |
| 1318 rtx byteoffset = NULL_RTX; | |
| 1319 bool aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode)); | |
| 1320 | |
| 1321 if (aligned) | |
| 1322 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */ | |
| 1323 else | |
| 1324 { | |
| 1325 /* Alignment is unknown. */ | |
| 1326 rtx addr, align; | |
| 1327 | |
| 1328 /* Force the address into a register. */ | |
| 1329 addr = force_reg (Pmode, XEXP (mem, 0)); | |
| 1330 | |
| 1331 /* Align it to SImode. */ | |
| 1332 align = expand_simple_binop (Pmode, AND, addr, | |
| 1333 GEN_INT (-GET_MODE_SIZE (SImode)), | |
| 1334 NULL_RTX, 1, OPTAB_DIRECT); | |
| 1335 /* Generate MEM. */ | |
| 1336 ac->memsi = gen_rtx_MEM (SImode, align); | |
| 1337 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem); | |
| 1338 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER); | |
| 1339 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode)); | |
| 1340 | |
| 1341 byteoffset = expand_simple_binop (Pmode, AND, addr, | |
| 1342 GEN_INT (GET_MODE_SIZE (SImode) - 1), | |
| 1343 NULL_RTX, 1, OPTAB_DIRECT); | |
| 1344 } | |
| 1345 | |
| 1346 /* Calculate shiftcount. */ | |
| 1347 if (TARGET_BIG_ENDIAN) | |
| 1348 { | |
| 1349 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode)); | |
| 1350 if (!aligned) | |
| 1351 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset, | |
| 1352 NULL_RTX, 1, OPTAB_DIRECT); | |
| 1353 } | |
| 1354 else | |
| 1355 { | |
| 1356 if (aligned) | |
| 1357 ac->shift = NULL_RTX; | |
| 1358 else | |
| 1359 ac->shift = byteoffset; | |
| 1360 } | |
| 1361 | |
| 1362 if (ac->shift != NULL_RTX) | |
| 1363 { | |
| 1364 /* Shift is the byte count, but we need the bitcount. */ | |
| 1365 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, | |
| 1366 GEN_INT (BITS_PER_UNIT), | |
| 1367 NULL_RTX, 1, OPTAB_DIRECT); | |
| 1368 ac->modemask = expand_simple_binop (SImode, ASHIFT, | |
| 1369 GEN_INT (GET_MODE_MASK (mode)), | |
| 1370 ac->shift, | |
| 1371 NULL_RTX, 1, OPTAB_DIRECT); | |
| 1372 } | |
| 1373 else | |
| 1374 ac->modemask = GEN_INT (GET_MODE_MASK (mode)); | |
| 1375 | |
| 1376 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1); | |
| 1377 } | |
| 1378 | |
| 1379 | |
| 1380 /* Expand an atomic compare and swap operation for HImode and QImode. | |
| 1381 MEM is the memory location, CMP the old value to compare MEM with | |
| 1382 and NEW_RTX the value to set if CMP == MEM. */ | |
| 1383 | |
| 1384 void | |
| 1385 xtensa_expand_compare_and_swap (rtx target, rtx mem, rtx cmp, rtx new_rtx) | |
| 1386 { | |
| 1387 enum machine_mode mode = GET_MODE (mem); | |
| 1388 struct alignment_context ac; | |
| 1389 rtx tmp, cmpv, newv, val; | |
| 1390 rtx oldval = gen_reg_rtx (SImode); | |
| 1391 rtx res = gen_reg_rtx (SImode); | |
| 1392 rtx csloop = gen_label_rtx (); | |
| 1393 rtx csend = gen_label_rtx (); | |
| 1394 | |
| 1395 init_alignment_context (&ac, mem); | |
| 1396 | |
| 1397 if (ac.shift != NULL_RTX) | |
| 1398 { | |
| 1399 cmp = xtensa_expand_mask_and_shift (cmp, mode, ac.shift); | |
| 1400 new_rtx = xtensa_expand_mask_and_shift (new_rtx, mode, ac.shift); | |
| 1401 } | |
| 1402 | |
| 1403 /* Load the surrounding word into VAL with the MEM value masked out. */ | |
| 1404 val = force_reg (SImode, expand_simple_binop (SImode, AND, ac.memsi, | |
| 1405 ac.modemaski, NULL_RTX, 1, | |
| 1406 OPTAB_DIRECT)); | |
| 1407 emit_label (csloop); | |
| 1408 | |
| 1409 /* Patch CMP and NEW_RTX into VAL at correct position. */ | |
| 1410 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val, | |
| 1411 NULL_RTX, 1, OPTAB_DIRECT)); | |
| 1412 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val, | |
| 1413 NULL_RTX, 1, OPTAB_DIRECT)); | |
| 1414 | |
| 1415 /* Jump to end if we're done. */ | |
| 1416 emit_insn (gen_sync_compare_and_swapsi (res, ac.memsi, cmpv, newv)); | |
| 1417 emit_cmp_and_jump_insns (res, cmpv, EQ, const0_rtx, SImode, true, csend); | |
| 1418 | |
| 1419 /* Check for changes outside mode. */ | |
| 1420 emit_move_insn (oldval, val); | |
| 1421 tmp = expand_simple_binop (SImode, AND, res, ac.modemaski, | |
| 1422 val, 1, OPTAB_DIRECT); | |
| 1423 if (tmp != val) | |
| 1424 emit_move_insn (val, tmp); | |
| 1425 | |
| 1426 /* Loop internal if so. */ | |
| 1427 emit_cmp_and_jump_insns (oldval, val, NE, const0_rtx, SImode, true, csloop); | |
| 1428 | |
| 1429 emit_label (csend); | |
| 1430 | |
| 1431 /* Return the correct part of the bitfield. */ | |
| 1432 convert_move (target, | |
| 1433 (ac.shift == NULL_RTX ? res | |
| 1434 : expand_simple_binop (SImode, LSHIFTRT, res, ac.shift, | |
| 1435 NULL_RTX, 1, OPTAB_DIRECT)), | |
| 1436 1); | |
| 1437 } | |
| 1438 | |
| 1439 | |
| 1440 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode -- | |
| 1441 the default expansion works fine for SImode). MEM is the memory location | |
| 1442 and VAL the value to play with. If AFTER is true then store the value | |
| 1443 MEM holds after the operation, if AFTER is false then store the value MEM | |
| 1444 holds before the operation. If TARGET is zero then discard that value, else | |
| 1445 store it to TARGET. */ | |
| 1446 | |
| 1447 void | |
| 1448 xtensa_expand_atomic (enum rtx_code code, rtx target, rtx mem, rtx val, | |
| 1449 bool after) | |
| 1450 { | |
| 1451 enum machine_mode mode = GET_MODE (mem); | |
| 1452 struct alignment_context ac; | |
| 1453 rtx csloop = gen_label_rtx (); | |
| 1454 rtx cmp, tmp; | |
| 1455 rtx old = gen_reg_rtx (SImode); | |
| 1456 rtx new_rtx = gen_reg_rtx (SImode); | |
| 1457 rtx orig = NULL_RTX; | |
| 1458 | |
| 1459 init_alignment_context (&ac, mem); | |
| 1460 | |
| 1461 /* Prepare values before the compare-and-swap loop. */ | |
| 1462 if (ac.shift != NULL_RTX) | |
| 1463 val = xtensa_expand_mask_and_shift (val, mode, ac.shift); | |
| 1464 switch (code) | |
| 1465 { | |
| 1466 case PLUS: | |
| 1467 case MINUS: | |
| 1468 orig = gen_reg_rtx (SImode); | |
| 1469 convert_move (orig, val, 1); | |
| 1470 break; | |
| 1471 | |
| 1472 case SET: | |
| 1473 case IOR: | |
| 1474 case XOR: | |
| 1475 break; | |
| 1476 | |
| 1477 case MULT: /* NAND */ | |
| 1478 case AND: | |
| 1479 /* val = "11..1<val>11..1" */ | |
| 1480 val = expand_simple_binop (SImode, XOR, val, ac.modemaski, | |
| 1481 NULL_RTX, 1, OPTAB_DIRECT); | |
| 1482 break; | |
| 1483 | |
| 1484 default: | |
| 1485 gcc_unreachable (); | |
| 1486 } | |
| 1487 | |
| 1488 /* Load full word. Subsequent loads are performed by S32C1I. */ | |
| 1489 cmp = force_reg (SImode, ac.memsi); | |
| 1490 | |
| 1491 emit_label (csloop); | |
| 1492 emit_move_insn (old, cmp); | |
| 1493 | |
| 1494 switch (code) | |
| 1495 { | |
| 1496 case PLUS: | |
| 1497 case MINUS: | |
| 1498 val = expand_simple_binop (SImode, code, old, orig, | |
| 1499 NULL_RTX, 1, OPTAB_DIRECT); | |
| 1500 val = expand_simple_binop (SImode, AND, val, ac.modemask, | |
| 1501 NULL_RTX, 1, OPTAB_DIRECT); | |
| 1502 /* FALLTHRU */ | |
| 1503 case SET: | |
| 1504 tmp = expand_simple_binop (SImode, AND, old, ac.modemaski, | |
| 1505 NULL_RTX, 1, OPTAB_DIRECT); | |
| 1506 tmp = expand_simple_binop (SImode, IOR, tmp, val, | |
| 1507 new_rtx, 1, OPTAB_DIRECT); | |
| 1508 break; | |
| 1509 | |
| 1510 case AND: | |
| 1511 case IOR: | |
| 1512 case XOR: | |
| 1513 tmp = expand_simple_binop (SImode, code, old, val, | |
| 1514 new_rtx, 1, OPTAB_DIRECT); | |
| 1515 break; | |
| 1516 | |
| 1517 case MULT: /* NAND */ | |
| 1518 tmp = expand_simple_binop (SImode, XOR, old, ac.modemask, | |
| 1519 NULL_RTX, 1, OPTAB_DIRECT); | |
| 1520 tmp = expand_simple_binop (SImode, AND, tmp, val, | |
| 1521 new_rtx, 1, OPTAB_DIRECT); | |
| 1522 break; | |
| 1523 | |
| 1524 default: | |
| 1525 gcc_unreachable (); | |
| 1526 } | |
| 1527 | |
| 1528 if (tmp != new_rtx) | |
| 1529 emit_move_insn (new_rtx, tmp); | |
| 1530 emit_insn (gen_sync_compare_and_swapsi (cmp, ac.memsi, old, new_rtx)); | |
| 1531 emit_cmp_and_jump_insns (cmp, old, NE, const0_rtx, SImode, true, csloop); | |
| 1532 | |
| 1533 if (target) | |
| 1534 { | |
| 1535 tmp = (after ? new_rtx : cmp); | |
| 1536 convert_move (target, | |
| 1537 (ac.shift == NULL_RTX ? tmp | |
| 1538 : expand_simple_binop (SImode, LSHIFTRT, tmp, ac.shift, | |
| 1539 NULL_RTX, 1, OPTAB_DIRECT)), | |
| 1540 1); | |
| 1541 } | |
| 1542 } | |
| 1543 | |
| 1544 | |
| 1545 void | |
| 1546 xtensa_setup_frame_addresses (void) | |
| 1547 { | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1548 /* Set flag to cause TARGET_FRAME_POINTER_REQUIRED to return true. */ |
| 0 | 1549 cfun->machine->accesses_prev_frame = 1; |
| 1550 | |
| 1551 emit_library_call | |
| 1552 (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_libgcc_window_spill"), | |
| 1553 0, VOIDmode, 0); | |
| 1554 } | |
| 1555 | |
| 1556 | |
| 1557 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit | |
| 1558 a comment showing where the end of the loop is. However, if there is a | |
| 1559 label or a branch at the end of the loop then we need to place a nop | |
| 1560 there. If the loop ends with a label we need the nop so that branches | |
| 1561 targeting that label will target the nop (and thus remain in the loop), | |
| 1562 instead of targeting the instruction after the loop (and thus exiting | |
| 1563 the loop). If the loop ends with a branch, we need the nop in case the | |
| 1564 branch is targeting a location inside the loop. When the branch | |
| 1565 executes it will cause the loop count to be decremented even if it is | |
| 1566 taken (because it is the last instruction in the loop), so we need to | |
| 1567 nop after the branch to prevent the loop count from being decremented | |
| 1568 when the branch is taken. */ | |
| 1569 | |
| 1570 void | |
| 1571 xtensa_emit_loop_end (rtx insn, rtx *operands) | |
| 1572 { | |
| 1573 char done = 0; | |
| 1574 | |
| 1575 for (insn = PREV_INSN (insn); insn && !done; insn = PREV_INSN (insn)) | |
| 1576 { | |
| 1577 switch (GET_CODE (insn)) | |
| 1578 { | |
| 1579 case NOTE: | |
| 1580 case BARRIER: | |
| 1581 break; | |
| 1582 | |
| 1583 case CODE_LABEL: | |
| 1584 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands); | |
| 1585 done = 1; | |
| 1586 break; | |
| 1587 | |
| 1588 default: | |
| 1589 { | |
| 1590 rtx body = PATTERN (insn); | |
| 1591 | |
| 1592 if (GET_CODE (body) == JUMP_INSN) | |
| 1593 { | |
| 1594 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands); | |
| 1595 done = 1; | |
| 1596 } | |
| 1597 else if ((GET_CODE (body) != USE) | |
| 1598 && (GET_CODE (body) != CLOBBER)) | |
| 1599 done = 1; | |
| 1600 } | |
| 1601 break; | |
| 1602 } | |
| 1603 } | |
| 1604 | |
| 1605 output_asm_insn ("# loop end for %0", operands); | |
| 1606 } | |
| 1607 | |
| 1608 | |
| 1609 char * | |
| 1610 xtensa_emit_branch (bool inverted, bool immed, rtx *operands) | |
| 1611 { | |
| 1612 static char result[64]; | |
| 1613 enum rtx_code code; | |
| 1614 const char *op; | |
| 1615 | |
| 1616 code = GET_CODE (operands[3]); | |
| 1617 switch (code) | |
| 1618 { | |
| 1619 case EQ: op = inverted ? "ne" : "eq"; break; | |
| 1620 case NE: op = inverted ? "eq" : "ne"; break; | |
| 1621 case LT: op = inverted ? "ge" : "lt"; break; | |
| 1622 case GE: op = inverted ? "lt" : "ge"; break; | |
| 1623 case LTU: op = inverted ? "geu" : "ltu"; break; | |
| 1624 case GEU: op = inverted ? "ltu" : "geu"; break; | |
| 1625 default: gcc_unreachable (); | |
| 1626 } | |
| 1627 | |
| 1628 if (immed) | |
| 1629 { | |
| 1630 if (INTVAL (operands[1]) == 0) | |
| 1631 sprintf (result, "b%sz%s\t%%0, %%2", op, | |
| 1632 (TARGET_DENSITY && (code == EQ || code == NE)) ? ".n" : ""); | |
| 1633 else | |
| 1634 sprintf (result, "b%si\t%%0, %%d1, %%2", op); | |
| 1635 } | |
| 1636 else | |
| 1637 sprintf (result, "b%s\t%%0, %%1, %%2", op); | |
| 1638 | |
| 1639 return result; | |
| 1640 } | |
| 1641 | |
| 1642 | |
| 1643 char * | |
| 1644 xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands) | |
| 1645 { | |
| 1646 static char result[64]; | |
| 1647 const char *op; | |
| 1648 | |
| 1649 switch (GET_CODE (operands[3])) | |
| 1650 { | |
| 1651 case EQ: op = inverted ? "bs" : "bc"; break; | |
| 1652 case NE: op = inverted ? "bc" : "bs"; break; | |
| 1653 default: gcc_unreachable (); | |
| 1654 } | |
| 1655 | |
| 1656 if (immed) | |
| 1657 { | |
| 1658 unsigned bitnum = INTVAL (operands[1]) & 0x1f; | |
| 1659 operands[1] = GEN_INT (bitnum); | |
| 1660 sprintf (result, "b%si\t%%0, %%d1, %%2", op); | |
| 1661 } | |
| 1662 else | |
| 1663 sprintf (result, "b%s\t%%0, %%1, %%2", op); | |
| 1664 | |
| 1665 return result; | |
| 1666 } | |
| 1667 | |
| 1668 | |
| 1669 char * | |
| 1670 xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands) | |
| 1671 { | |
| 1672 static char result[64]; | |
| 1673 enum rtx_code code; | |
| 1674 const char *op; | |
| 1675 | |
| 1676 code = GET_CODE (operands[4]); | |
| 1677 if (isbool) | |
| 1678 { | |
| 1679 switch (code) | |
| 1680 { | |
| 1681 case EQ: op = inverted ? "t" : "f"; break; | |
| 1682 case NE: op = inverted ? "f" : "t"; break; | |
| 1683 default: gcc_unreachable (); | |
| 1684 } | |
| 1685 } | |
| 1686 else | |
| 1687 { | |
| 1688 switch (code) | |
| 1689 { | |
| 1690 case EQ: op = inverted ? "nez" : "eqz"; break; | |
| 1691 case NE: op = inverted ? "eqz" : "nez"; break; | |
| 1692 case LT: op = inverted ? "gez" : "ltz"; break; | |
| 1693 case GE: op = inverted ? "ltz" : "gez"; break; | |
| 1694 default: gcc_unreachable (); | |
| 1695 } | |
| 1696 } | |
| 1697 | |
| 1698 sprintf (result, "mov%s%s\t%%0, %%%d, %%1", | |
| 1699 op, isfp ? ".s" : "", inverted ? 3 : 2); | |
| 1700 return result; | |
| 1701 } | |
| 1702 | |
| 1703 | |
| 1704 char * | |
| 1705 xtensa_emit_call (int callop, rtx *operands) | |
| 1706 { | |
| 1707 static char result[64]; | |
| 1708 rtx tgt = operands[callop]; | |
| 1709 | |
| 1710 if (GET_CODE (tgt) == CONST_INT) | |
| 1711 sprintf (result, "call8\t0x%lx", INTVAL (tgt)); | |
| 1712 else if (register_operand (tgt, VOIDmode)) | |
| 1713 sprintf (result, "callx8\t%%%d", callop); | |
| 1714 else | |
| 1715 sprintf (result, "call8\t%%%d", callop); | |
| 1716 | |
| 1717 return result; | |
| 1718 } | |
| 1719 | |
| 1720 | |
| 1721 bool | |
| 1722 xtensa_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict) | |
| 1723 { | |
| 1724 /* Allow constant pool addresses. */ | |
| 1725 if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD | |
| 1726 && ! TARGET_CONST16 && constantpool_address_p (addr) | |
| 1727 && ! xtensa_tls_referenced_p (addr)) | |
| 1728 return true; | |
| 1729 | |
| 1730 while (GET_CODE (addr) == SUBREG) | |
| 1731 addr = SUBREG_REG (addr); | |
| 1732 | |
| 1733 /* Allow base registers. */ | |
| 1734 if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict)) | |
| 1735 return true; | |
| 1736 | |
| 1737 /* Check for "register + offset" addressing. */ | |
| 1738 if (GET_CODE (addr) == PLUS) | |
| 1739 { | |
| 1740 rtx xplus0 = XEXP (addr, 0); | |
| 1741 rtx xplus1 = XEXP (addr, 1); | |
| 1742 enum rtx_code code0; | |
| 1743 enum rtx_code code1; | |
| 1744 | |
| 1745 while (GET_CODE (xplus0) == SUBREG) | |
| 1746 xplus0 = SUBREG_REG (xplus0); | |
| 1747 code0 = GET_CODE (xplus0); | |
| 1748 | |
| 1749 while (GET_CODE (xplus1) == SUBREG) | |
| 1750 xplus1 = SUBREG_REG (xplus1); | |
| 1751 code1 = GET_CODE (xplus1); | |
| 1752 | |
| 1753 /* Swap operands if necessary so the register is first. */ | |
| 1754 if (code0 != REG && code1 == REG) | |
| 1755 { | |
| 1756 xplus0 = XEXP (addr, 1); | |
| 1757 xplus1 = XEXP (addr, 0); | |
| 1758 code0 = GET_CODE (xplus0); | |
| 1759 code1 = GET_CODE (xplus1); | |
| 1760 } | |
| 1761 | |
| 1762 if (code0 == REG && BASE_REG_P (xplus0, strict) | |
| 1763 && code1 == CONST_INT | |
| 1764 && xtensa_mem_offset (INTVAL (xplus1), mode)) | |
| 1765 return true; | |
| 1766 } | |
| 1767 | |
| 1768 return false; | |
| 1769 } | |
| 1770 | |
| 1771 | |
| 1772 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */ | |
| 1773 | |
| 1774 static GTY(()) rtx xtensa_tls_module_base_symbol; | |
| 1775 | |
| 1776 static rtx | |
| 1777 xtensa_tls_module_base (void) | |
| 1778 { | |
| 1779 if (! xtensa_tls_module_base_symbol) | |
| 1780 { | |
| 1781 xtensa_tls_module_base_symbol = | |
| 1782 gen_rtx_SYMBOL_REF (Pmode, "_TLS_MODULE_BASE_"); | |
| 1783 SYMBOL_REF_FLAGS (xtensa_tls_module_base_symbol) | |
| 1784 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT; | |
| 1785 } | |
| 1786 | |
| 1787 return xtensa_tls_module_base_symbol; | |
| 1788 } | |
| 1789 | |
| 1790 | |
| 1791 static rtx | |
| 1792 xtensa_call_tls_desc (rtx sym, rtx *retp) | |
| 1793 { | |
| 1794 rtx fn, arg, a10, call_insn, insns; | |
| 1795 | |
| 1796 start_sequence (); | |
| 1797 fn = gen_reg_rtx (Pmode); | |
| 1798 arg = gen_reg_rtx (Pmode); | |
| 1799 a10 = gen_rtx_REG (Pmode, 10); | |
| 1800 | |
| 1801 emit_insn (gen_tls_func (fn, sym)); | |
| 1802 emit_insn (gen_tls_arg (arg, sym)); | |
| 1803 emit_move_insn (a10, arg); | |
| 1804 call_insn = emit_call_insn (gen_tls_call (a10, fn, sym, const1_rtx)); | |
| 1805 CALL_INSN_FUNCTION_USAGE (call_insn) | |
| 1806 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, a10), | |
| 1807 CALL_INSN_FUNCTION_USAGE (call_insn)); | |
| 1808 insns = get_insns (); | |
| 1809 end_sequence (); | |
| 1810 | |
| 1811 *retp = a10; | |
| 1812 return insns; | |
| 1813 } | |
| 1814 | |
| 1815 | |
| 1816 static rtx | |
| 1817 xtensa_legitimize_tls_address (rtx x) | |
| 1818 { | |
| 1819 unsigned int model = SYMBOL_REF_TLS_MODEL (x); | |
| 1820 rtx dest, tp, ret, modbase, base, addend, insns; | |
| 1821 | |
| 1822 dest = gen_reg_rtx (Pmode); | |
| 1823 switch (model) | |
| 1824 { | |
| 1825 case TLS_MODEL_GLOBAL_DYNAMIC: | |
| 1826 insns = xtensa_call_tls_desc (x, &ret); | |
| 1827 emit_libcall_block (insns, dest, ret, x); | |
| 1828 break; | |
| 1829 | |
| 1830 case TLS_MODEL_LOCAL_DYNAMIC: | |
| 1831 base = gen_reg_rtx (Pmode); | |
| 1832 modbase = xtensa_tls_module_base (); | |
| 1833 insns = xtensa_call_tls_desc (modbase, &ret); | |
| 1834 emit_libcall_block (insns, base, ret, modbase); | |
| 1835 addend = force_reg (SImode, gen_sym_DTPOFF (x)); | |
| 1836 emit_insn (gen_addsi3 (dest, base, addend)); | |
| 1837 break; | |
| 1838 | |
| 1839 case TLS_MODEL_INITIAL_EXEC: | |
| 1840 case TLS_MODEL_LOCAL_EXEC: | |
| 1841 tp = gen_reg_rtx (SImode); | |
| 1842 emit_insn (gen_load_tp (tp)); | |
| 1843 addend = force_reg (SImode, gen_sym_TPOFF (x)); | |
| 1844 emit_insn (gen_addsi3 (dest, tp, addend)); | |
| 1845 break; | |
| 1846 | |
| 1847 default: | |
| 1848 gcc_unreachable (); | |
| 1849 } | |
| 1850 | |
| 1851 return dest; | |
| 1852 } | |
| 1853 | |
| 1854 | |
| 1855 rtx | |
| 1856 xtensa_legitimize_address (rtx x, | |
| 1857 rtx oldx ATTRIBUTE_UNUSED, | |
| 1858 enum machine_mode mode) | |
| 1859 { | |
| 1860 if (xtensa_tls_symbol_p (x)) | |
| 1861 return xtensa_legitimize_tls_address (x); | |
| 1862 | |
| 1863 if (GET_CODE (x) == PLUS) | |
| 1864 { | |
| 1865 rtx plus0 = XEXP (x, 0); | |
| 1866 rtx plus1 = XEXP (x, 1); | |
| 1867 | |
| 1868 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) | |
| 1869 { | |
| 1870 plus0 = XEXP (x, 1); | |
| 1871 plus1 = XEXP (x, 0); | |
| 1872 } | |
| 1873 | |
| 1874 /* Try to split up the offset to use an ADDMI instruction. */ | |
| 1875 if (GET_CODE (plus0) == REG | |
| 1876 && GET_CODE (plus1) == CONST_INT | |
| 1877 && !xtensa_mem_offset (INTVAL (plus1), mode) | |
| 1878 && !xtensa_simm8 (INTVAL (plus1)) | |
| 1879 && xtensa_mem_offset (INTVAL (plus1) & 0xff, mode) | |
| 1880 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) | |
| 1881 { | |
| 1882 rtx temp = gen_reg_rtx (Pmode); | |
| 1883 rtx addmi_offset = GEN_INT (INTVAL (plus1) & ~0xff); | |
| 1884 emit_insn (gen_rtx_SET (Pmode, temp, | |
| 1885 gen_rtx_PLUS (Pmode, plus0, addmi_offset))); | |
| 1886 return gen_rtx_PLUS (Pmode, temp, GEN_INT (INTVAL (plus1) & 0xff)); | |
| 1887 } | |
| 1888 } | |
| 1889 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1890 return x; |
| 0 | 1891 } |
| 1892 | |
| 1893 | |
| 1894 /* Helper for xtensa_tls_referenced_p. */ | |
| 1895 | |
| 1896 static int | |
| 1897 xtensa_tls_referenced_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
| 1898 { | |
| 1899 if (GET_CODE (*x) == SYMBOL_REF) | |
| 1900 return SYMBOL_REF_TLS_MODEL (*x) != 0; | |
| 1901 | |
| 1902 /* Ignore TLS references that have already been legitimized. */ | |
| 1903 if (GET_CODE (*x) == UNSPEC) | |
| 1904 { | |
| 1905 switch (XINT (*x, 1)) | |
| 1906 { | |
| 1907 case UNSPEC_TPOFF: | |
| 1908 case UNSPEC_DTPOFF: | |
| 1909 case UNSPEC_TLS_FUNC: | |
| 1910 case UNSPEC_TLS_ARG: | |
| 1911 case UNSPEC_TLS_CALL: | |
| 1912 return -1; | |
| 1913 default: | |
| 1914 break; | |
| 1915 } | |
| 1916 } | |
| 1917 | |
| 1918 return 0; | |
| 1919 } | |
| 1920 | |
| 1921 | |
| 1922 /* Return TRUE if X contains any TLS symbol references. */ | |
| 1923 | |
| 1924 bool | |
| 1925 xtensa_tls_referenced_p (rtx x) | |
| 1926 { | |
| 1927 if (! TARGET_HAVE_TLS) | |
| 1928 return false; | |
| 1929 | |
| 1930 return for_each_rtx (&x, xtensa_tls_referenced_p_1, NULL); | |
| 1931 } | |
| 1932 | |
| 1933 | |
| 1934 /* Return the debugger register number to use for 'regno'. */ | |
| 1935 | |
| 1936 int | |
| 1937 xtensa_dbx_register_number (int regno) | |
| 1938 { | |
| 1939 int first = -1; | |
| 1940 | |
| 1941 if (GP_REG_P (regno)) | |
| 1942 { | |
| 1943 regno -= GP_REG_FIRST; | |
| 1944 first = 0; | |
| 1945 } | |
| 1946 else if (BR_REG_P (regno)) | |
| 1947 { | |
| 1948 regno -= BR_REG_FIRST; | |
| 1949 first = 16; | |
| 1950 } | |
| 1951 else if (FP_REG_P (regno)) | |
| 1952 { | |
| 1953 regno -= FP_REG_FIRST; | |
| 1954 first = 48; | |
| 1955 } | |
| 1956 else if (ACC_REG_P (regno)) | |
| 1957 { | |
| 1958 first = 0x200; /* Start of Xtensa special registers. */ | |
| 1959 regno = 16; /* ACCLO is special register 16. */ | |
| 1960 } | |
| 1961 | |
| 1962 /* When optimizing, we sometimes get asked about pseudo-registers | |
| 1963 that don't represent hard registers. Return 0 for these. */ | |
| 1964 if (first == -1) | |
| 1965 return 0; | |
| 1966 | |
| 1967 return first + regno; | |
| 1968 } | |
| 1969 | |
| 1970 | |
| 1971 /* Argument support functions. */ | |
| 1972 | |
| 1973 /* Initialize CUMULATIVE_ARGS for a function. */ | |
| 1974 | |
| 1975 void | |
| 1976 init_cumulative_args (CUMULATIVE_ARGS *cum, int incoming) | |
| 1977 { | |
| 1978 cum->arg_words = 0; | |
| 1979 cum->incoming = incoming; | |
| 1980 } | |
| 1981 | |
| 1982 | |
| 1983 /* Advance the argument to the next argument position. */ | |
| 1984 | |
| 1985 void | |
| 1986 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type) | |
| 1987 { | |
| 1988 int words, max; | |
| 1989 int *arg_words; | |
| 1990 | |
| 1991 arg_words = &cum->arg_words; | |
| 1992 max = MAX_ARGS_IN_REGISTERS; | |
| 1993 | |
| 1994 words = (((mode != BLKmode) | |
| 1995 ? (int) GET_MODE_SIZE (mode) | |
| 1996 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
| 1997 | |
| 1998 if (*arg_words < max | |
| 1999 && (targetm.calls.must_pass_in_stack (mode, type) | |
| 2000 || *arg_words + words > max)) | |
| 2001 *arg_words = max; | |
| 2002 | |
| 2003 *arg_words += words; | |
| 2004 } | |
| 2005 | |
| 2006 | |
| 2007 /* Return an RTL expression containing the register for the given mode, | |
| 2008 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero | |
| 2009 if this is an incoming argument to the current function. */ | |
| 2010 | |
| 2011 rtx | |
| 2012 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, | |
| 2013 int incoming_p) | |
| 2014 { | |
| 2015 int regbase, words, max; | |
| 2016 int *arg_words; | |
| 2017 int regno; | |
| 2018 | |
| 2019 arg_words = &cum->arg_words; | |
| 2020 regbase = (incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST); | |
| 2021 max = MAX_ARGS_IN_REGISTERS; | |
| 2022 | |
| 2023 words = (((mode != BLKmode) | |
| 2024 ? (int) GET_MODE_SIZE (mode) | |
| 2025 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
| 2026 | |
| 2027 if (type && (TYPE_ALIGN (type) > BITS_PER_WORD)) | |
| 2028 { | |
| 2029 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_WORD; | |
| 2030 *arg_words = (*arg_words + align - 1) & -align; | |
| 2031 } | |
| 2032 | |
| 2033 if (*arg_words + words > max) | |
| 2034 return (rtx)0; | |
| 2035 | |
| 2036 regno = regbase + *arg_words; | |
| 2037 | |
| 2038 if (cum->incoming && regno <= A7_REG && regno + words > A7_REG) | |
| 2039 cfun->machine->need_a7_copy = true; | |
| 2040 | |
| 2041 return gen_rtx_REG (mode, regno); | |
| 2042 } | |
| 2043 | |
| 2044 | |
| 2045 int | |
| 2046 function_arg_boundary (enum machine_mode mode, tree type) | |
| 2047 { | |
| 2048 unsigned int alignment; | |
| 2049 | |
| 2050 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode); | |
| 2051 if (alignment < PARM_BOUNDARY) | |
| 2052 alignment = PARM_BOUNDARY; | |
| 2053 if (alignment > STACK_BOUNDARY) | |
| 2054 alignment = STACK_BOUNDARY; | |
| 2055 return alignment; | |
| 2056 } | |
| 2057 | |
| 2058 | |
| 2059 static bool | |
| 2060 xtensa_return_in_msb (const_tree valtype) | |
| 2061 { | |
| 2062 return (TARGET_BIG_ENDIAN | |
| 2063 && AGGREGATE_TYPE_P (valtype) | |
| 2064 && int_size_in_bytes (valtype) >= UNITS_PER_WORD); | |
| 2065 } | |
| 2066 | |
| 2067 | |
| 2068 void | |
| 2069 override_options (void) | |
| 2070 { | |
| 2071 int regno; | |
| 2072 enum machine_mode mode; | |
| 2073 | |
| 2074 if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT) | |
| 2075 error ("boolean registers required for the floating-point option"); | |
| 2076 | |
| 2077 /* Set up array giving whether a given register can hold a given mode. */ | |
| 2078 for (mode = VOIDmode; | |
| 2079 mode != MAX_MACHINE_MODE; | |
| 2080 mode = (enum machine_mode) ((int) mode + 1)) | |
| 2081 { | |
| 2082 int size = GET_MODE_SIZE (mode); | |
| 2083 enum mode_class mclass = GET_MODE_CLASS (mode); | |
| 2084 | |
| 2085 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
| 2086 { | |
| 2087 int temp; | |
| 2088 | |
| 2089 if (ACC_REG_P (regno)) | |
| 2090 temp = (TARGET_MAC16 | |
| 2091 && (mclass == MODE_INT) && (size <= UNITS_PER_WORD)); | |
| 2092 else if (GP_REG_P (regno)) | |
| 2093 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD)); | |
| 2094 else if (FP_REG_P (regno)) | |
| 2095 temp = (TARGET_HARD_FLOAT && (mode == SFmode)); | |
| 2096 else if (BR_REG_P (regno)) | |
| 2097 temp = (TARGET_BOOLEANS && (mode == CCmode)); | |
| 2098 else | |
| 2099 temp = FALSE; | |
| 2100 | |
| 2101 xtensa_hard_regno_mode_ok[(int) mode][regno] = temp; | |
| 2102 } | |
| 2103 } | |
| 2104 | |
| 2105 init_machine_status = xtensa_init_machine_status; | |
| 2106 | |
| 2107 /* Check PIC settings. PIC is only supported when using L32R | |
| 2108 instructions, and some targets need to always use PIC. */ | |
| 2109 if (flag_pic && TARGET_CONST16) | |
| 2110 error ("-f%s is not supported with CONST16 instructions", | |
| 2111 (flag_pic > 1 ? "PIC" : "pic")); | |
| 2112 else if (XTENSA_ALWAYS_PIC) | |
| 2113 { | |
| 2114 if (TARGET_CONST16) | |
| 2115 error ("PIC is required but not supported with CONST16 instructions"); | |
| 2116 flag_pic = 1; | |
| 2117 } | |
| 2118 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */ | |
| 2119 if (flag_pic > 1) | |
| 2120 flag_pic = 1; | |
| 2121 if (flag_pic && !flag_pie) | |
| 2122 flag_shlib = 1; | |
| 2123 | |
| 2124 /* Hot/cold partitioning does not work on this architecture, because of | |
| 2125 constant pools (the load instruction cannot necessarily reach that far). | |
| 2126 Therefore disable it on this architecture. */ | |
| 2127 if (flag_reorder_blocks_and_partition) | |
| 2128 { | |
| 2129 flag_reorder_blocks_and_partition = 0; | |
| 2130 flag_reorder_blocks = 1; | |
| 2131 } | |
| 2132 } | |
| 2133 | |
| 2134 | |
| 2135 /* A C compound statement to output to stdio stream STREAM the | |
| 2136 assembler syntax for an instruction operand X. X is an RTL | |
| 2137 expression. | |
| 2138 | |
| 2139 CODE is a value that can be used to specify one of several ways | |
| 2140 of printing the operand. It is used when identical operands | |
| 2141 must be printed differently depending on the context. CODE | |
| 2142 comes from the '%' specification that was used to request | |
| 2143 printing of the operand. If the specification was just '%DIGIT' | |
| 2144 then CODE is 0; if the specification was '%LTR DIGIT' then CODE | |
| 2145 is the ASCII code for LTR. | |
| 2146 | |
| 2147 If X is a register, this macro should print the register's name. | |
| 2148 The names can be found in an array 'reg_names' whose type is | |
| 2149 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'. | |
| 2150 | |
| 2151 When the machine description has a specification '%PUNCT' (a '%' | |
| 2152 followed by a punctuation character), this macro is called with | |
| 2153 a null pointer for X and the punctuation character for CODE. | |
| 2154 | |
| 2155 'a', 'c', 'l', and 'n' are reserved. | |
| 2156 | |
| 2157 The Xtensa specific codes are: | |
| 2158 | |
| 2159 'd' CONST_INT, print as signed decimal | |
| 2160 'x' CONST_INT, print as signed hexadecimal | |
| 2161 'K' CONST_INT, print number of bits in mask for EXTUI | |
| 2162 'R' CONST_INT, print (X & 0x1f) | |
| 2163 'L' CONST_INT, print ((32 - X) & 0x1f) | |
| 2164 'D' REG, print second register of double-word register operand | |
| 2165 'N' MEM, print address of next word following a memory operand | |
| 2166 'v' MEM, if memory reference is volatile, output a MEMW before it | |
| 2167 't' any constant, add "@h" suffix for top 16 bits | |
| 2168 'b' any constant, add "@l" suffix for bottom 16 bits | |
| 2169 */ | |
| 2170 | |
| 2171 static void | |
| 2172 printx (FILE *file, signed int val) | |
| 2173 { | |
| 2174 /* Print a hexadecimal value in a nice way. */ | |
| 2175 if ((val > -0xa) && (val < 0xa)) | |
| 2176 fprintf (file, "%d", val); | |
| 2177 else if (val < 0) | |
| 2178 fprintf (file, "-0x%x", -val); | |
| 2179 else | |
| 2180 fprintf (file, "0x%x", val); | |
| 2181 } | |
| 2182 | |
| 2183 | |
| 2184 void | |
| 2185 print_operand (FILE *file, rtx x, int letter) | |
| 2186 { | |
| 2187 if (!x) | |
| 2188 error ("PRINT_OPERAND null pointer"); | |
| 2189 | |
| 2190 switch (letter) | |
| 2191 { | |
| 2192 case 'D': | |
| 2193 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG) | |
| 2194 fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]); | |
| 2195 else | |
| 2196 output_operand_lossage ("invalid %%D value"); | |
| 2197 break; | |
| 2198 | |
| 2199 case 'v': | |
| 2200 if (GET_CODE (x) == MEM) | |
| 2201 { | |
| 2202 /* For a volatile memory reference, emit a MEMW before the | |
| 2203 load or store. */ | |
| 2204 if (MEM_VOLATILE_P (x) && TARGET_SERIALIZE_VOLATILE) | |
| 2205 fprintf (file, "memw\n\t"); | |
| 2206 } | |
| 2207 else | |
| 2208 output_operand_lossage ("invalid %%v value"); | |
| 2209 break; | |
| 2210 | |
| 2211 case 'N': | |
| 2212 if (GET_CODE (x) == MEM | |
| 2213 && (GET_MODE (x) == DFmode || GET_MODE (x) == DImode)) | |
| 2214 { | |
| 2215 x = adjust_address (x, GET_MODE (x) == DFmode ? SFmode : SImode, 4); | |
| 2216 output_address (XEXP (x, 0)); | |
| 2217 } | |
| 2218 else | |
| 2219 output_operand_lossage ("invalid %%N value"); | |
| 2220 break; | |
| 2221 | |
| 2222 case 'K': | |
| 2223 if (GET_CODE (x) == CONST_INT) | |
| 2224 { | |
| 2225 int num_bits = 0; | |
| 2226 unsigned val = INTVAL (x); | |
| 2227 while (val & 1) | |
| 2228 { | |
| 2229 num_bits += 1; | |
| 2230 val = val >> 1; | |
| 2231 } | |
| 2232 if ((val != 0) || (num_bits == 0) || (num_bits > 16)) | |
| 2233 fatal_insn ("invalid mask", x); | |
| 2234 | |
| 2235 fprintf (file, "%d", num_bits); | |
| 2236 } | |
| 2237 else | |
| 2238 output_operand_lossage ("invalid %%K value"); | |
| 2239 break; | |
| 2240 | |
| 2241 case 'L': | |
| 2242 if (GET_CODE (x) == CONST_INT) | |
| 2243 fprintf (file, "%ld", (32 - INTVAL (x)) & 0x1f); | |
| 2244 else | |
| 2245 output_operand_lossage ("invalid %%L value"); | |
| 2246 break; | |
| 2247 | |
| 2248 case 'R': | |
| 2249 if (GET_CODE (x) == CONST_INT) | |
| 2250 fprintf (file, "%ld", INTVAL (x) & 0x1f); | |
| 2251 else | |
| 2252 output_operand_lossage ("invalid %%R value"); | |
| 2253 break; | |
| 2254 | |
| 2255 case 'x': | |
| 2256 if (GET_CODE (x) == CONST_INT) | |
| 2257 printx (file, INTVAL (x)); | |
| 2258 else | |
| 2259 output_operand_lossage ("invalid %%x value"); | |
| 2260 break; | |
| 2261 | |
| 2262 case 'd': | |
| 2263 if (GET_CODE (x) == CONST_INT) | |
| 2264 fprintf (file, "%ld", INTVAL (x)); | |
| 2265 else | |
| 2266 output_operand_lossage ("invalid %%d value"); | |
| 2267 break; | |
| 2268 | |
| 2269 case 't': | |
| 2270 case 'b': | |
| 2271 if (GET_CODE (x) == CONST_INT) | |
| 2272 { | |
| 2273 printx (file, INTVAL (x)); | |
| 2274 fputs (letter == 't' ? "@h" : "@l", file); | |
| 2275 } | |
| 2276 else if (GET_CODE (x) == CONST_DOUBLE) | |
| 2277 { | |
| 2278 REAL_VALUE_TYPE r; | |
| 2279 REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
| 2280 if (GET_MODE (x) == SFmode) | |
| 2281 { | |
| 2282 long l; | |
| 2283 REAL_VALUE_TO_TARGET_SINGLE (r, l); | |
| 2284 fprintf (file, "0x%08lx@%c", l, letter == 't' ? 'h' : 'l'); | |
| 2285 } | |
| 2286 else | |
| 2287 output_operand_lossage ("invalid %%t/%%b value"); | |
| 2288 } | |
| 2289 else if (GET_CODE (x) == CONST) | |
| 2290 { | |
| 2291 /* X must be a symbolic constant on ELF. Write an expression | |
| 2292 suitable for 'const16' that sets the high or low 16 bits. */ | |
| 2293 if (GET_CODE (XEXP (x, 0)) != PLUS | |
| 2294 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
| 2295 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
| 2296 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
| 2297 output_operand_lossage ("invalid %%t/%%b value"); | |
| 2298 print_operand (file, XEXP (XEXP (x, 0), 0), 0); | |
| 2299 fputs (letter == 't' ? "@h" : "@l", file); | |
| 2300 /* There must be a non-alphanumeric character between 'h' or 'l' | |
| 2301 and the number. The '-' is added by print_operand() already. */ | |
| 2302 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) | |
| 2303 fputs ("+", file); | |
| 2304 print_operand (file, XEXP (XEXP (x, 0), 1), 0); | |
| 2305 } | |
| 2306 else | |
| 2307 { | |
| 2308 output_addr_const (file, x); | |
| 2309 fputs (letter == 't' ? "@h" : "@l", file); | |
| 2310 } | |
| 2311 break; | |
| 2312 | |
| 2313 default: | |
| 2314 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG) | |
| 2315 fprintf (file, "%s", reg_names[xt_true_regnum (x)]); | |
| 2316 else if (GET_CODE (x) == MEM) | |
| 2317 output_address (XEXP (x, 0)); | |
| 2318 else if (GET_CODE (x) == CONST_INT) | |
| 2319 fprintf (file, "%ld", INTVAL (x)); | |
| 2320 else | |
| 2321 output_addr_const (file, x); | |
| 2322 } | |
| 2323 } | |
| 2324 | |
| 2325 | |
| 2326 /* A C compound statement to output to stdio stream STREAM the | |
| 2327 assembler syntax for an instruction operand that is a memory | |
| 2328 reference whose address is ADDR. ADDR is an RTL expression. */ | |
| 2329 | |
| 2330 void | |
| 2331 print_operand_address (FILE *file, rtx addr) | |
| 2332 { | |
| 2333 if (!addr) | |
| 2334 error ("PRINT_OPERAND_ADDRESS, null pointer"); | |
| 2335 | |
| 2336 switch (GET_CODE (addr)) | |
| 2337 { | |
| 2338 default: | |
| 2339 fatal_insn ("invalid address", addr); | |
| 2340 break; | |
| 2341 | |
| 2342 case REG: | |
| 2343 fprintf (file, "%s, 0", reg_names [REGNO (addr)]); | |
| 2344 break; | |
| 2345 | |
| 2346 case PLUS: | |
| 2347 { | |
| 2348 rtx reg = (rtx)0; | |
| 2349 rtx offset = (rtx)0; | |
| 2350 rtx arg0 = XEXP (addr, 0); | |
| 2351 rtx arg1 = XEXP (addr, 1); | |
| 2352 | |
| 2353 if (GET_CODE (arg0) == REG) | |
| 2354 { | |
| 2355 reg = arg0; | |
| 2356 offset = arg1; | |
| 2357 } | |
| 2358 else if (GET_CODE (arg1) == REG) | |
| 2359 { | |
| 2360 reg = arg1; | |
| 2361 offset = arg0; | |
| 2362 } | |
| 2363 else | |
| 2364 fatal_insn ("no register in address", addr); | |
| 2365 | |
| 2366 if (CONSTANT_P (offset)) | |
| 2367 { | |
| 2368 fprintf (file, "%s, ", reg_names [REGNO (reg)]); | |
| 2369 output_addr_const (file, offset); | |
| 2370 } | |
| 2371 else | |
| 2372 fatal_insn ("address offset not a constant", addr); | |
| 2373 } | |
| 2374 break; | |
| 2375 | |
| 2376 case LABEL_REF: | |
| 2377 case SYMBOL_REF: | |
| 2378 case CONST_INT: | |
| 2379 case CONST: | |
| 2380 output_addr_const (file, addr); | |
| 2381 break; | |
| 2382 } | |
| 2383 } | |
| 2384 | |
| 2385 | |
| 2386 bool | |
| 2387 xtensa_output_addr_const_extra (FILE *fp, rtx x) | |
| 2388 { | |
| 2389 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1) | |
| 2390 { | |
| 2391 switch (XINT (x, 1)) | |
| 2392 { | |
| 2393 case UNSPEC_TPOFF: | |
| 2394 output_addr_const (fp, XVECEXP (x, 0, 0)); | |
| 2395 fputs ("@TPOFF", fp); | |
| 2396 return true; | |
| 2397 case UNSPEC_DTPOFF: | |
| 2398 output_addr_const (fp, XVECEXP (x, 0, 0)); | |
| 2399 fputs ("@DTPOFF", fp); | |
| 2400 return true; | |
| 2401 case UNSPEC_PLT: | |
| 2402 if (flag_pic) | |
| 2403 { | |
| 2404 output_addr_const (fp, XVECEXP (x, 0, 0)); | |
| 2405 fputs ("@PLT", fp); | |
| 2406 return true; | |
| 2407 } | |
| 2408 break; | |
| 2409 default: | |
| 2410 break; | |
| 2411 } | |
| 2412 } | |
| 2413 return false; | |
| 2414 } | |
| 2415 | |
| 2416 | |
| 2417 void | |
| 2418 xtensa_output_literal (FILE *file, rtx x, enum machine_mode mode, int labelno) | |
| 2419 { | |
| 2420 long value_long[2]; | |
| 2421 REAL_VALUE_TYPE r; | |
| 2422 int size; | |
| 2423 rtx first, second; | |
| 2424 | |
| 2425 fprintf (file, "\t.literal .LC%u, ", (unsigned) labelno); | |
| 2426 | |
| 2427 switch (GET_MODE_CLASS (mode)) | |
| 2428 { | |
| 2429 case MODE_FLOAT: | |
| 2430 gcc_assert (GET_CODE (x) == CONST_DOUBLE); | |
| 2431 | |
| 2432 REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
| 2433 switch (mode) | |
| 2434 { | |
| 2435 case SFmode: | |
| 2436 REAL_VALUE_TO_TARGET_SINGLE (r, value_long[0]); | |
| 2437 if (HOST_BITS_PER_LONG > 32) | |
| 2438 value_long[0] &= 0xffffffff; | |
| 2439 fprintf (file, "0x%08lx\n", value_long[0]); | |
| 2440 break; | |
| 2441 | |
| 2442 case DFmode: | |
| 2443 REAL_VALUE_TO_TARGET_DOUBLE (r, value_long); | |
| 2444 if (HOST_BITS_PER_LONG > 32) | |
| 2445 { | |
| 2446 value_long[0] &= 0xffffffff; | |
| 2447 value_long[1] &= 0xffffffff; | |
| 2448 } | |
| 2449 fprintf (file, "0x%08lx, 0x%08lx\n", | |
| 2450 value_long[0], value_long[1]); | |
| 2451 break; | |
| 2452 | |
| 2453 default: | |
| 2454 gcc_unreachable (); | |
| 2455 } | |
| 2456 | |
| 2457 break; | |
| 2458 | |
| 2459 case MODE_INT: | |
| 2460 case MODE_PARTIAL_INT: | |
| 2461 size = GET_MODE_SIZE (mode); | |
| 2462 switch (size) | |
| 2463 { | |
| 2464 case 4: | |
| 2465 output_addr_const (file, x); | |
| 2466 fputs ("\n", file); | |
| 2467 break; | |
| 2468 | |
| 2469 case 8: | |
| 2470 split_double (x, &first, &second); | |
| 2471 output_addr_const (file, first); | |
| 2472 fputs (", ", file); | |
| 2473 output_addr_const (file, second); | |
| 2474 fputs ("\n", file); | |
| 2475 break; | |
| 2476 | |
| 2477 default: | |
| 2478 gcc_unreachable (); | |
| 2479 } | |
| 2480 break; | |
| 2481 | |
| 2482 default: | |
| 2483 gcc_unreachable (); | |
| 2484 } | |
| 2485 } | |
| 2486 | |
| 2487 | |
| 2488 /* Return the bytes needed to compute the frame pointer from the current | |
| 2489 stack pointer. */ | |
| 2490 | |
| 2491 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT) | |
| 2492 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1)) | |
| 2493 | |
| 2494 long | |
| 2495 compute_frame_size (int size) | |
| 2496 { | |
| 2497 /* Add space for the incoming static chain value. */ | |
| 2498 if (cfun->static_chain_decl != NULL) | |
| 2499 size += (1 * UNITS_PER_WORD); | |
| 2500 | |
| 2501 xtensa_current_frame_size = | |
| 2502 XTENSA_STACK_ALIGN (size | |
| 2503 + crtl->outgoing_args_size | |
| 2504 + (WINDOW_SIZE * UNITS_PER_WORD)); | |
| 2505 return xtensa_current_frame_size; | |
| 2506 } | |
| 2507 | |
| 2508 | |
|
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2509 bool |
| 0 | 2510 xtensa_frame_pointer_required (void) |
| 2511 { | |
| 2512 /* The code to expand builtin_frame_addr and builtin_return_addr | |
| 2513 currently uses the hard_frame_pointer instead of frame_pointer. | |
| 2514 This seems wrong but maybe it's necessary for other architectures. | |
| 2515 This function is derived from the i386 code. */ | |
| 2516 | |
| 2517 if (cfun->machine->accesses_prev_frame) | |
|
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2518 return true; |
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2519 |
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2520 return false; |
| 0 | 2521 } |
| 2522 | |
| 2523 | |
| 2524 /* minimum frame = reg save area (4 words) plus static chain (1 word) | |
| 2525 and the total number of words must be a multiple of 128 bits. */ | |
| 2526 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD) | |
| 2527 | |
| 2528 void | |
| 2529 xtensa_expand_prologue (void) | |
| 2530 { | |
| 2531 HOST_WIDE_INT total_size; | |
| 2532 rtx size_rtx; | |
| 2533 rtx insn, note_rtx; | |
| 2534 | |
| 2535 total_size = compute_frame_size (get_frame_size ()); | |
| 2536 size_rtx = GEN_INT (total_size); | |
| 2537 | |
| 2538 if (total_size < (1 << (12+3))) | |
| 2539 insn = emit_insn (gen_entry (size_rtx)); | |
| 2540 else | |
| 2541 { | |
| 2542 /* Use a8 as a temporary since a0-a7 may be live. */ | |
| 2543 rtx tmp_reg = gen_rtx_REG (Pmode, A8_REG); | |
| 2544 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE))); | |
| 2545 emit_move_insn (tmp_reg, GEN_INT (total_size - MIN_FRAME_SIZE)); | |
| 2546 emit_insn (gen_subsi3 (tmp_reg, stack_pointer_rtx, tmp_reg)); | |
| 2547 insn = emit_insn (gen_movsi (stack_pointer_rtx, tmp_reg)); | |
| 2548 } | |
| 2549 | |
| 2550 if (frame_pointer_needed) | |
| 2551 { | |
| 2552 if (cfun->machine->set_frame_ptr_insn) | |
| 2553 { | |
| 2554 rtx first; | |
| 2555 | |
| 2556 push_topmost_sequence (); | |
| 2557 first = get_insns (); | |
| 2558 pop_topmost_sequence (); | |
| 2559 | |
| 2560 /* For all instructions prior to set_frame_ptr_insn, replace | |
| 2561 hard_frame_pointer references with stack_pointer. */ | |
| 2562 for (insn = first; | |
| 2563 insn != cfun->machine->set_frame_ptr_insn; | |
| 2564 insn = NEXT_INSN (insn)) | |
| 2565 { | |
| 2566 if (INSN_P (insn)) | |
| 2567 { | |
| 2568 PATTERN (insn) = replace_rtx (copy_rtx (PATTERN (insn)), | |
| 2569 hard_frame_pointer_rtx, | |
| 2570 stack_pointer_rtx); | |
| 2571 df_insn_rescan (insn); | |
| 2572 } | |
| 2573 } | |
| 2574 } | |
| 2575 else | |
| 2576 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, | |
| 2577 stack_pointer_rtx)); | |
| 2578 } | |
| 2579 | |
| 2580 /* Create a note to describe the CFA. Because this is only used to set | |
| 2581 DW_AT_frame_base for debug info, don't bother tracking changes through | |
| 2582 each instruction in the prologue. It just takes up space. */ | |
| 2583 note_rtx = gen_rtx_SET (VOIDmode, (frame_pointer_needed | |
| 2584 ? hard_frame_pointer_rtx | |
| 2585 : stack_pointer_rtx), | |
| 2586 plus_constant (stack_pointer_rtx, -total_size)); | |
| 2587 RTX_FRAME_RELATED_P (insn) = 1; | |
| 2588 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
| 2589 note_rtx, REG_NOTES (insn)); | |
| 2590 } | |
| 2591 | |
| 2592 | |
| 2593 /* Clear variables at function end. */ | |
| 2594 | |
| 2595 void | |
| 2596 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED, | |
| 2597 HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
| 2598 { | |
| 2599 xtensa_current_frame_size = 0; | |
| 2600 } | |
| 2601 | |
| 2602 | |
| 2603 rtx | |
| 2604 xtensa_return_addr (int count, rtx frame) | |
| 2605 { | |
| 2606 rtx result, retaddr, curaddr, label; | |
| 2607 | |
| 2608 if (count == -1) | |
| 2609 retaddr = gen_rtx_REG (Pmode, A0_REG); | |
| 2610 else | |
| 2611 { | |
| 2612 rtx addr = plus_constant (frame, -4 * UNITS_PER_WORD); | |
| 2613 addr = memory_address (Pmode, addr); | |
| 2614 retaddr = gen_reg_rtx (Pmode); | |
| 2615 emit_move_insn (retaddr, gen_rtx_MEM (Pmode, addr)); | |
| 2616 } | |
| 2617 | |
| 2618 /* The 2 most-significant bits of the return address on Xtensa hold | |
| 2619 the register window size. To get the real return address, these | |
| 2620 bits must be replaced with the high bits from some address in the | |
| 2621 code. */ | |
| 2622 | |
| 2623 /* Get the 2 high bits of a local label in the code. */ | |
| 2624 curaddr = gen_reg_rtx (Pmode); | |
| 2625 label = gen_label_rtx (); | |
| 2626 emit_label (label); | |
| 2627 LABEL_PRESERVE_P (label) = 1; | |
| 2628 emit_move_insn (curaddr, gen_rtx_LABEL_REF (Pmode, label)); | |
| 2629 emit_insn (gen_lshrsi3 (curaddr, curaddr, GEN_INT (30))); | |
| 2630 emit_insn (gen_ashlsi3 (curaddr, curaddr, GEN_INT (30))); | |
| 2631 | |
| 2632 /* Clear the 2 high bits of the return address. */ | |
| 2633 result = gen_reg_rtx (Pmode); | |
| 2634 emit_insn (gen_ashlsi3 (result, retaddr, GEN_INT (2))); | |
| 2635 emit_insn (gen_lshrsi3 (result, result, GEN_INT (2))); | |
| 2636 | |
| 2637 /* Combine them to get the result. */ | |
| 2638 emit_insn (gen_iorsi3 (result, result, curaddr)); | |
| 2639 return result; | |
| 2640 } | |
| 2641 | |
| 2642 | |
| 2643 /* Create the va_list data type. | |
| 2644 | |
| 2645 This structure is set up by __builtin_saveregs. The __va_reg field | |
| 2646 points to a stack-allocated region holding the contents of the | |
| 2647 incoming argument registers. The __va_ndx field is an index | |
| 2648 initialized to the position of the first unnamed (variable) | |
| 2649 argument. This same index is also used to address the arguments | |
| 2650 passed in memory. Thus, the __va_stk field is initialized to point | |
| 2651 to the position of the first argument in memory offset to account | |
| 2652 for the arguments passed in registers and to account for the size | |
| 2653 of the argument registers not being 16-byte aligned. E.G., there | |
| 2654 are 6 argument registers of 4 bytes each, but we want the __va_ndx | |
| 2655 for the first stack argument to have the maximal alignment of 16 | |
| 2656 bytes, so we offset the __va_stk address by 32 bytes so that | |
| 2657 __va_stk[32] references the first argument on the stack. */ | |
| 2658 | |
| 2659 static tree | |
| 2660 xtensa_build_builtin_va_list (void) | |
| 2661 { | |
| 2662 tree f_stk, f_reg, f_ndx, record, type_decl; | |
| 2663 | |
| 2664 record = (*lang_hooks.types.make_type) (RECORD_TYPE); | |
|
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2665 type_decl = build_decl (BUILTINS_LOCATION, |
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2666 TYPE_DECL, get_identifier ("__va_list_tag"), record); |
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2667 |
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2668 f_stk = build_decl (BUILTINS_LOCATION, |
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2669 FIELD_DECL, get_identifier ("__va_stk"), |
| 0 | 2670 ptr_type_node); |
|
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2671 f_reg = build_decl (BUILTINS_LOCATION, |
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2672 FIELD_DECL, get_identifier ("__va_reg"), |
| 0 | 2673 ptr_type_node); |
|
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2674 f_ndx = build_decl (BUILTINS_LOCATION, |
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2675 FIELD_DECL, get_identifier ("__va_ndx"), |
| 0 | 2676 integer_type_node); |
| 2677 | |
| 2678 DECL_FIELD_CONTEXT (f_stk) = record; | |
| 2679 DECL_FIELD_CONTEXT (f_reg) = record; | |
| 2680 DECL_FIELD_CONTEXT (f_ndx) = record; | |
| 2681 | |
| 2682 TREE_CHAIN (record) = type_decl; | |
| 2683 TYPE_NAME (record) = type_decl; | |
| 2684 TYPE_FIELDS (record) = f_stk; | |
| 2685 TREE_CHAIN (f_stk) = f_reg; | |
| 2686 TREE_CHAIN (f_reg) = f_ndx; | |
| 2687 | |
| 2688 layout_type (record); | |
| 2689 return record; | |
| 2690 } | |
| 2691 | |
| 2692 | |
| 2693 /* Save the incoming argument registers on the stack. Returns the | |
| 2694 address of the saved registers. */ | |
| 2695 | |
| 2696 static rtx | |
| 2697 xtensa_builtin_saveregs (void) | |
| 2698 { | |
| 2699 rtx gp_regs; | |
| 2700 int arg_words = crtl->args.info.arg_words; | |
| 2701 int gp_left = MAX_ARGS_IN_REGISTERS - arg_words; | |
| 2702 | |
| 2703 if (gp_left <= 0) | |
| 2704 return const0_rtx; | |
| 2705 | |
| 2706 /* Allocate the general-purpose register space. */ | |
| 2707 gp_regs = assign_stack_local | |
| 2708 (BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1); | |
| 2709 set_mem_alias_set (gp_regs, get_varargs_alias_set ()); | |
| 2710 | |
| 2711 /* Now store the incoming registers. */ | |
| 2712 cfun->machine->need_a7_copy = true; | |
| 2713 cfun->machine->vararg_a7 = true; | |
| 2714 move_block_from_reg (GP_ARG_FIRST + arg_words, | |
| 2715 adjust_address (gp_regs, BLKmode, | |
| 2716 arg_words * UNITS_PER_WORD), | |
| 2717 gp_left); | |
| 2718 gcc_assert (cfun->machine->vararg_a7_copy != 0); | |
| 2719 emit_insn_before (cfun->machine->vararg_a7_copy, get_insns ()); | |
| 2720 | |
| 2721 return XEXP (gp_regs, 0); | |
| 2722 } | |
| 2723 | |
| 2724 | |
| 2725 /* Implement `va_start' for varargs and stdarg. We look at the | |
| 2726 current function to fill in an initial va_list. */ | |
| 2727 | |
| 2728 static void | |
| 2729 xtensa_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) | |
| 2730 { | |
| 2731 tree f_stk, stk; | |
| 2732 tree f_reg, reg; | |
| 2733 tree f_ndx, ndx; | |
| 2734 tree t, u; | |
| 2735 int arg_words; | |
| 2736 | |
| 2737 arg_words = crtl->args.info.arg_words; | |
| 2738 | |
| 2739 f_stk = TYPE_FIELDS (va_list_type_node); | |
| 2740 f_reg = TREE_CHAIN (f_stk); | |
| 2741 f_ndx = TREE_CHAIN (f_reg); | |
| 2742 | |
| 2743 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE); | |
| 2744 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist), | |
| 2745 f_reg, NULL_TREE); | |
| 2746 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist), | |
| 2747 f_ndx, NULL_TREE); | |
| 2748 | |
| 2749 /* Call __builtin_saveregs; save the result in __va_reg */ | |
| 2750 u = make_tree (sizetype, expand_builtin_saveregs ()); | |
| 2751 u = fold_convert (ptr_type_node, u); | |
| 2752 t = build2 (MODIFY_EXPR, ptr_type_node, reg, u); | |
| 2753 TREE_SIDE_EFFECTS (t) = 1; | |
| 2754 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
| 2755 | |
| 2756 /* Set the __va_stk member to ($arg_ptr - 32). */ | |
| 2757 u = make_tree (ptr_type_node, virtual_incoming_args_rtx); | |
| 2758 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u, size_int (-32)); | |
| 2759 t = build2 (MODIFY_EXPR, ptr_type_node, stk, u); | |
| 2760 TREE_SIDE_EFFECTS (t) = 1; | |
| 2761 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
| 2762 | |
| 2763 /* Set the __va_ndx member. If the first variable argument is on | |
| 2764 the stack, adjust __va_ndx by 2 words to account for the extra | |
| 2765 alignment offset for __va_stk. */ | |
| 2766 if (arg_words >= MAX_ARGS_IN_REGISTERS) | |
| 2767 arg_words += 2; | |
| 2768 t = build2 (MODIFY_EXPR, integer_type_node, ndx, | |
| 2769 build_int_cst (integer_type_node, arg_words * UNITS_PER_WORD)); | |
| 2770 TREE_SIDE_EFFECTS (t) = 1; | |
| 2771 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
| 2772 } | |
| 2773 | |
| 2774 | |
| 2775 /* Implement `va_arg'. */ | |
| 2776 | |
| 2777 static tree | |
| 2778 xtensa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, | |
| 2779 gimple_seq *post_p ATTRIBUTE_UNUSED) | |
| 2780 { | |
| 2781 tree f_stk, stk; | |
| 2782 tree f_reg, reg; | |
| 2783 tree f_ndx, ndx; | |
| 2784 tree type_size, array, orig_ndx, addr, size, va_size, t; | |
| 2785 tree lab_false, lab_over, lab_false2; | |
| 2786 bool indirect; | |
| 2787 | |
| 2788 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false); | |
| 2789 if (indirect) | |
| 2790 type = build_pointer_type (type); | |
| 2791 | |
| 2792 /* Handle complex values as separate real and imaginary parts. */ | |
| 2793 if (TREE_CODE (type) == COMPLEX_TYPE) | |
| 2794 { | |
| 2795 tree real_part, imag_part; | |
| 2796 | |
| 2797 real_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type), | |
| 2798 pre_p, NULL); | |
| 2799 real_part = get_initialized_tmp_var (real_part, pre_p, NULL); | |
| 2800 | |
| 2801 imag_part = xtensa_gimplify_va_arg_expr (unshare_expr (valist), | |
| 2802 TREE_TYPE (type), | |
| 2803 pre_p, NULL); | |
| 2804 imag_part = get_initialized_tmp_var (imag_part, pre_p, NULL); | |
| 2805 | |
| 2806 return build2 (COMPLEX_EXPR, type, real_part, imag_part); | |
| 2807 } | |
| 2808 | |
| 2809 f_stk = TYPE_FIELDS (va_list_type_node); | |
| 2810 f_reg = TREE_CHAIN (f_stk); | |
| 2811 f_ndx = TREE_CHAIN (f_reg); | |
| 2812 | |
| 2813 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, | |
| 2814 f_stk, NULL_TREE); | |
| 2815 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist), | |
| 2816 f_reg, NULL_TREE); | |
| 2817 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist), | |
| 2818 f_ndx, NULL_TREE); | |
| 2819 | |
| 2820 type_size = size_in_bytes (type); | |
| 2821 va_size = round_up (type_size, UNITS_PER_WORD); | |
| 2822 gimplify_expr (&va_size, pre_p, NULL, is_gimple_val, fb_rvalue); | |
| 2823 | |
| 2824 | |
| 2825 /* First align __va_ndx if necessary for this arg: | |
| 2826 | |
| 2827 orig_ndx = (AP).__va_ndx; | |
| 2828 if (__alignof__ (TYPE) > 4 ) | |
| 2829 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1) | |
| 2830 & -__alignof__ (TYPE)); */ | |
| 2831 | |
| 2832 orig_ndx = get_initialized_tmp_var (ndx, pre_p, NULL); | |
| 2833 | |
| 2834 if (TYPE_ALIGN (type) > BITS_PER_WORD) | |
| 2835 { | |
| 2836 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_UNIT; | |
| 2837 | |
| 2838 t = build2 (PLUS_EXPR, integer_type_node, unshare_expr (orig_ndx), | |
| 2839 build_int_cst (integer_type_node, align - 1)); | |
| 2840 t = build2 (BIT_AND_EXPR, integer_type_node, t, | |
| 2841 build_int_cst (integer_type_node, -align)); | |
| 2842 gimplify_assign (unshare_expr (orig_ndx), t, pre_p); | |
| 2843 } | |
| 2844 | |
| 2845 | |
| 2846 /* Increment __va_ndx to point past the argument: | |
| 2847 | |
| 2848 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */ | |
| 2849 | |
| 2850 t = fold_convert (integer_type_node, va_size); | |
| 2851 t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, t); | |
| 2852 gimplify_assign (unshare_expr (ndx), t, pre_p); | |
| 2853 | |
| 2854 | |
| 2855 /* Check if the argument is in registers: | |
| 2856 | |
| 2857 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4 | |
| 2858 && !must_pass_in_stack (type)) | |
| 2859 __array = (AP).__va_reg; */ | |
| 2860 | |
| 2861 array = create_tmp_var (ptr_type_node, NULL); | |
| 2862 | |
| 2863 lab_over = NULL; | |
| 2864 if (!targetm.calls.must_pass_in_stack (TYPE_MODE (type), type)) | |
| 2865 { | |
|
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2866 lab_false = create_artificial_label (UNKNOWN_LOCATION); |
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2867 lab_over = create_artificial_label (UNKNOWN_LOCATION); |
| 0 | 2868 |
| 2869 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (ndx), | |
| 2870 build_int_cst (integer_type_node, | |
| 2871 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)); | |
| 2872 t = build3 (COND_EXPR, void_type_node, t, | |
| 2873 build1 (GOTO_EXPR, void_type_node, lab_false), | |
| 2874 NULL_TREE); | |
| 2875 gimplify_and_add (t, pre_p); | |
| 2876 | |
| 2877 gimplify_assign (unshare_expr (array), reg, pre_p); | |
| 2878 | |
| 2879 t = build1 (GOTO_EXPR, void_type_node, lab_over); | |
| 2880 gimplify_and_add (t, pre_p); | |
| 2881 | |
| 2882 t = build1 (LABEL_EXPR, void_type_node, lab_false); | |
| 2883 gimplify_and_add (t, pre_p); | |
| 2884 } | |
| 2885 | |
| 2886 | |
| 2887 /* ...otherwise, the argument is on the stack (never split between | |
| 2888 registers and the stack -- change __va_ndx if necessary): | |
| 2889 | |
| 2890 else | |
| 2891 { | |
| 2892 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4) | |
| 2893 (AP).__va_ndx = 32 + __va_size (TYPE); | |
| 2894 __array = (AP).__va_stk; | |
| 2895 } */ | |
| 2896 | |
|
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diff
changeset
|
2897 lab_false2 = create_artificial_label (UNKNOWN_LOCATION); |
| 0 | 2898 |
| 2899 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (orig_ndx), | |
| 2900 build_int_cst (integer_type_node, | |
| 2901 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)); | |
| 2902 t = build3 (COND_EXPR, void_type_node, t, | |
| 2903 build1 (GOTO_EXPR, void_type_node, lab_false2), | |
| 2904 NULL_TREE); | |
| 2905 gimplify_and_add (t, pre_p); | |
| 2906 | |
| 2907 t = size_binop (PLUS_EXPR, unshare_expr (va_size), size_int (32)); | |
| 2908 t = fold_convert (integer_type_node, t); | |
| 2909 gimplify_assign (unshare_expr (ndx), t, pre_p); | |
| 2910 | |
| 2911 t = build1 (LABEL_EXPR, void_type_node, lab_false2); | |
| 2912 gimplify_and_add (t, pre_p); | |
| 2913 | |
| 2914 gimplify_assign (array, stk, pre_p); | |
| 2915 | |
| 2916 if (lab_over) | |
| 2917 { | |
| 2918 t = build1 (LABEL_EXPR, void_type_node, lab_over); | |
| 2919 gimplify_and_add (t, pre_p); | |
| 2920 } | |
| 2921 | |
| 2922 | |
| 2923 /* Given the base array pointer (__array) and index to the subsequent | |
| 2924 argument (__va_ndx), find the address: | |
| 2925 | |
| 2926 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4 | |
| 2927 ? sizeof (TYPE) | |
| 2928 : __va_size (TYPE)) | |
| 2929 | |
| 2930 The results are endian-dependent because values smaller than one word | |
| 2931 are aligned differently. */ | |
| 2932 | |
| 2933 | |
| 2934 if (BYTES_BIG_ENDIAN && TREE_CODE (type_size) == INTEGER_CST) | |
| 2935 { | |
| 2936 t = fold_build2 (GE_EXPR, boolean_type_node, unshare_expr (type_size), | |
| 2937 size_int (PARM_BOUNDARY / BITS_PER_UNIT)); | |
| 2938 t = fold_build3 (COND_EXPR, sizetype, t, unshare_expr (va_size), | |
| 2939 unshare_expr (type_size)); | |
| 2940 size = t; | |
| 2941 } | |
| 2942 else | |
| 2943 size = unshare_expr (va_size); | |
| 2944 | |
| 2945 t = fold_convert (sizetype, unshare_expr (ndx)); | |
| 2946 t = build2 (MINUS_EXPR, sizetype, t, size); | |
| 2947 addr = build2 (POINTER_PLUS_EXPR, ptr_type_node, unshare_expr (array), t); | |
| 2948 | |
| 2949 addr = fold_convert (build_pointer_type (type), addr); | |
| 2950 if (indirect) | |
| 2951 addr = build_va_arg_indirect_ref (addr); | |
| 2952 return build_va_arg_indirect_ref (addr); | |
| 2953 } | |
| 2954 | |
| 2955 | |
| 2956 /* Builtins. */ | |
| 2957 | |
| 2958 enum xtensa_builtin | |
| 2959 { | |
| 2960 XTENSA_BUILTIN_UMULSIDI3, | |
| 2961 XTENSA_BUILTIN_THREAD_POINTER, | |
| 2962 XTENSA_BUILTIN_SET_THREAD_POINTER, | |
| 2963 XTENSA_BUILTIN_max | |
| 2964 }; | |
| 2965 | |
| 2966 | |
| 2967 static void | |
| 2968 xtensa_init_builtins (void) | |
| 2969 { | |
| 2970 tree ftype, decl; | |
| 2971 | |
| 2972 ftype = build_function_type_list (unsigned_intDI_type_node, | |
| 2973 unsigned_intSI_type_node, | |
| 2974 unsigned_intSI_type_node, NULL_TREE); | |
| 2975 | |
| 2976 decl = add_builtin_function ("__builtin_umulsidi3", ftype, | |
| 2977 XTENSA_BUILTIN_UMULSIDI3, BUILT_IN_MD, | |
| 2978 "__umulsidi3", NULL_TREE); | |
| 2979 TREE_NOTHROW (decl) = 1; | |
| 2980 TREE_READONLY (decl) = 1; | |
| 2981 | |
| 2982 if (TARGET_THREADPTR) | |
| 2983 { | |
| 2984 ftype = build_function_type (ptr_type_node, void_list_node); | |
| 2985 decl = add_builtin_function ("__builtin_thread_pointer", ftype, | |
| 2986 XTENSA_BUILTIN_THREAD_POINTER, BUILT_IN_MD, | |
| 2987 NULL, NULL_TREE); | |
| 2988 TREE_READONLY (decl) = 1; | |
| 2989 TREE_NOTHROW (decl) = 1; | |
| 2990 | |
| 2991 ftype = build_function_type_list (void_type_node, ptr_type_node, | |
| 2992 NULL_TREE); | |
| 2993 decl = add_builtin_function ("__builtin_set_thread_pointer", ftype, | |
| 2994 XTENSA_BUILTIN_SET_THREAD_POINTER, | |
| 2995 BUILT_IN_MD, NULL, NULL_TREE); | |
| 2996 TREE_NOTHROW (decl) = 1; | |
| 2997 } | |
| 2998 } | |
| 2999 | |
| 3000 | |
| 3001 static tree | |
|
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55
diff
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|
3002 xtensa_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args, |
|
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55
diff
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|
3003 bool ignore ATTRIBUTE_UNUSED) |
| 0 | 3004 { |
| 3005 unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
| 3006 tree arg0, arg1; | |
| 3007 | |
| 3008 switch (fcode) | |
| 3009 { | |
| 3010 case XTENSA_BUILTIN_UMULSIDI3: | |
|
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diff
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|
3011 arg0 = args[0]; |
|
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parents:
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diff
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|
3012 arg1 = args[1]; |
| 0 | 3013 if ((TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST) |
| 3014 || TARGET_MUL32_HIGH) | |
| 3015 return fold_build2 (MULT_EXPR, unsigned_intDI_type_node, | |
| 3016 fold_convert (unsigned_intDI_type_node, arg0), | |
| 3017 fold_convert (unsigned_intDI_type_node, arg1)); | |
| 3018 break; | |
| 3019 | |
| 3020 case XTENSA_BUILTIN_THREAD_POINTER: | |
| 3021 case XTENSA_BUILTIN_SET_THREAD_POINTER: | |
| 3022 break; | |
| 3023 | |
| 3024 default: | |
| 3025 internal_error ("bad builtin code"); | |
| 3026 break; | |
| 3027 } | |
| 3028 | |
| 3029 return NULL; | |
| 3030 } | |
| 3031 | |
| 3032 | |
| 3033 static rtx | |
| 3034 xtensa_expand_builtin (tree exp, rtx target, | |
| 3035 rtx subtarget ATTRIBUTE_UNUSED, | |
| 3036 enum machine_mode mode ATTRIBUTE_UNUSED, | |
| 3037 int ignore) | |
| 3038 { | |
| 3039 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); | |
| 3040 unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
| 3041 rtx arg; | |
| 3042 | |
| 3043 switch (fcode) | |
| 3044 { | |
| 3045 case XTENSA_BUILTIN_UMULSIDI3: | |
| 3046 /* The umulsidi3 builtin is just a mechanism to avoid calling the real | |
| 3047 __umulsidi3 function when the Xtensa configuration can directly | |
| 3048 implement it. If not, just call the function. */ | |
| 3049 return expand_call (exp, target, ignore); | |
| 3050 | |
| 3051 case XTENSA_BUILTIN_THREAD_POINTER: | |
| 3052 if (!target || !register_operand (target, Pmode)) | |
| 3053 target = gen_reg_rtx (Pmode); | |
| 3054 emit_insn (gen_load_tp (target)); | |
| 3055 return target; | |
| 3056 | |
| 3057 case XTENSA_BUILTIN_SET_THREAD_POINTER: | |
| 3058 arg = expand_normal (CALL_EXPR_ARG (exp, 0)); | |
| 3059 if (!register_operand (arg, Pmode)) | |
| 3060 arg = copy_to_mode_reg (Pmode, arg); | |
| 3061 emit_insn (gen_set_tp (arg)); | |
| 3062 return const0_rtx; | |
| 3063 | |
| 3064 default: | |
| 3065 internal_error ("bad builtin code"); | |
| 3066 } | |
| 3067 return NULL_RTX; | |
| 3068 } | |
| 3069 | |
| 3070 | |
| 3071 enum reg_class | |
| 3072 xtensa_preferred_reload_class (rtx x, enum reg_class rclass, int isoutput) | |
| 3073 { | |
| 3074 if (!isoutput && CONSTANT_P (x) && GET_CODE (x) == CONST_DOUBLE) | |
| 3075 return NO_REGS; | |
| 3076 | |
| 3077 /* Don't use the stack pointer or hard frame pointer for reloads! | |
| 3078 The hard frame pointer would normally be OK except that it may | |
| 3079 briefly hold an incoming argument in the prologue, and reload | |
| 3080 won't know that it is live because the hard frame pointer is | |
| 3081 treated specially. */ | |
| 3082 | |
| 3083 if (rclass == AR_REGS || rclass == GR_REGS) | |
| 3084 return RL_REGS; | |
| 3085 | |
| 3086 return rclass; | |
| 3087 } | |
| 3088 | |
| 3089 | |
| 3090 enum reg_class | |
| 3091 xtensa_secondary_reload (bool in_p, rtx x, enum reg_class rclass, | |
| 3092 enum machine_mode mode, secondary_reload_info *sri) | |
| 3093 { | |
| 3094 int regno; | |
| 3095 | |
| 3096 if (in_p && constantpool_mem_p (x)) | |
| 3097 { | |
| 3098 if (rclass == FP_REGS) | |
| 3099 return RL_REGS; | |
| 3100 | |
| 3101 if (mode == QImode) | |
| 3102 sri->icode = CODE_FOR_reloadqi_literal; | |
| 3103 else if (mode == HImode) | |
| 3104 sri->icode = CODE_FOR_reloadhi_literal; | |
| 3105 } | |
| 3106 | |
| 3107 regno = xt_true_regnum (x); | |
| 3108 if (ACC_REG_P (regno)) | |
| 3109 return ((rclass == GR_REGS || rclass == RL_REGS) ? NO_REGS : RL_REGS); | |
| 3110 if (rclass == ACC_REG) | |
| 3111 return (GP_REG_P (regno) ? NO_REGS : RL_REGS); | |
| 3112 | |
| 3113 return NO_REGS; | |
| 3114 } | |
| 3115 | |
| 3116 | |
| 3117 void | |
| 3118 order_regs_for_local_alloc (void) | |
| 3119 { | |
| 3120 if (!leaf_function_p ()) | |
| 3121 { | |
| 3122 memcpy (reg_alloc_order, reg_nonleaf_alloc_order, | |
| 3123 FIRST_PSEUDO_REGISTER * sizeof (int)); | |
| 3124 } | |
| 3125 else | |
| 3126 { | |
| 3127 int i, num_arg_regs; | |
| 3128 int nxt = 0; | |
| 3129 | |
| 3130 /* Use the AR registers in increasing order (skipping a0 and a1) | |
| 3131 but save the incoming argument registers for a last resort. */ | |
| 3132 num_arg_regs = crtl->args.info.arg_words; | |
| 3133 if (num_arg_regs > MAX_ARGS_IN_REGISTERS) | |
| 3134 num_arg_regs = MAX_ARGS_IN_REGISTERS; | |
| 3135 for (i = GP_ARG_FIRST; i < 16 - num_arg_regs; i++) | |
| 3136 reg_alloc_order[nxt++] = i + num_arg_regs; | |
| 3137 for (i = 0; i < num_arg_regs; i++) | |
| 3138 reg_alloc_order[nxt++] = GP_ARG_FIRST + i; | |
| 3139 | |
| 3140 /* List the coprocessor registers in order. */ | |
| 3141 for (i = 0; i < BR_REG_NUM; i++) | |
| 3142 reg_alloc_order[nxt++] = BR_REG_FIRST + i; | |
| 3143 | |
| 3144 /* List the FP registers in order for now. */ | |
| 3145 for (i = 0; i < 16; i++) | |
| 3146 reg_alloc_order[nxt++] = FP_REG_FIRST + i; | |
| 3147 | |
| 3148 /* GCC requires that we list *all* the registers.... */ | |
| 3149 reg_alloc_order[nxt++] = 0; /* a0 = return address */ | |
| 3150 reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */ | |
| 3151 reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */ | |
| 3152 reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */ | |
| 3153 | |
| 3154 reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */ | |
| 3155 } | |
| 3156 } | |
| 3157 | |
| 3158 | |
| 3159 /* Some Xtensa targets support multiple bss sections. If the section | |
| 3160 name ends with ".bss", add SECTION_BSS to the flags. */ | |
| 3161 | |
| 3162 static unsigned int | |
| 3163 xtensa_multibss_section_type_flags (tree decl, const char *name, int reloc) | |
| 3164 { | |
| 3165 unsigned int flags = default_section_type_flags (decl, name, reloc); | |
| 3166 const char *suffix; | |
| 3167 | |
| 3168 suffix = strrchr (name, '.'); | |
| 3169 if (suffix && strcmp (suffix, ".bss") == 0) | |
| 3170 { | |
| 3171 if (!decl || (TREE_CODE (decl) == VAR_DECL | |
| 3172 && DECL_INITIAL (decl) == NULL_TREE)) | |
| 3173 flags |= SECTION_BSS; /* @nobits */ | |
| 3174 else | |
| 3175 warning (0, "only uninitialized variables can be placed in a " | |
| 3176 ".bss section"); | |
| 3177 } | |
| 3178 | |
| 3179 return flags; | |
| 3180 } | |
| 3181 | |
| 3182 | |
| 3183 /* The literal pool stays with the function. */ | |
| 3184 | |
| 3185 static section * | |
| 3186 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED, | |
| 3187 rtx x ATTRIBUTE_UNUSED, | |
| 3188 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
| 3189 { | |
| 3190 return function_section (current_function_decl); | |
| 3191 } | |
| 3192 | |
| 3193 | |
| 3194 /* Compute a (partial) cost for rtx X. Return true if the complete | |
| 3195 cost has been computed, and false if subexpressions should be | |
| 3196 scanned. In either case, *TOTAL contains the cost result. */ | |
| 3197 | |
| 3198 static bool | |
| 3199 xtensa_rtx_costs (rtx x, int code, int outer_code, int *total, | |
| 3200 bool speed ATTRIBUTE_UNUSED) | |
| 3201 { | |
| 3202 switch (code) | |
| 3203 { | |
| 3204 case CONST_INT: | |
| 3205 switch (outer_code) | |
| 3206 { | |
| 3207 case SET: | |
| 3208 if (xtensa_simm12b (INTVAL (x))) | |
| 3209 { | |
| 3210 *total = 4; | |
| 3211 return true; | |
| 3212 } | |
| 3213 break; | |
| 3214 case PLUS: | |
| 3215 if (xtensa_simm8 (INTVAL (x)) | |
| 3216 || xtensa_simm8x256 (INTVAL (x))) | |
| 3217 { | |
| 3218 *total = 0; | |
| 3219 return true; | |
| 3220 } | |
| 3221 break; | |
| 3222 case AND: | |
| 3223 if (xtensa_mask_immediate (INTVAL (x))) | |
| 3224 { | |
| 3225 *total = 0; | |
| 3226 return true; | |
| 3227 } | |
| 3228 break; | |
| 3229 case COMPARE: | |
| 3230 if ((INTVAL (x) == 0) || xtensa_b4const (INTVAL (x))) | |
| 3231 { | |
| 3232 *total = 0; | |
| 3233 return true; | |
| 3234 } | |
| 3235 break; | |
| 3236 case ASHIFT: | |
| 3237 case ASHIFTRT: | |
| 3238 case LSHIFTRT: | |
| 3239 case ROTATE: | |
| 3240 case ROTATERT: | |
| 3241 /* No way to tell if X is the 2nd operand so be conservative. */ | |
| 3242 default: break; | |
| 3243 } | |
| 3244 if (xtensa_simm12b (INTVAL (x))) | |
| 3245 *total = 5; | |
| 3246 else if (TARGET_CONST16) | |
| 3247 *total = COSTS_N_INSNS (2); | |
| 3248 else | |
| 3249 *total = 6; | |
| 3250 return true; | |
| 3251 | |
| 3252 case CONST: | |
| 3253 case LABEL_REF: | |
| 3254 case SYMBOL_REF: | |
| 3255 if (TARGET_CONST16) | |
| 3256 *total = COSTS_N_INSNS (2); | |
| 3257 else | |
| 3258 *total = 5; | |
| 3259 return true; | |
| 3260 | |
| 3261 case CONST_DOUBLE: | |
| 3262 if (TARGET_CONST16) | |
| 3263 *total = COSTS_N_INSNS (4); | |
| 3264 else | |
| 3265 *total = 7; | |
| 3266 return true; | |
| 3267 | |
| 3268 case MEM: | |
| 3269 { | |
| 3270 int num_words = | |
| 3271 (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) ? 2 : 1; | |
| 3272 | |
| 3273 if (memory_address_p (GET_MODE (x), XEXP ((x), 0))) | |
| 3274 *total = COSTS_N_INSNS (num_words); | |
| 3275 else | |
| 3276 *total = COSTS_N_INSNS (2*num_words); | |
| 3277 return true; | |
| 3278 } | |
| 3279 | |
| 3280 case FFS: | |
| 3281 case CTZ: | |
| 3282 *total = COSTS_N_INSNS (TARGET_NSA ? 5 : 50); | |
| 3283 return true; | |
| 3284 | |
| 3285 case CLZ: | |
| 3286 *total = COSTS_N_INSNS (TARGET_NSA ? 1 : 50); | |
| 3287 return true; | |
| 3288 | |
| 3289 case NOT: | |
| 3290 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 3 : 2); | |
| 3291 return true; | |
| 3292 | |
| 3293 case AND: | |
| 3294 case IOR: | |
| 3295 case XOR: | |
| 3296 if (GET_MODE (x) == DImode) | |
| 3297 *total = COSTS_N_INSNS (2); | |
| 3298 else | |
| 3299 *total = COSTS_N_INSNS (1); | |
| 3300 return true; | |
| 3301 | |
| 3302 case ASHIFT: | |
| 3303 case ASHIFTRT: | |
| 3304 case LSHIFTRT: | |
| 3305 if (GET_MODE (x) == DImode) | |
| 3306 *total = COSTS_N_INSNS (50); | |
| 3307 else | |
| 3308 *total = COSTS_N_INSNS (1); | |
| 3309 return true; | |
| 3310 | |
| 3311 case ABS: | |
| 3312 { | |
| 3313 enum machine_mode xmode = GET_MODE (x); | |
| 3314 if (xmode == SFmode) | |
| 3315 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50); | |
| 3316 else if (xmode == DFmode) | |
| 3317 *total = COSTS_N_INSNS (50); | |
| 3318 else | |
| 3319 *total = COSTS_N_INSNS (4); | |
| 3320 return true; | |
| 3321 } | |
| 3322 | |
| 3323 case PLUS: | |
| 3324 case MINUS: | |
| 3325 { | |
| 3326 enum machine_mode xmode = GET_MODE (x); | |
| 3327 if (xmode == SFmode) | |
| 3328 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50); | |
| 3329 else if (xmode == DFmode || xmode == DImode) | |
| 3330 *total = COSTS_N_INSNS (50); | |
| 3331 else | |
| 3332 *total = COSTS_N_INSNS (1); | |
| 3333 return true; | |
| 3334 } | |
| 3335 | |
| 3336 case NEG: | |
| 3337 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 4 : 2); | |
| 3338 return true; | |
| 3339 | |
| 3340 case MULT: | |
| 3341 { | |
| 3342 enum machine_mode xmode = GET_MODE (x); | |
| 3343 if (xmode == SFmode) | |
| 3344 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50); | |
| 3345 else if (xmode == DFmode) | |
| 3346 *total = COSTS_N_INSNS (50); | |
| 3347 else if (xmode == DImode) | |
| 3348 *total = COSTS_N_INSNS (TARGET_MUL32_HIGH ? 10 : 50); | |
| 3349 else if (TARGET_MUL32) | |
| 3350 *total = COSTS_N_INSNS (4); | |
| 3351 else if (TARGET_MAC16) | |
| 3352 *total = COSTS_N_INSNS (16); | |
| 3353 else if (TARGET_MUL16) | |
| 3354 *total = COSTS_N_INSNS (12); | |
| 3355 else | |
| 3356 *total = COSTS_N_INSNS (50); | |
| 3357 return true; | |
| 3358 } | |
| 3359 | |
| 3360 case DIV: | |
| 3361 case MOD: | |
| 3362 { | |
| 3363 enum machine_mode xmode = GET_MODE (x); | |
| 3364 if (xmode == SFmode) | |
| 3365 { | |
| 3366 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50); | |
| 3367 return true; | |
| 3368 } | |
| 3369 else if (xmode == DFmode) | |
| 3370 { | |
| 3371 *total = COSTS_N_INSNS (50); | |
| 3372 return true; | |
| 3373 } | |
| 3374 } | |
| 3375 /* Fall through. */ | |
| 3376 | |
| 3377 case UDIV: | |
| 3378 case UMOD: | |
| 3379 { | |
| 3380 enum machine_mode xmode = GET_MODE (x); | |
| 3381 if (xmode == DImode) | |
| 3382 *total = COSTS_N_INSNS (50); | |
| 3383 else if (TARGET_DIV32) | |
| 3384 *total = COSTS_N_INSNS (32); | |
| 3385 else | |
| 3386 *total = COSTS_N_INSNS (50); | |
| 3387 return true; | |
| 3388 } | |
| 3389 | |
| 3390 case SQRT: | |
| 3391 if (GET_MODE (x) == SFmode) | |
| 3392 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50); | |
| 3393 else | |
| 3394 *total = COSTS_N_INSNS (50); | |
| 3395 return true; | |
| 3396 | |
| 3397 case SMIN: | |
| 3398 case UMIN: | |
| 3399 case SMAX: | |
| 3400 case UMAX: | |
| 3401 *total = COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50); | |
| 3402 return true; | |
| 3403 | |
| 3404 case SIGN_EXTRACT: | |
| 3405 case SIGN_EXTEND: | |
| 3406 *total = COSTS_N_INSNS (TARGET_SEXT ? 1 : 2); | |
| 3407 return true; | |
| 3408 | |
| 3409 case ZERO_EXTRACT: | |
| 3410 case ZERO_EXTEND: | |
| 3411 *total = COSTS_N_INSNS (1); | |
| 3412 return true; | |
| 3413 | |
| 3414 default: | |
| 3415 return false; | |
| 3416 } | |
| 3417 } | |
| 3418 | |
| 3419 /* Worker function for TARGET_RETURN_IN_MEMORY. */ | |
| 3420 | |
| 3421 static bool | |
| 3422 xtensa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) | |
| 3423 { | |
| 3424 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) | |
| 3425 > 4 * UNITS_PER_WORD); | |
| 3426 } | |
| 3427 | |
| 3428 /* Worker function for TARGET_FUNCTION_VALUE. */ | |
| 3429 | |
| 3430 rtx | |
| 3431 xtensa_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED, | |
| 3432 bool outgoing) | |
| 3433 { | |
| 3434 return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype) | |
| 3435 && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
| 3436 ? SImode : TYPE_MODE (valtype), | |
| 3437 outgoing ? GP_OUTGOING_RETURN : GP_RETURN); | |
| 3438 } | |
| 3439 | |
|
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3440 /* The static chain is passed in memory. Provide rtx giving 'mem' |
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3441 expressions that denote where they are stored. */ |
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3442 |
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3443 static rtx |
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3444 xtensa_static_chain (const_tree ARG_UNUSED (fndecl), bool incoming_p) |
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3445 { |
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3446 rtx base = incoming_p ? arg_pointer_rtx : stack_pointer_rtx; |
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3447 return gen_frame_mem (Pmode, plus_constant (base, -5 * UNITS_PER_WORD)); |
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3448 } |
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3449 |
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3450 |
| 0 | 3451 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY |
| 3452 instruction with a minimal stack frame in order to get some free | |
| 3453 registers. Once the actual call target is known, the proper stack frame | |
| 3454 size is extracted from the ENTRY instruction at the target and the | |
| 3455 current frame is adjusted to match. The trampoline then transfers | |
| 3456 control to the instruction following the ENTRY at the target. Note: | |
| 3457 this assumes that the target begins with an ENTRY instruction. */ | |
| 3458 | |
|
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3459 static void |
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3460 xtensa_asm_trampoline_template (FILE *stream) |
| 0 | 3461 { |
| 3462 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS); | |
| 3463 | |
| 3464 fprintf (stream, "\t.begin no-transform\n"); | |
| 3465 fprintf (stream, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); | |
| 3466 | |
| 3467 if (use_call0) | |
| 3468 { | |
| 3469 /* Save the return address. */ | |
| 3470 fprintf (stream, "\tmov\ta10, a0\n"); | |
| 3471 | |
| 3472 /* Use a CALL0 instruction to skip past the constants and in the | |
| 3473 process get the PC into A0. This allows PC-relative access to | |
| 3474 the constants without relying on L32R. */ | |
| 3475 fprintf (stream, "\tcall0\t.Lskipconsts\n"); | |
| 3476 } | |
| 3477 else | |
| 3478 fprintf (stream, "\tj\t.Lskipconsts\n"); | |
| 3479 | |
| 3480 fprintf (stream, "\t.align\t4\n"); | |
| 3481 fprintf (stream, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); | |
| 3482 fprintf (stream, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); | |
| 3483 fprintf (stream, ".Lskipconsts:\n"); | |
| 3484 | |
| 3485 /* Load the static chain and function address from the trampoline. */ | |
| 3486 if (use_call0) | |
| 3487 { | |
| 3488 fprintf (stream, "\taddi\ta0, a0, 3\n"); | |
| 3489 fprintf (stream, "\tl32i\ta9, a0, 0\n"); | |
| 3490 fprintf (stream, "\tl32i\ta8, a0, 4\n"); | |
| 3491 } | |
| 3492 else | |
| 3493 { | |
| 3494 fprintf (stream, "\tl32r\ta9, .Lchainval\n"); | |
| 3495 fprintf (stream, "\tl32r\ta8, .Lfnaddr\n"); | |
| 3496 } | |
| 3497 | |
| 3498 /* Store the static chain. */ | |
| 3499 fprintf (stream, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE - 20); | |
| 3500 | |
| 3501 /* Set the proper stack pointer value. */ | |
| 3502 fprintf (stream, "\tl32i\ta9, a8, 0\n"); | |
| 3503 fprintf (stream, "\textui\ta9, a9, %d, 12\n", | |
| 3504 TARGET_BIG_ENDIAN ? 8 : 12); | |
| 3505 fprintf (stream, "\tslli\ta9, a9, 3\n"); | |
| 3506 fprintf (stream, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); | |
| 3507 fprintf (stream, "\tsub\ta9, sp, a9\n"); | |
| 3508 fprintf (stream, "\tmovsp\tsp, a9\n"); | |
| 3509 | |
| 3510 if (use_call0) | |
| 3511 /* Restore the return address. */ | |
| 3512 fprintf (stream, "\tmov\ta0, a10\n"); | |
| 3513 | |
| 3514 /* Jump to the instruction following the ENTRY. */ | |
| 3515 fprintf (stream, "\taddi\ta8, a8, 3\n"); | |
| 3516 fprintf (stream, "\tjx\ta8\n"); | |
| 3517 | |
| 3518 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */ | |
| 3519 if (use_call0) | |
| 3520 fprintf (stream, "\t.byte\t0\n"); | |
| 3521 else | |
| 3522 fprintf (stream, "\tnop\n"); | |
| 3523 | |
| 3524 fprintf (stream, "\t.end no-transform\n"); | |
| 3525 } | |
| 3526 | |
|
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3527 static void |
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3528 xtensa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain) |
| 0 | 3529 { |
|
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3530 rtx func = XEXP (DECL_RTL (fndecl), 0); |
| 0 | 3531 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS); |
| 3532 int chain_off = use_call0 ? 12 : 8; | |
| 3533 int func_off = use_call0 ? 16 : 12; | |
|
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3534 |
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3535 emit_block_move (m_tramp, assemble_trampoline_template (), |
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3536 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); |
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3537 |
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3538 emit_move_insn (adjust_address (m_tramp, SImode, chain_off), chain); |
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3539 emit_move_insn (adjust_address (m_tramp, SImode, func_off), func); |
| 0 | 3540 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"), |
|
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3541 0, VOIDmode, 1, XEXP (m_tramp, 0), Pmode); |
| 0 | 3542 } |
| 3543 | |
| 3544 | |
| 3545 #include "gt-xtensa.h" |