Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/arm/arm.h @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | b7f97abdc517 |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 /* Definitions of target machine for GNU compiler, for ARM. |
| 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, | |
|
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3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
| 0 | 4 Free Software Foundation, Inc. |
| 5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) | |
| 6 and Martin Simmons (@harleqn.co.uk). | |
| 7 More major hacks by Richard Earnshaw (rearnsha@arm.com) | |
| 8 Minor hacks by Nick Clifton (nickc@cygnus.com) | |
| 9 | |
| 10 This file is part of GCC. | |
| 11 | |
| 12 GCC is free software; you can redistribute it and/or modify it | |
| 13 under the terms of the GNU General Public License as published | |
| 14 by the Free Software Foundation; either version 3, or (at your | |
| 15 option) any later version. | |
| 16 | |
| 17 GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 20 License for more details. | |
| 21 | |
| 22 You should have received a copy of the GNU General Public License | |
| 23 along with GCC; see the file COPYING3. If not see | |
| 24 <http://www.gnu.org/licenses/>. */ | |
| 25 | |
| 26 #ifndef GCC_ARM_H | |
| 27 #define GCC_ARM_H | |
| 28 | |
|
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29 /* We can't use enum machine_mode inside a generator file because it |
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30 hasn't been created yet; we shouldn't be using any code that |
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31 needs the real definition though, so this ought to be safe. */ |
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32 #ifdef GENERATOR_FILE |
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33 #define MACHMODE int |
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34 #else |
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35 #include "insn-modes.h" |
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36 #define MACHMODE enum machine_mode |
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37 #endif |
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38 |
| 0 | 39 #include "config/vxworks-dummy.h" |
| 40 | |
| 41 /* The architecture define. */ | |
| 42 extern char arm_arch_name[]; | |
| 43 | |
| 44 /* Target CPU builtins. */ | |
| 45 #define TARGET_CPU_CPP_BUILTINS() \ | |
| 46 do \ | |
| 47 { \ | |
| 48 /* Define __arm__ even when in thumb mode, for \ | |
| 49 consistency with armcc. */ \ | |
| 50 builtin_define ("__arm__"); \ | |
| 51 builtin_define ("__APCS_32__"); \ | |
| 52 if (TARGET_THUMB) \ | |
| 53 builtin_define ("__thumb__"); \ | |
| 54 if (TARGET_THUMB2) \ | |
| 55 builtin_define ("__thumb2__"); \ | |
| 56 \ | |
| 57 if (TARGET_BIG_END) \ | |
| 58 { \ | |
| 59 builtin_define ("__ARMEB__"); \ | |
| 60 if (TARGET_THUMB) \ | |
| 61 builtin_define ("__THUMBEB__"); \ | |
| 62 if (TARGET_LITTLE_WORDS) \ | |
| 63 builtin_define ("__ARMWEL__"); \ | |
| 64 } \ | |
| 65 else \ | |
| 66 { \ | |
| 67 builtin_define ("__ARMEL__"); \ | |
| 68 if (TARGET_THUMB) \ | |
| 69 builtin_define ("__THUMBEL__"); \ | |
| 70 } \ | |
| 71 \ | |
| 72 if (TARGET_SOFT_FLOAT) \ | |
| 73 builtin_define ("__SOFTFP__"); \ | |
| 74 \ | |
| 75 if (TARGET_VFP) \ | |
| 76 builtin_define ("__VFP_FP__"); \ | |
| 77 \ | |
| 78 if (TARGET_NEON) \ | |
| 79 builtin_define ("__ARM_NEON__"); \ | |
| 80 \ | |
| 81 /* Add a define for interworking. \ | |
| 82 Needed when building libgcc.a. */ \ | |
| 83 if (arm_cpp_interwork) \ | |
| 84 builtin_define ("__THUMB_INTERWORK__"); \ | |
| 85 \ | |
| 86 builtin_assert ("cpu=arm"); \ | |
| 87 builtin_assert ("machine=arm"); \ | |
| 88 \ | |
| 89 builtin_define (arm_arch_name); \ | |
| 90 if (arm_arch_cirrus) \ | |
| 91 builtin_define ("__MAVERICK__"); \ | |
| 92 if (arm_arch_xscale) \ | |
| 93 builtin_define ("__XSCALE__"); \ | |
| 94 if (arm_arch_iwmmxt) \ | |
| 95 builtin_define ("__IWMMXT__"); \ | |
| 96 if (TARGET_AAPCS_BASED) \ | |
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97 { \ |
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98 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \ |
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99 builtin_define ("__ARM_PCS_VFP"); \ |
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100 else if (arm_pcs_default == ARM_PCS_AAPCS) \ |
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101 builtin_define ("__ARM_PCS"); \ |
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102 builtin_define ("__ARM_EABI__"); \ |
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103 } \ |
| 0 | 104 } while (0) |
| 105 | |
| 106 /* The various ARM cores. */ | |
| 107 enum processor_type | |
| 108 { | |
| 109 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ | |
| 110 IDENT, | |
| 111 #include "arm-cores.def" | |
| 112 #undef ARM_CORE | |
| 113 /* Used to indicate that no processor has been specified. */ | |
| 114 arm_none | |
| 115 }; | |
| 116 | |
| 117 enum target_cpus | |
| 118 { | |
| 119 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ | |
| 120 TARGET_CPU_##IDENT, | |
| 121 #include "arm-cores.def" | |
| 122 #undef ARM_CORE | |
| 123 TARGET_CPU_generic | |
| 124 }; | |
| 125 | |
| 126 /* The processor for which instructions should be scheduled. */ | |
| 127 extern enum processor_type arm_tune; | |
| 128 | |
|
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129 enum arm_sync_generator_tag |
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130 { |
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131 arm_sync_generator_omn, |
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132 arm_sync_generator_omrn |
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133 }; |
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134 |
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135 /* Wrapper to pass around a polymorphic pointer to a sync instruction |
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136 generator and. */ |
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137 struct arm_sync_generator |
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138 { |
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139 enum arm_sync_generator_tag op; |
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140 union |
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141 { |
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142 rtx (* omn) (rtx, rtx, rtx); |
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143 rtx (* omrn) (rtx, rtx, rtx, rtx); |
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144 } u; |
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145 }; |
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146 |
| 0 | 147 typedef enum arm_cond_code |
| 148 { | |
| 149 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | |
| 150 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV | |
| 151 } | |
| 152 arm_cc; | |
| 153 | |
| 154 extern arm_cc arm_current_cc; | |
| 155 | |
| 156 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) | |
| 157 | |
| 158 extern int arm_target_label; | |
| 159 extern int arm_ccfsm_state; | |
| 160 extern GTY(()) rtx arm_target_insn; | |
| 161 /* The label of the current constant pool. */ | |
| 162 extern rtx pool_vector_label; | |
| 163 /* Set to 1 when a return insn is output, this means that the epilogue | |
| 164 is not needed. */ | |
| 165 extern int return_used_this_function; | |
| 166 /* Callback to output language specific object attributes. */ | |
| 167 extern void (*arm_lang_output_object_attributes_hook)(void); | |
| 168 | |
| 169 /* Just in case configure has failed to define anything. */ | |
| 170 #ifndef TARGET_CPU_DEFAULT | |
| 171 #define TARGET_CPU_DEFAULT TARGET_CPU_generic | |
| 172 #endif | |
| 173 | |
| 174 | |
| 175 #undef CPP_SPEC | |
| 176 #define CPP_SPEC "%(subtarget_cpp_spec) \ | |
| 177 %{msoft-float:%{mhard-float: \ | |
| 178 %e-msoft-float and -mhard_float may not be used together}} \ | |
| 179 %{mbig-endian:%{mlittle-endian: \ | |
| 180 %e-mbig-endian and -mlittle-endian may not be used together}}" | |
| 181 | |
| 182 #ifndef CC1_SPEC | |
| 183 #define CC1_SPEC "" | |
| 184 #endif | |
| 185 | |
| 186 /* This macro defines names of additional specifications to put in the specs | |
| 187 that can be used in various specifications like CC1_SPEC. Its definition | |
| 188 is an initializer with a subgrouping for each command option. | |
| 189 | |
| 190 Each subgrouping contains a string constant, that defines the | |
| 191 specification name, and a string constant that used by the GCC driver | |
| 192 program. | |
| 193 | |
| 194 Do not define this macro if it does not need to do anything. */ | |
| 195 #define EXTRA_SPECS \ | |
| 196 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ | |
| 197 SUBTARGET_EXTRA_SPECS | |
| 198 | |
| 199 #ifndef SUBTARGET_EXTRA_SPECS | |
| 200 #define SUBTARGET_EXTRA_SPECS | |
| 201 #endif | |
| 202 | |
| 203 #ifndef SUBTARGET_CPP_SPEC | |
| 204 #define SUBTARGET_CPP_SPEC "" | |
| 205 #endif | |
| 206 | |
| 207 /* Run-time Target Specification. */ | |
| 208 #ifndef TARGET_VERSION | |
| 209 #define TARGET_VERSION fputs (" (ARM/generic)", stderr); | |
| 210 #endif | |
| 211 | |
| 212 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) | |
| 213 /* Use hardware floating point instructions. */ | |
| 214 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) | |
| 215 /* Use hardware floating point calling convention. */ | |
| 216 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) | |
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217 #define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA) |
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218 #define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK) |
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219 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP) |
| 0 | 220 #define TARGET_IWMMXT (arm_arch_iwmmxt) |
| 221 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) | |
| 222 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) | |
| 223 #define TARGET_ARM (! TARGET_THUMB) | |
| 224 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ | |
| 225 #define TARGET_BACKTRACE (leaf_function_p () \ | |
| 226 ? TARGET_TPCS_LEAF_FRAME \ | |
| 227 : TARGET_TPCS_FRAME) | |
| 228 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN) | |
| 229 #define TARGET_AAPCS_BASED \ | |
| 230 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) | |
| 231 | |
| 232 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) | |
| 233 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) | |
| 234 | |
| 235 /* Only 16-bit thumb code. */ | |
| 236 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) | |
| 237 /* Arm or Thumb-2 32-bit code. */ | |
| 238 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) | |
| 239 /* 32-bit Thumb-2 code. */ | |
| 240 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) | |
| 241 /* Thumb-1 only. */ | |
| 242 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) | |
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243 /* FPA emulator without LFM. */ |
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244 #define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2) |
| 0 | 245 |
| 246 /* The following two macros concern the ability to execute coprocessor | |
| 247 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently | |
| 248 only ever tested when we know we are generating for VFP hardware; we need | |
| 249 to be more careful with TARGET_NEON as noted below. */ | |
| 250 | |
| 251 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ | |
|
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252 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32) |
| 0 | 253 |
| 254 /* FPU supports VFPv3 instructions. */ | |
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255 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3) |
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256 |
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257 /* FPU only supports VFP single-precision instructions. */ |
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258 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE) |
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259 |
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260 /* FPU supports VFP double-precision instructions. */ |
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261 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE) |
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262 |
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263 /* FPU supports half-precision floating-point with NEON element load/store. */ |
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264 #define TARGET_NEON_FP16 \ |
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265 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16) |
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266 |
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267 /* FPU supports VFP half-precision floating-point. */ |
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268 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16) |
| 0 | 269 |
| 270 /* FPU supports Neon instructions. The setting of this macro gets | |
| 271 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT | |
| 272 and TARGET_HARD_FLOAT to ensure that NEON instructions are | |
| 273 available. */ | |
| 274 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ | |
|
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275 && TARGET_VFP && arm_fpu_desc->neon) |
| 0 | 276 |
| 277 /* "DSP" multiply instructions, eg. SMULxy. */ | |
| 278 #define TARGET_DSP_MULTIPLY \ | |
|
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279 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) |
| 0 | 280 /* Integer SIMD instructions, and extend-accumulate instructions. */ |
| 281 #define TARGET_INT_SIMD \ | |
|
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282 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) |
| 0 | 283 |
| 284 /* Should MOVW/MOVT be used in preference to a constant pool. */ | |
| 285 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size) | |
| 286 | |
| 287 /* We could use unified syntax for arm mode, but for now we just use it | |
| 288 for Thumb-2. */ | |
| 289 #define TARGET_UNIFIED_ASM TARGET_THUMB2 | |
| 290 | |
|
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291 /* Nonzero if this chip provides the DMB instruction. */ |
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292 #define TARGET_HAVE_DMB (arm_arch7) |
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293 |
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294 /* Nonzero if this chip implements a memory barrier via CP15. */ |
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295 #define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB) |
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296 |
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297 /* Nonzero if this chip implements a memory barrier instruction. */ |
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298 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) |
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299 |
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300 /* Nonzero if this chip supports ldrex and strex */ |
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301 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) |
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302 |
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303 /* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */ |
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304 #define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7) |
| 0 | 305 |
| 306 /* True iff the full BPABI is being used. If TARGET_BPABI is true, | |
| 307 then TARGET_AAPCS_BASED must be true -- but the converse does not | |
| 308 hold. TARGET_BPABI implies the use of the BPABI runtime library, | |
| 309 etc., in addition to just the AAPCS calling conventions. */ | |
| 310 #ifndef TARGET_BPABI | |
| 311 #define TARGET_BPABI false | |
| 312 #endif | |
| 313 | |
| 314 /* Support for a compile-time default CPU, et cetera. The rules are: | |
| 315 --with-arch is ignored if -march or -mcpu are specified. | |
| 316 --with-cpu is ignored if -march or -mcpu are specified, and is overridden | |
| 317 by --with-arch. | |
| 318 --with-tune is ignored if -mtune or -mcpu are specified (but not affected | |
| 319 by -march). | |
| 320 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are | |
| 321 specified. | |
| 322 --with-fpu is ignored if -mfpu is specified. | |
| 323 --with-abi is ignored is -mabi is specified. */ | |
| 324 #define OPTION_DEFAULT_SPECS \ | |
| 325 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ | |
| 326 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ | |
| 327 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ | |
| 328 {"float", \ | |
| 329 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \ | |
| 330 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ | |
| 331 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ | |
| 332 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, | |
| 333 | |
| 334 /* Which floating point model to use. */ | |
| 335 enum arm_fp_model | |
| 336 { | |
| 337 ARM_FP_MODEL_UNKNOWN, | |
| 338 /* FPA model (Hardware or software). */ | |
| 339 ARM_FP_MODEL_FPA, | |
| 340 /* Cirrus Maverick floating point model. */ | |
| 341 ARM_FP_MODEL_MAVERICK, | |
| 342 /* VFP floating point model. */ | |
| 343 ARM_FP_MODEL_VFP | |
| 344 }; | |
| 345 | |
|
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346 enum vfp_reg_type |
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347 { |
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348 VFP_NONE = 0, |
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349 VFP_REG_D16, |
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350 VFP_REG_D32, |
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351 VFP_REG_SINGLE |
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352 }; |
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353 |
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354 extern const struct arm_fpu_desc |
| 0 | 355 { |
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356 const char *name; |
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357 enum arm_fp_model model; |
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358 int rev; |
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359 enum vfp_reg_type regs; |
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360 int neon; |
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361 int fp16; |
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362 } *arm_fpu_desc; |
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363 |
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364 /* Which floating point hardware to schedule for. */ |
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365 extern int arm_fpu_attr; |
| 0 | 366 |
| 367 enum float_abi_type | |
| 368 { | |
| 369 ARM_FLOAT_ABI_SOFT, | |
| 370 ARM_FLOAT_ABI_SOFTFP, | |
| 371 ARM_FLOAT_ABI_HARD | |
| 372 }; | |
| 373 | |
| 374 extern enum float_abi_type arm_float_abi; | |
| 375 | |
| 376 #ifndef TARGET_DEFAULT_FLOAT_ABI | |
| 377 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT | |
| 378 #endif | |
| 379 | |
|
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380 /* Which __fp16 format to use. |
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381 The enumeration values correspond to the numbering for the |
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382 Tag_ABI_FP_16bit_format attribute. |
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383 */ |
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384 enum arm_fp16_format_type |
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385 { |
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386 ARM_FP16_FORMAT_NONE = 0, |
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387 ARM_FP16_FORMAT_IEEE = 1, |
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388 ARM_FP16_FORMAT_ALTERNATIVE = 2 |
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389 }; |
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390 |
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391 extern enum arm_fp16_format_type arm_fp16_format; |
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392 #define LARGEST_EXPONENT_IS_NORMAL(bits) \ |
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393 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) |
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394 |
| 0 | 395 /* Which ABI to use. */ |
| 396 enum arm_abi_type | |
| 397 { | |
| 398 ARM_ABI_APCS, | |
| 399 ARM_ABI_ATPCS, | |
| 400 ARM_ABI_AAPCS, | |
| 401 ARM_ABI_IWMMXT, | |
| 402 ARM_ABI_AAPCS_LINUX | |
| 403 }; | |
| 404 | |
| 405 extern enum arm_abi_type arm_abi; | |
| 406 | |
| 407 #ifndef ARM_DEFAULT_ABI | |
| 408 #define ARM_DEFAULT_ABI ARM_ABI_APCS | |
| 409 #endif | |
| 410 | |
| 411 /* Which thread pointer access sequence to use. */ | |
| 412 enum arm_tp_type { | |
| 413 TP_AUTO, | |
| 414 TP_SOFT, | |
| 415 TP_CP15 | |
| 416 }; | |
| 417 | |
| 418 extern enum arm_tp_type target_thread_pointer; | |
| 419 | |
| 420 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ | |
| 421 extern int arm_arch3m; | |
| 422 | |
| 423 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ | |
| 424 extern int arm_arch4; | |
| 425 | |
| 426 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ | |
| 427 extern int arm_arch4t; | |
| 428 | |
| 429 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ | |
| 430 extern int arm_arch5; | |
| 431 | |
| 432 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ | |
| 433 extern int arm_arch5e; | |
| 434 | |
| 435 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ | |
| 436 extern int arm_arch6; | |
| 437 | |
|
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438 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ |
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439 extern int arm_arch6k; |
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440 |
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441 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ |
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442 extern int arm_arch7; |
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443 |
| 0 | 444 /* Nonzero if instructions not present in the 'M' profile can be used. */ |
| 445 extern int arm_arch_notm; | |
| 446 | |
|
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447 /* Nonzero if instructions present in ARMv7E-M can be used. */ |
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448 extern int arm_arch7em; |
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449 |
| 0 | 450 /* Nonzero if this chip can benefit from load scheduling. */ |
| 451 extern int arm_ld_sched; | |
| 452 | |
|
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453 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */ |
| 0 | 454 extern int thumb_code; |
| 455 | |
|
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456 /* Nonzero if generating Thumb-1 code. */ |
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457 extern int thumb1_code; |
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458 |
| 0 | 459 /* Nonzero if this chip is a StrongARM. */ |
| 460 extern int arm_tune_strongarm; | |
| 461 | |
| 462 /* Nonzero if this chip is a Cirrus variant. */ | |
| 463 extern int arm_arch_cirrus; | |
| 464 | |
| 465 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ | |
| 466 extern int arm_arch_iwmmxt; | |
| 467 | |
| 468 /* Nonzero if this chip is an XScale. */ | |
| 469 extern int arm_arch_xscale; | |
| 470 | |
| 471 /* Nonzero if tuning for XScale. */ | |
| 472 extern int arm_tune_xscale; | |
| 473 | |
| 474 /* Nonzero if tuning for stores via the write buffer. */ | |
| 475 extern int arm_tune_wbuf; | |
| 476 | |
| 477 /* Nonzero if tuning for Cortex-A9. */ | |
| 478 extern int arm_tune_cortex_a9; | |
| 479 | |
| 480 /* Nonzero if we should define __THUMB_INTERWORK__ in the | |
| 481 preprocessor. | |
| 482 XXX This is a bit of a hack, it's intended to help work around | |
| 483 problems in GLD which doesn't understand that armv5t code is | |
| 484 interworking clean. */ | |
| 485 extern int arm_cpp_interwork; | |
| 486 | |
| 487 /* Nonzero if chip supports Thumb 2. */ | |
| 488 extern int arm_arch_thumb2; | |
| 489 | |
| 490 /* Nonzero if chip supports integer division instruction. */ | |
| 491 extern int arm_arch_hwdiv; | |
| 492 | |
| 493 #ifndef TARGET_DEFAULT | |
| 494 #define TARGET_DEFAULT (MASK_APCS_FRAME) | |
| 495 #endif | |
| 496 | |
| 497 /* Nonzero if PIC code requires explicit qualifiers to generate | |
| 498 PLT and GOT relocs rather than the assembler doing so implicitly. | |
| 499 Subtargets can override these if required. */ | |
| 500 #ifndef NEED_GOT_RELOC | |
| 501 #define NEED_GOT_RELOC 0 | |
| 502 #endif | |
| 503 #ifndef NEED_PLT_RELOC | |
| 504 #define NEED_PLT_RELOC 0 | |
| 505 #endif | |
| 506 | |
| 507 /* Nonzero if we need to refer to the GOT with a PC-relative | |
| 508 offset. In other words, generate | |
| 509 | |
| 510 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] | |
| 511 | |
| 512 rather than | |
| 513 | |
| 514 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) | |
| 515 | |
| 516 The default is true, which matches NetBSD. Subtargets can | |
| 517 override this if required. */ | |
| 518 #ifndef GOT_PCREL | |
| 519 #define GOT_PCREL 1 | |
| 520 #endif | |
| 521 | |
| 522 /* Target machine storage Layout. */ | |
| 523 | |
| 524 | |
| 525 /* Define this macro if it is advisable to hold scalars in registers | |
| 526 in a wider mode than that declared by the program. In such cases, | |
| 527 the value is constrained to be within the bounds of the declared | |
| 528 type, but kept valid in the wider mode. The signedness of the | |
| 529 extension may differ from that of the type. */ | |
| 530 | |
| 531 /* It is far faster to zero extend chars than to sign extend them */ | |
| 532 | |
| 533 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
| 534 if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
| 535 && GET_MODE_SIZE (MODE) < 4) \ | |
| 536 { \ | |
| 537 if (MODE == QImode) \ | |
| 538 UNSIGNEDP = 1; \ | |
| 539 else if (MODE == HImode) \ | |
| 540 UNSIGNEDP = 1; \ | |
| 541 (MODE) = SImode; \ | |
| 542 } | |
| 543 | |
| 544 /* Define this if most significant bit is lowest numbered | |
| 545 in instructions that operate on numbered bit-fields. */ | |
| 546 #define BITS_BIG_ENDIAN 0 | |
| 547 | |
| 548 /* Define this if most significant byte of a word is the lowest numbered. | |
| 549 Most ARM processors are run in little endian mode, so that is the default. | |
| 550 If you want to have it run-time selectable, change the definition in a | |
| 551 cover file to be TARGET_BIG_ENDIAN. */ | |
| 552 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) | |
| 553 | |
| 554 /* Define this if most significant word of a multiword number is the lowest | |
| 555 numbered. | |
| 556 This is always false, even when in big-endian mode. */ | |
| 557 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) | |
| 558 | |
| 559 /* Define this if most significant word of doubles is the lowest numbered. | |
| 560 The rules are different based on whether or not we use FPA-format, | |
| 561 VFP-format or some other floating point co-processor's format doubles. */ | |
| 562 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ()) | |
| 563 | |
| 564 #define UNITS_PER_WORD 4 | |
| 565 | |
| 566 /* True if natural alignment is used for doubleword types. */ | |
| 567 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED | |
| 568 | |
| 569 #define DOUBLEWORD_ALIGNMENT 64 | |
| 570 | |
| 571 #define PARM_BOUNDARY 32 | |
| 572 | |
| 573 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) | |
| 574 | |
| 575 #define PREFERRED_STACK_BOUNDARY \ | |
| 576 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) | |
| 577 | |
|
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578 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32) |
| 0 | 579 |
| 580 /* The lowest bit is used to indicate Thumb-mode functions, so the | |
| 581 vbit must go into the delta field of pointers to member | |
| 582 functions. */ | |
| 583 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
| 584 | |
| 585 #define EMPTY_FIELD_BOUNDARY 32 | |
| 586 | |
| 587 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) | |
| 588 | |
| 589 /* XXX Blah -- this macro is used directly by libobjc. Since it | |
| 590 supports no vector modes, cut out the complexity and fall back | |
| 591 on BIGGEST_FIELD_ALIGNMENT. */ | |
| 592 #ifdef IN_TARGET_LIBS | |
| 593 #define BIGGEST_FIELD_ALIGNMENT 64 | |
| 594 #endif | |
| 595 | |
| 596 /* Make strings word-aligned so strcpy from constants will be faster. */ | |
| 597 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) | |
| 598 | |
| 599 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
| 600 ((TREE_CODE (EXP) == STRING_CST \ | |
| 601 && !optimize_size \ | |
| 602 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ | |
| 603 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) | |
| 604 | |
| 605 /* Align definitions of arrays, unions and structures so that | |
| 606 initializations and copies can be made more efficient. This is not | |
| 607 ABI-changing, so it only affects places where we can see the | |
|
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608 definition. Increasing the alignment tends to introduce padding, |
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609 so don't do this when optimizing for size/conserving stack space. */ |
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610 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ |
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611 (((COND) && ((ALIGN) < BITS_PER_WORD) \ |
| 0 | 612 && (TREE_CODE (EXP) == ARRAY_TYPE \ |
| 613 || TREE_CODE (EXP) == UNION_TYPE \ | |
| 614 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
| 615 | |
|
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616 /* Align global data. */ |
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617 #define DATA_ALIGNMENT(EXP, ALIGN) \ |
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618 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) |
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619 |
| 0 | 620 /* Similarly, make sure that objects on the stack are sensibly aligned. */ |
|
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621 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ |
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622 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) |
| 0 | 623 |
| 624 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the | |
| 625 value set in previous versions of this toolchain was 8, which produces more | |
| 626 compact structures. The command line option -mstructure_size_boundary=<n> | |
| 627 can be used to change this value. For compatibility with the ARM SDK | |
| 628 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI | |
| 629 0020D) page 2-20 says "Structures are aligned on word boundaries". | |
| 630 The AAPCS specifies a value of 8. */ | |
| 631 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary | |
| 632 extern int arm_structure_size_boundary; | |
| 633 | |
| 634 /* This is the value used to initialize arm_structure_size_boundary. If a | |
| 635 particular arm target wants to change the default value it should change | |
| 636 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h | |
| 637 for an example of this. */ | |
| 638 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY | |
| 639 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 | |
| 640 #endif | |
| 641 | |
| 642 /* Nonzero if move instructions will actually fail to work | |
| 643 when given unaligned data. */ | |
| 644 #define STRICT_ALIGNMENT 1 | |
| 645 | |
| 646 /* wchar_t is unsigned under the AAPCS. */ | |
| 647 #ifndef WCHAR_TYPE | |
| 648 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") | |
| 649 | |
| 650 #define WCHAR_TYPE_SIZE BITS_PER_WORD | |
| 651 #endif | |
| 652 | |
| 653 #ifndef SIZE_TYPE | |
| 654 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") | |
| 655 #endif | |
| 656 | |
| 657 #ifndef PTRDIFF_TYPE | |
| 658 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") | |
| 659 #endif | |
| 660 | |
| 661 /* AAPCS requires that structure alignment is affected by bitfields. */ | |
| 662 #ifndef PCC_BITFIELD_TYPE_MATTERS | |
| 663 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED | |
| 664 #endif | |
| 665 | |
| 666 | |
| 667 /* Standard register usage. */ | |
| 668 | |
| 669 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): | |
| 670 (S - saved over call). | |
| 671 | |
| 672 r0 * argument word/integer result | |
| 673 r1-r3 argument word | |
| 674 | |
| 675 r4-r8 S register variable | |
| 676 r9 S (rfp) register variable (real frame pointer) | |
| 677 | |
| 678 r10 F S (sl) stack limit (used by -mapcs-stack-check) | |
| 679 r11 F S (fp) argument pointer | |
| 680 r12 (ip) temp workspace | |
| 681 r13 F S (sp) lower end of current stack frame | |
| 682 r14 (lr) link address/workspace | |
| 683 r15 F (pc) program counter | |
| 684 | |
| 685 f0 floating point result | |
| 686 f1-f3 floating point scratch | |
| 687 | |
| 688 f4-f7 S floating point variable | |
| 689 | |
| 690 cc This is NOT a real register, but is used internally | |
| 691 to represent things that use or set the condition | |
| 692 codes. | |
| 693 sfp This isn't either. It is used during rtl generation | |
| 694 since the offset between the frame pointer and the | |
| 695 auto's isn't known until after register allocation. | |
| 696 afp Nor this, we only need this because of non-local | |
| 697 goto. Without it fp appears to be used and the | |
| 698 elimination code won't get rid of sfp. It tracks | |
| 699 fp exactly at all times. | |
| 700 | |
|
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701 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ |
| 0 | 702 |
| 703 /* | |
| 704 mvf0 Cirrus floating point result | |
| 705 mvf1-mvf3 Cirrus floating point scratch | |
| 706 mvf4-mvf15 S Cirrus floating point variable. */ | |
| 707 | |
| 708 /* s0-s15 VFP scratch (aka d0-d7). | |
| 709 s16-s31 S VFP variable (aka d8-d15). | |
| 710 vfpcc Not a real register. Represents the VFP condition | |
| 711 code flags. */ | |
| 712 | |
| 713 /* The stack backtrace structure is as follows: | |
| 714 fp points to here: | save code pointer | [fp] | |
| 715 | return link value | [fp, #-4] | |
| 716 | return sp value | [fp, #-8] | |
| 717 | return fp value | [fp, #-12] | |
| 718 [| saved r10 value |] | |
| 719 [| saved r9 value |] | |
| 720 [| saved r8 value |] | |
| 721 [| saved r7 value |] | |
| 722 [| saved r6 value |] | |
| 723 [| saved r5 value |] | |
| 724 [| saved r4 value |] | |
| 725 [| saved r3 value |] | |
| 726 [| saved r2 value |] | |
| 727 [| saved r1 value |] | |
| 728 [| saved r0 value |] | |
| 729 [| saved f7 value |] three words | |
| 730 [| saved f6 value |] three words | |
| 731 [| saved f5 value |] three words | |
| 732 [| saved f4 value |] three words | |
| 733 r0-r3 are not normally saved in a C function. */ | |
| 734 | |
| 735 /* 1 for registers that have pervasive standard uses | |
| 736 and are not available for the register allocator. */ | |
| 737 #define FIXED_REGISTERS \ | |
| 738 { \ | |
| 739 0,0,0,0,0,0,0,0, \ | |
| 740 0,0,0,0,0,1,0,1, \ | |
| 741 0,0,0,0,0,0,0,0, \ | |
| 742 1,1,1, \ | |
| 743 1,1,1,1,1,1,1,1, \ | |
| 744 1,1,1,1,1,1,1,1, \ | |
| 745 1,1,1,1,1,1,1,1, \ | |
| 746 1,1,1,1,1,1,1,1, \ | |
| 747 1,1,1,1, \ | |
| 748 1,1,1,1,1,1,1,1, \ | |
| 749 1,1,1,1,1,1,1,1, \ | |
| 750 1,1,1,1,1,1,1,1, \ | |
| 751 1,1,1,1,1,1,1,1, \ | |
| 752 1,1,1,1,1,1,1,1, \ | |
| 753 1,1,1,1,1,1,1,1, \ | |
| 754 1,1,1,1,1,1,1,1, \ | |
| 755 1,1,1,1,1,1,1,1, \ | |
| 756 1 \ | |
| 757 } | |
| 758 | |
| 759 /* 1 for registers not available across function calls. | |
| 760 These must include the FIXED_REGISTERS and also any | |
| 761 registers that can be used without being saved. | |
| 762 The latter must include the registers where values are returned | |
| 763 and the register where structure-value addresses are passed. | |
| 764 Aside from that, you can include as many other registers as you like. | |
| 765 The CC is not preserved over function calls on the ARM 6, so it is | |
| 766 easier to assume this for all. SFP is preserved, since FP is. */ | |
| 767 #define CALL_USED_REGISTERS \ | |
| 768 { \ | |
| 769 1,1,1,1,0,0,0,0, \ | |
| 770 0,0,0,0,1,1,1,1, \ | |
| 771 1,1,1,1,0,0,0,0, \ | |
| 772 1,1,1, \ | |
| 773 1,1,1,1,1,1,1,1, \ | |
| 774 1,1,1,1,1,1,1,1, \ | |
| 775 1,1,1,1,1,1,1,1, \ | |
| 776 1,1,1,1,1,1,1,1, \ | |
| 777 1,1,1,1, \ | |
| 778 1,1,1,1,1,1,1,1, \ | |
| 779 1,1,1,1,1,1,1,1, \ | |
| 780 1,1,1,1,1,1,1,1, \ | |
| 781 1,1,1,1,1,1,1,1, \ | |
| 782 1,1,1,1,1,1,1,1, \ | |
| 783 1,1,1,1,1,1,1,1, \ | |
| 784 1,1,1,1,1,1,1,1, \ | |
| 785 1,1,1,1,1,1,1,1, \ | |
| 786 1 \ | |
| 787 } | |
| 788 | |
| 789 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE | |
| 790 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE | |
| 791 #endif | |
| 792 | |
| 793 /* These are a couple of extensions to the formats accepted | |
| 794 by asm_fprintf: | |
| 795 %@ prints out ASM_COMMENT_START | |
| 796 %r prints out REGISTER_PREFIX reg_names[arg] */ | |
| 797 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ | |
| 798 case '@': \ | |
| 799 fputs (ASM_COMMENT_START, FILE); \ | |
| 800 break; \ | |
| 801 \ | |
| 802 case 'r': \ | |
| 803 fputs (REGISTER_PREFIX, FILE); \ | |
| 804 fputs (reg_names [va_arg (ARGS, int)], FILE); \ | |
| 805 break; | |
| 806 | |
| 807 /* Round X up to the nearest word. */ | |
| 808 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) | |
| 809 | |
| 810 /* Convert fron bytes to ints. */ | |
| 811 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
| 812 | |
| 813 /* The number of (integer) registers required to hold a quantity of type MODE. | |
| 814 Also used for VFP registers. */ | |
| 815 #define ARM_NUM_REGS(MODE) \ | |
| 816 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) | |
| 817 | |
| 818 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ | |
| 819 #define ARM_NUM_REGS2(MODE, TYPE) \ | |
| 820 ARM_NUM_INTS ((MODE) == BLKmode ? \ | |
| 821 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) | |
| 822 | |
| 823 /* The number of (integer) argument register available. */ | |
| 824 #define NUM_ARG_REGS 4 | |
| 825 | |
|
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826 /* And similarly for the VFP. */ |
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827 #define NUM_VFP_ARG_REGS 16 |
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828 |
| 0 | 829 /* Return the register number of the N'th (integer) argument. */ |
| 830 #define ARG_REGISTER(N) (N - 1) | |
| 831 | |
| 832 /* Specify the registers used for certain standard purposes. | |
| 833 The values of these macros are register numbers. */ | |
| 834 | |
| 835 /* The number of the last argument register. */ | |
| 836 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) | |
| 837 | |
| 838 /* The numbers of the Thumb register ranges. */ | |
| 839 #define FIRST_LO_REGNUM 0 | |
| 840 #define LAST_LO_REGNUM 7 | |
| 841 #define FIRST_HI_REGNUM 8 | |
| 842 #define LAST_HI_REGNUM 11 | |
| 843 | |
|
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844 /* Overridden by config/arm/bpabi.h. */ |
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845 #ifndef ARM_UNWIND_INFO |
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846 #define ARM_UNWIND_INFO 0 |
| 0 | 847 #endif |
| 848 | |
| 849 /* Use r0 and r1 to pass exception handling information. */ | |
| 850 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) | |
| 851 | |
| 852 /* The register that holds the return address in exception handlers. */ | |
| 853 #define ARM_EH_STACKADJ_REGNUM 2 | |
| 854 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) | |
| 855 | |
| 856 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain | |
| 857 as an invisible last argument (possible since varargs don't exist in | |
| 858 Pascal), so the following is not true. */ | |
| 859 #define STATIC_CHAIN_REGNUM 12 | |
| 860 | |
| 861 /* Define this to be where the real frame pointer is if it is not possible to | |
| 862 work out the offset between the frame pointer and the automatic variables | |
| 863 until after register allocation has taken place. FRAME_POINTER_REGNUM | |
| 864 should point to a special register that we will make sure is eliminated. | |
| 865 | |
| 866 For the Thumb we have another problem. The TPCS defines the frame pointer | |
| 867 as r11, and GCC believes that it is always possible to use the frame pointer | |
| 868 as base register for addressing purposes. (See comments in | |
| 869 find_reloads_address()). But - the Thumb does not allow high registers, | |
| 870 including r11, to be used as base address registers. Hence our problem. | |
| 871 | |
| 872 The solution used here, and in the old thumb port is to use r7 instead of | |
| 873 r11 as the hard frame pointer and to have special code to generate | |
| 874 backtrace structures on the stack (if required to do so via a command line | |
| 875 option) using r11. This is the only 'user visible' use of r11 as a frame | |
| 876 pointer. */ | |
| 877 #define ARM_HARD_FRAME_POINTER_REGNUM 11 | |
| 878 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 | |
| 879 | |
| 880 #define HARD_FRAME_POINTER_REGNUM \ | |
| 881 (TARGET_ARM \ | |
| 882 ? ARM_HARD_FRAME_POINTER_REGNUM \ | |
| 883 : THUMB_HARD_FRAME_POINTER_REGNUM) | |
| 884 | |
|
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885 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 |
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886 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 |
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887 |
| 0 | 888 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM |
| 889 | |
| 890 /* Register to use for pushing function arguments. */ | |
| 891 #define STACK_POINTER_REGNUM SP_REGNUM | |
| 892 | |
| 893 /* ARM floating pointer registers. */ | |
| 894 #define FIRST_FPA_REGNUM 16 | |
| 895 #define LAST_FPA_REGNUM 23 | |
| 896 #define IS_FPA_REGNUM(REGNUM) \ | |
| 897 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM)) | |
| 898 | |
| 899 #define FIRST_IWMMXT_GR_REGNUM 43 | |
| 900 #define LAST_IWMMXT_GR_REGNUM 46 | |
| 901 #define FIRST_IWMMXT_REGNUM 47 | |
| 902 #define LAST_IWMMXT_REGNUM 62 | |
| 903 #define IS_IWMMXT_REGNUM(REGNUM) \ | |
| 904 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) | |
| 905 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ | |
| 906 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) | |
| 907 | |
| 908 /* Base register for access to local variables of the function. */ | |
| 909 #define FRAME_POINTER_REGNUM 25 | |
| 910 | |
| 911 /* Base register for access to arguments of the function. */ | |
| 912 #define ARG_POINTER_REGNUM 26 | |
| 913 | |
| 914 #define FIRST_CIRRUS_FP_REGNUM 27 | |
| 915 #define LAST_CIRRUS_FP_REGNUM 42 | |
| 916 #define IS_CIRRUS_REGNUM(REGNUM) \ | |
| 917 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM)) | |
| 918 | |
| 919 #define FIRST_VFP_REGNUM 63 | |
| 920 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */ | |
| 921 #define LAST_VFP_REGNUM \ | |
| 922 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) | |
| 923 | |
| 924 #define IS_VFP_REGNUM(REGNUM) \ | |
| 925 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) | |
| 926 | |
| 927 /* VFP registers are split into two types: those defined by VFP versions < 3 | |
| 928 have D registers overlaid on consecutive pairs of S registers. VFP version 3 | |
| 929 defines 16 new D registers (d16-d31) which, for simplicity and correctness | |
| 930 in various parts of the backend, we implement as "fake" single-precision | |
| 931 registers (which would be S32-S63, but cannot be used in that way). The | |
| 932 following macros define these ranges of registers. */ | |
| 933 #define LAST_LO_VFP_REGNUM 94 | |
| 934 #define FIRST_HI_VFP_REGNUM 95 | |
| 935 #define LAST_HI_VFP_REGNUM 126 | |
| 936 | |
| 937 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ | |
| 938 ((REGNUM) <= LAST_LO_VFP_REGNUM) | |
| 939 | |
| 940 /* DFmode values are only valid in even register pairs. */ | |
| 941 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ | |
| 942 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) | |
| 943 | |
| 944 /* Neon Quad values must start at a multiple of four registers. */ | |
| 945 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ | |
| 946 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) | |
| 947 | |
| 948 /* Neon structures of vectors must be in even register pairs and there | |
| 949 must be enough registers available. Because of various patterns | |
| 950 requiring quad registers, we require them to start at a multiple of | |
| 951 four. */ | |
| 952 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ | |
| 953 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ | |
| 954 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) | |
| 955 | |
| 956 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */ | |
| 957 /* + 16 Cirrus registers take us up to 43. */ | |
| 958 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ | |
| 959 /* VFP (VFP3) adds 32 (64) + 1 more. */ | |
| 960 #define FIRST_PSEUDO_REGISTER 128 | |
| 961 | |
| 962 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) | |
| 963 | |
| 964 /* Value should be nonzero if functions must have frame pointers. | |
| 965 Zero means the frame pointer need not be set up (and parms may be accessed | |
| 966 via the stack pointer) in functions that seem suitable. | |
| 967 If we have to have a frame pointer we might as well make use of it. | |
| 968 APCS says that the frame pointer does not need to be pushed in leaf | |
| 969 functions, or simple tail call functions. */ | |
| 970 | |
| 971 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
| 972 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
| 973 #endif | |
| 974 | |
| 975 /* Return number of consecutive hard regs needed starting at reg REGNO | |
| 976 to hold something of mode MODE. | |
| 977 This is ordinarily the length in words of a value of mode MODE | |
| 978 but can be less for certain modes in special long registers. | |
| 979 | |
| 980 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP | |
| 981 mode. */ | |
| 982 #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
| 983 ((TARGET_32BIT \ | |
| 984 && REGNO >= FIRST_FPA_REGNUM \ | |
| 985 && REGNO != FRAME_POINTER_REGNUM \ | |
| 986 && REGNO != ARG_POINTER_REGNUM) \ | |
| 987 && !IS_VFP_REGNUM (REGNO) \ | |
| 988 ? 1 : ARM_NUM_REGS (MODE)) | |
| 989 | |
| 990 /* Return true if REGNO is suitable for holding a quantity of type MODE. */ | |
| 991 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
| 992 arm_hard_regno_mode_ok ((REGNO), (MODE)) | |
| 993 | |
| 994 /* Value is 1 if it is a good idea to tie two pseudo registers | |
| 995 when one has mode MODE1 and one has mode MODE2. | |
| 996 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
| 997 for any hard reg, then this must be 0 for correct output. */ | |
| 998 #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
| 999 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
| 1000 | |
| 1001 #define VALID_IWMMXT_REG_MODE(MODE) \ | |
| 1002 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) | |
| 1003 | |
| 1004 /* Modes valid for Neon D registers. */ | |
| 1005 #define VALID_NEON_DREG_MODE(MODE) \ | |
| 1006 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ | |
| 1007 || (MODE) == V2SFmode || (MODE) == DImode) | |
| 1008 | |
| 1009 /* Modes valid for Neon Q registers. */ | |
| 1010 #define VALID_NEON_QREG_MODE(MODE) \ | |
| 1011 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ | |
| 1012 || (MODE) == V4SFmode || (MODE) == V2DImode) | |
| 1013 | |
| 1014 /* Structure modes valid for Neon registers. */ | |
| 1015 #define VALID_NEON_STRUCT_MODE(MODE) \ | |
| 1016 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ | |
| 1017 || (MODE) == CImode || (MODE) == XImode) | |
| 1018 | |
|
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1019 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ |
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1020 extern int arm_regs_in_sequence[]; |
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1021 |
| 0 | 1022 /* The order in which register should be allocated. It is good to use ip |
| 1023 since no saving is required (though calls clobber it) and it never contains | |
| 1024 function parameters. It is quite good to use lr since other calls may | |
| 1025 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is | |
| 1026 least likely to contain a function parameter; in addition results are | |
| 1027 returned in r0. | |
| 1028 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), | |
| 1029 then D8-D15. The reason for doing this is to attempt to reduce register | |
| 1030 pressure when both single- and double-precision registers are used in a | |
| 1031 function. */ | |
| 1032 | |
| 1033 #define REG_ALLOC_ORDER \ | |
| 1034 { \ | |
| 1035 3, 2, 1, 0, 12, 14, 4, 5, \ | |
| 1036 6, 7, 8, 10, 9, 11, 13, 15, \ | |
| 1037 16, 17, 18, 19, 20, 21, 22, 23, \ | |
| 1038 27, 28, 29, 30, 31, 32, 33, 34, \ | |
| 1039 35, 36, 37, 38, 39, 40, 41, 42, \ | |
| 1040 43, 44, 45, 46, 47, 48, 49, 50, \ | |
| 1041 51, 52, 53, 54, 55, 56, 57, 58, \ | |
| 1042 59, 60, 61, 62, \ | |
| 1043 24, 25, 26, \ | |
| 1044 95, 96, 97, 98, 99, 100, 101, 102, \ | |
| 1045 103, 104, 105, 106, 107, 108, 109, 110, \ | |
| 1046 111, 112, 113, 114, 115, 116, 117, 118, \ | |
| 1047 119, 120, 121, 122, 123, 124, 125, 126, \ | |
| 1048 78, 77, 76, 75, 74, 73, 72, 71, \ | |
| 1049 70, 69, 68, 67, 66, 65, 64, 63, \ | |
| 1050 79, 80, 81, 82, 83, 84, 85, 86, \ | |
| 1051 87, 88, 89, 90, 91, 92, 93, 94, \ | |
| 1052 127 \ | |
| 1053 } | |
| 1054 | |
| 1055 /* Use different register alloc ordering for Thumb. */ | |
|
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1056 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () |
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1057 |
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1058 /* Tell IRA to use the order we define rather than messing it up with its |
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1059 own cost calculations. */ |
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1060 #define HONOR_REG_ALLOC_ORDER |
| 0 | 1061 |
| 1062 /* Interrupt functions can only use registers that have already been | |
| 1063 saved by the prologue, even if they would normally be | |
| 1064 call-clobbered. */ | |
| 1065 #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
| 1066 (! IS_INTERRUPT (cfun->machine->func_type) || \ | |
| 1067 df_regs_ever_live_p (DST)) | |
| 1068 | |
| 1069 /* Register and constant classes. */ | |
| 1070 | |
| 1071 /* Register classes: used to be simple, just all ARM regs or all FPA regs | |
| 1072 Now that the Thumb is involved it has become more complicated. */ | |
| 1073 enum reg_class | |
| 1074 { | |
| 1075 NO_REGS, | |
| 1076 FPA_REGS, | |
| 1077 CIRRUS_REGS, | |
| 1078 VFP_D0_D7_REGS, | |
| 1079 VFP_LO_REGS, | |
| 1080 VFP_HI_REGS, | |
| 1081 VFP_REGS, | |
| 1082 IWMMXT_GR_REGS, | |
| 1083 IWMMXT_REGS, | |
| 1084 LO_REGS, | |
| 1085 STACK_REG, | |
| 1086 BASE_REGS, | |
| 1087 HI_REGS, | |
| 1088 CC_REG, | |
| 1089 VFPCC_REG, | |
| 1090 GENERAL_REGS, | |
| 1091 CORE_REGS, | |
| 1092 ALL_REGS, | |
| 1093 LIM_REG_CLASSES | |
| 1094 }; | |
| 1095 | |
| 1096 #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
| 1097 | |
| 1098 /* Give names of register classes as strings for dump file. */ | |
| 1099 #define REG_CLASS_NAMES \ | |
| 1100 { \ | |
| 1101 "NO_REGS", \ | |
| 1102 "FPA_REGS", \ | |
| 1103 "CIRRUS_REGS", \ | |
| 1104 "VFP_D0_D7_REGS", \ | |
| 1105 "VFP_LO_REGS", \ | |
| 1106 "VFP_HI_REGS", \ | |
| 1107 "VFP_REGS", \ | |
| 1108 "IWMMXT_GR_REGS", \ | |
| 1109 "IWMMXT_REGS", \ | |
| 1110 "LO_REGS", \ | |
| 1111 "STACK_REG", \ | |
| 1112 "BASE_REGS", \ | |
| 1113 "HI_REGS", \ | |
| 1114 "CC_REG", \ | |
| 1115 "VFPCC_REG", \ | |
| 1116 "GENERAL_REGS", \ | |
| 1117 "CORE_REGS", \ | |
| 1118 "ALL_REGS", \ | |
| 1119 } | |
| 1120 | |
| 1121 /* Define which registers fit in which classes. | |
| 1122 This is an initializer for a vector of HARD_REG_SET | |
| 1123 of length N_REG_CLASSES. */ | |
| 1124 #define REG_CLASS_CONTENTS \ | |
| 1125 { \ | |
| 1126 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
| 1127 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \ | |
| 1128 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \ | |
| 1129 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \ | |
| 1130 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \ | |
| 1131 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \ | |
| 1132 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \ | |
| 1133 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \ | |
| 1134 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \ | |
| 1135 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ | |
| 1136 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ | |
| 1137 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ | |
| 1138 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ | |
| 1139 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \ | |
| 1140 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \ | |
|
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1141 { 0x0000DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ |
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1142 { 0x0000FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ |
| 0 | 1143 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \ |
| 1144 } | |
| 1145 | |
| 1146 /* Any of the VFP register classes. */ | |
| 1147 #define IS_VFP_CLASS(X) \ | |
| 1148 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ | |
| 1149 || (X) == VFP_HI_REGS || (X) == VFP_REGS) | |
| 1150 | |
| 1151 /* The same information, inverted: | |
| 1152 Return the class number of the smallest class containing | |
| 1153 reg number REGNO. This could be a conditional expression | |
| 1154 or could index an array. */ | |
| 1155 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) | |
| 1156 | |
| 1157 /* The following macro defines cover classes for Integrated Register | |
| 1158 Allocator. Cover classes is a set of non-intersected register | |
| 1159 classes covering all hard registers used for register allocation | |
| 1160 purpose. Any move between two registers of a cover class should be | |
| 1161 cheaper than load or store of the registers. The macro value is | |
| 1162 array of register classes with LIM_REG_CLASSES used as the end | |
| 1163 marker. */ | |
| 1164 | |
| 1165 #define IRA_COVER_CLASSES \ | |
| 1166 { \ | |
| 1167 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\ | |
| 1168 LIM_REG_CLASSES \ | |
| 1169 } | |
| 1170 | |
| 1171 /* FPA registers can't do subreg as all values are reformatted to internal | |
| 1172 precision. VFP registers may only be accessed in the mode they | |
| 1173 were set. */ | |
| 1174 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
| 1175 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ | |
| 1176 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \ | |
| 1177 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \ | |
| 1178 : 0) | |
| 1179 | |
| 1180 /* The class value for index registers, and the one for base regs. */ | |
| 1181 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) | |
| 1182 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) | |
| 1183 | |
| 1184 /* For the Thumb the high registers cannot be used as base registers | |
| 1185 when addressing quantities in QI or HI mode; if we don't know the | |
| 1186 mode, then we must be conservative. */ | |
| 1187 #define MODE_BASE_REG_CLASS(MODE) \ | |
| 1188 (TARGET_32BIT ? CORE_REGS : \ | |
| 1189 (((MODE) == SImode) ? BASE_REGS : LO_REGS)) | |
| 1190 | |
| 1191 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS | |
| 1192 instead of BASE_REGS. */ | |
| 1193 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS | |
| 1194 | |
|
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1195 /* When this hook returns true for MODE, the compiler allows |
| 0 | 1196 registers explicitly used in the rtl to be used as spill registers |
| 1197 but prevents the compiler from extending the lifetime of these | |
| 1198 registers. */ | |
|
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1199 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ |
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1200 arm_small_register_classes_for_mode_p |
| 0 | 1201 |
| 1202 /* Given an rtx X being reloaded into a reg required to be | |
| 1203 in class CLASS, return the class of reg to actually use. | |
| 1204 In general this is just CLASS, but for the Thumb core registers and | |
| 1205 immediate constants we prefer a LO_REGS class or a subset. */ | |
| 1206 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
|
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1207 (TARGET_32BIT ? (CLASS) : \ |
| 0 | 1208 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \ |
| 1209 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \ | |
| 1210 ? LO_REGS : (CLASS))) | |
| 1211 | |
| 1212 /* Must leave BASE_REGS reloads alone */ | |
| 1213 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
| 1214 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ | |
| 1215 ? ((true_regnum (X) == -1 ? LO_REGS \ | |
| 1216 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
| 1217 : NO_REGS)) \ | |
| 1218 : NO_REGS) | |
| 1219 | |
| 1220 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
| 1221 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ | |
| 1222 ? ((true_regnum (X) == -1 ? LO_REGS \ | |
| 1223 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
| 1224 : NO_REGS)) \ | |
| 1225 : NO_REGS) | |
| 1226 | |
| 1227 /* Return the register class of a scratch register needed to copy IN into | |
| 1228 or out of a register in CLASS in MODE. If it can be done directly, | |
| 1229 NO_REGS is returned. */ | |
| 1230 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
| 1231 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ | |
| 1232 ((TARGET_VFP && TARGET_HARD_FLOAT \ | |
| 1233 && IS_VFP_CLASS (CLASS)) \ | |
| 1234 ? coproc_secondary_reload_class (MODE, X, FALSE) \ | |
| 1235 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ | |
| 1236 ? coproc_secondary_reload_class (MODE, X, TRUE) \ | |
| 1237 : TARGET_32BIT \ | |
| 1238 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ | |
| 1239 ? GENERAL_REGS : NO_REGS) \ | |
| 1240 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) | |
| 1241 | |
| 1242 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ | |
| 1243 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
| 1244 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ | |
| 1245 ((TARGET_VFP && TARGET_HARD_FLOAT \ | |
| 1246 && IS_VFP_CLASS (CLASS)) \ | |
| 1247 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ | |
| 1248 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ | |
| 1249 coproc_secondary_reload_class (MODE, X, TRUE) : \ | |
| 1250 /* Cannot load constants into Cirrus registers. */ \ | |
| 1251 (TARGET_MAVERICK && TARGET_HARD_FLOAT \ | |
| 1252 && (CLASS) == CIRRUS_REGS \ | |
| 1253 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \ | |
| 1254 ? GENERAL_REGS : \ | |
| 1255 (TARGET_32BIT ? \ | |
| 1256 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ | |
| 1257 && CONSTANT_P (X)) \ | |
| 1258 ? GENERAL_REGS : \ | |
| 1259 (((MODE) == HImode && ! arm_arch4 \ | |
| 1260 && (GET_CODE (X) == MEM \ | |
| 1261 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ | |
| 1262 && true_regnum (X) == -1))) \ | |
| 1263 ? GENERAL_REGS : NO_REGS) \ | |
| 1264 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) | |
| 1265 | |
| 1266 /* Try a machine-dependent way of reloading an illegitimate address | |
| 1267 operand. If we find one, push the reload and jump to WIN. This | |
| 1268 macro is used in only one place: `find_reloads_address' in reload.c. | |
| 1269 | |
| 1270 For the ARM, we wish to handle large displacements off a base | |
| 1271 register by splitting the addend across a MOV and the mem insn. | |
| 1272 This can cut the number of reloads needed. */ | |
| 1273 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ | |
| 1274 do \ | |
| 1275 { \ | |
|
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1276 if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \ |
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1277 goto WIN; \ |
| 0 | 1278 } \ |
| 1279 while (0) | |
| 1280 | |
| 1281 /* XXX If an HImode FP+large_offset address is converted to an HImode | |
| 1282 SP+large_offset address, then reload won't know how to fix it. It sees | |
| 1283 only that SP isn't valid for HImode, and so reloads the SP into an index | |
| 1284 register, but the resulting address is still invalid because the offset | |
| 1285 is too big. We fix it here instead by reloading the entire address. */ | |
| 1286 /* We could probably achieve better results by defining PROMOTE_MODE to help | |
| 1287 cope with the variances between the Thumb's signed and unsigned byte and | |
| 1288 halfword load instructions. */ | |
| 1289 /* ??? This should be safe for thumb2, but we may be able to do better. */ | |
| 1290 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ | |
| 1291 do { \ | |
| 1292 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ | |
| 1293 if (new_x) \ | |
| 1294 { \ | |
| 1295 X = new_x; \ | |
| 1296 goto WIN; \ | |
| 1297 } \ | |
| 1298 } while (0) | |
| 1299 | |
| 1300 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ | |
| 1301 if (TARGET_ARM) \ | |
| 1302 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ | |
| 1303 else \ | |
| 1304 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) | |
| 1305 | |
| 1306 /* Return the maximum number of consecutive registers | |
| 1307 needed to represent mode MODE in a register of class CLASS. | |
| 1308 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */ | |
| 1309 #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
| 1310 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE)) | |
| 1311 | |
| 1312 /* If defined, gives a class of registers that cannot be used as the | |
| 1313 operand of a SUBREG that changes the mode of the object illegally. */ | |
| 1314 | |
|
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1315 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. |
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1316 Moves between VFP_REGS and GENERAL_REGS are a single insn, but |
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1317 it is typically more expensive than a single memory access. We set |
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1318 the cost to less than two memory accesses so that floating |
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1319 point to integer conversion does not go through memory. */ |
| 0 | 1320 #define REGISTER_MOVE_COST(MODE, FROM, TO) \ |
| 1321 (TARGET_32BIT ? \ | |
| 1322 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \ | |
| 1323 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \ | |
|
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1324 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \ |
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1325 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \ |
| 0 | 1326 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \ |
| 1327 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \ | |
| 1328 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \ | |
| 1329 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \ | |
| 1330 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \ | |
| 1331 2) \ | |
| 1332 : \ | |
| 1333 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) | |
| 1334 | |
| 1335 /* Stack layout; function entry, exit and calling. */ | |
| 1336 | |
| 1337 /* Define this if pushing a word on the stack | |
| 1338 makes the stack pointer a smaller address. */ | |
| 1339 #define STACK_GROWS_DOWNWARD 1 | |
| 1340 | |
| 1341 /* Define this to nonzero if the nominal address of the stack frame | |
| 1342 is at the high-address end of the local variables; | |
| 1343 that is, each additional local variable allocated | |
| 1344 goes at a more negative offset in the frame. */ | |
| 1345 #define FRAME_GROWS_DOWNWARD 1 | |
| 1346 | |
| 1347 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). | |
| 1348 When present, it is one word in size, and sits at the top of the frame, | |
| 1349 between the soft frame pointer and either r7 or r11. | |
| 1350 | |
| 1351 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, | |
| 1352 and only then if some outgoing arguments are passed on the stack. It would | |
| 1353 be tempting to also check whether the stack arguments are passed by indirect | |
| 1354 calls, but there seems to be no reason in principle why a post-reload pass | |
| 1355 couldn't convert a direct call into an indirect one. */ | |
| 1356 #define CALLER_INTERWORKING_SLOT_SIZE \ | |
| 1357 (TARGET_CALLER_INTERWORKING \ | |
| 1358 && crtl->outgoing_args_size != 0 \ | |
| 1359 ? UNITS_PER_WORD : 0) | |
| 1360 | |
| 1361 /* Offset within stack frame to start allocating local variables at. | |
| 1362 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
| 1363 first local allocated. Otherwise, it is the offset to the BEGINNING | |
| 1364 of the first local allocated. */ | |
| 1365 #define STARTING_FRAME_OFFSET 0 | |
| 1366 | |
| 1367 /* If we generate an insn to push BYTES bytes, | |
| 1368 this says how many the stack pointer really advances by. */ | |
| 1369 /* The push insns do not do this rounding implicitly. | |
| 1370 So don't define this. */ | |
| 1371 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ | |
| 1372 | |
| 1373 /* Define this if the maximum size of all the outgoing args is to be | |
| 1374 accumulated and pushed during the prologue. The amount can be | |
| 1375 found in the variable crtl->outgoing_args_size. */ | |
| 1376 #define ACCUMULATE_OUTGOING_ARGS 1 | |
| 1377 | |
| 1378 /* Offset of first parameter from the argument pointer register value. */ | |
| 1379 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) | |
| 1380 | |
| 1381 /* Define how to find the value returned by a library function | |
| 1382 assuming the value has mode MODE. */ | |
|
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1383 #define LIBCALL_VALUE(MODE) \ |
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1384 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \ |
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1385 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \ |
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1386 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ |
| 0 | 1387 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \ |
| 1388 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \ | |
| 1389 && GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
| 1390 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \ | |
| 1391 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \ | |
| 1392 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \ | |
| 1393 : gen_rtx_REG (MODE, ARG_REGISTER (1))) | |
| 1394 | |
|
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1395 /* 1 if REGNO is a possible register number for a function value. */ |
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1396 #define FUNCTION_VALUE_REGNO_P(REGNO) \ |
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1397 ((REGNO) == ARG_REGISTER (1) \ |
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1398 || (TARGET_AAPCS_BASED && TARGET_32BIT \ |
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1399 && TARGET_VFP && TARGET_HARD_FLOAT \ |
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1400 && (REGNO) == FIRST_VFP_REGNUM) \ |
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1401 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \ |
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1402 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \ |
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1403 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \ |
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1404 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \ |
| 0 | 1405 && TARGET_HARD_FLOAT_ABI && TARGET_FPA)) |
| 1406 | |
| 1407 /* Amount of memory needed for an untyped call to save all possible return | |
| 1408 registers. */ | |
| 1409 #define APPLY_RESULT_SIZE arm_apply_result_size() | |
| 1410 | |
| 1411 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return | |
| 1412 values must be in memory. On the ARM, they need only do so if larger | |
| 1413 than a word, or if they contain elements offset from zero in the struct. */ | |
| 1414 #define DEFAULT_PCC_STRUCT_RETURN 0 | |
| 1415 | |
| 1416 /* These bits describe the different types of function supported | |
| 1417 by the ARM backend. They are exclusive. i.e. a function cannot be both a | |
| 1418 normal function and an interworked function, for example. Knowing the | |
| 1419 type of a function is important for determining its prologue and | |
| 1420 epilogue sequences. | |
| 1421 Note value 7 is currently unassigned. Also note that the interrupt | |
| 1422 function types all have bit 2 set, so that they can be tested for easily. | |
| 1423 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the | |
| 1424 machine_function structure is initialized (to zero) func_type will | |
| 1425 default to unknown. This will force the first use of arm_current_func_type | |
| 1426 to call arm_compute_func_type. */ | |
| 1427 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ | |
| 1428 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ | |
| 1429 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ | |
| 1430 #define ARM_FT_ISR 4 /* An interrupt service routine. */ | |
| 1431 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ | |
| 1432 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ | |
| 1433 | |
| 1434 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) | |
| 1435 | |
| 1436 /* In addition functions can have several type modifiers, | |
| 1437 outlined by these bit masks: */ | |
| 1438 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ | |
| 1439 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ | |
| 1440 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ | |
| 1441 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ | |
| 1442 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ | |
| 1443 | |
| 1444 /* Some macros to test these flags. */ | |
| 1445 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) | |
| 1446 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) | |
| 1447 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) | |
| 1448 #define IS_NAKED(t) (t & ARM_FT_NAKED) | |
| 1449 #define IS_NESTED(t) (t & ARM_FT_NESTED) | |
| 1450 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) | |
| 1451 | |
| 1452 | |
| 1453 /* Structure used to hold the function stack frame layout. Offsets are | |
| 1454 relative to the stack pointer on function entry. Positive offsets are | |
| 1455 in the direction of stack growth. | |
| 1456 Only soft_frame is used in thumb mode. */ | |
| 1457 | |
|
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1458 typedef struct GTY(()) arm_stack_offsets |
| 0 | 1459 { |
| 1460 int saved_args; /* ARG_POINTER_REGNUM. */ | |
| 1461 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ | |
| 1462 int saved_regs; | |
| 1463 int soft_frame; /* FRAME_POINTER_REGNUM. */ | |
| 1464 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ | |
| 1465 int outgoing_args; /* STACK_POINTER_REGNUM. */ | |
| 1466 unsigned int saved_regs_mask; | |
| 1467 } | |
| 1468 arm_stack_offsets; | |
| 1469 | |
|
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1470 #ifndef GENERATOR_FILE |
| 0 | 1471 /* A C structure for machine-specific, per-function data. |
| 1472 This is added to the cfun structure. */ | |
|
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1473 typedef struct GTY(()) machine_function |
| 0 | 1474 { |
| 1475 /* Additional stack adjustment in __builtin_eh_throw. */ | |
| 1476 rtx eh_epilogue_sp_ofs; | |
| 1477 /* Records if LR has to be saved for far jumps. */ | |
| 1478 int far_jump_used; | |
| 1479 /* Records if ARG_POINTER was ever live. */ | |
| 1480 int arg_pointer_live; | |
| 1481 /* Records if the save of LR has been eliminated. */ | |
| 1482 int lr_save_eliminated; | |
| 1483 /* The size of the stack frame. Only valid after reload. */ | |
| 1484 arm_stack_offsets stack_offsets; | |
| 1485 /* Records the type of the current function. */ | |
| 1486 unsigned long func_type; | |
| 1487 /* Record if the function has a variable argument list. */ | |
| 1488 int uses_anonymous_args; | |
| 1489 /* Records if sibcalls are blocked because an argument | |
| 1490 register is needed to preserve stack alignment. */ | |
| 1491 int sibcall_blocked; | |
| 1492 /* The PIC register for this function. This might be a pseudo. */ | |
| 1493 rtx pic_reg; | |
| 1494 /* Labels for per-function Thumb call-via stubs. One per potential calling | |
| 1495 register. We can never call via LR or PC. We can call via SP if a | |
| 1496 trampoline happens to be on the top of the stack. */ | |
| 1497 rtx call_via[14]; | |
|
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1498 /* Set to 1 when a return insn is output, this means that the epilogue |
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1499 is not needed. */ |
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1500 int return_used_this_function; |
|
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1501 /* When outputting Thumb-1 code, record the last insn that provides |
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1502 information about condition codes, and the comparison operands. */ |
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1503 rtx thumb1_cc_insn; |
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1504 rtx thumb1_cc_op0; |
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1505 rtx thumb1_cc_op1; |
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1506 /* Also record the CC mode that is supported. */ |
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1507 enum machine_mode thumb1_cc_mode; |
| 0 | 1508 } |
| 1509 machine_function; | |
|
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1510 #endif |
| 0 | 1511 |
| 1512 /* As in the machine_function, a global set of call-via labels, for code | |
| 1513 that is in text_section. */ | |
| 1514 extern GTY(()) rtx thumb_call_via_label[14]; | |
| 1515 | |
|
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1516 /* The number of potential ways of assigning to a co-processor. */ |
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1517 #define ARM_NUM_COPROC_SLOTS 1 |
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1518 |
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1519 /* Enumeration of procedure calling standard variants. We don't really |
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1520 support all of these yet. */ |
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1521 enum arm_pcs |
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1522 { |
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1523 ARM_PCS_AAPCS, /* Base standard AAPCS. */ |
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1524 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ |
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1525 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ |
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1526 /* This must be the last AAPCS variant. */ |
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1527 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ |
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1528 ARM_PCS_ATPCS, /* ATPCS. */ |
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1529 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ |
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1530 ARM_PCS_UNKNOWN |
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1531 }; |
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1532 |
|
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1533 /* Default procedure calling standard of current compilation unit. */ |
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1534 extern enum arm_pcs arm_pcs_default; |
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1535 |
| 0 | 1536 /* A C type for declaring a variable that is used as the first argument of |
|
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1537 `FUNCTION_ARG' and other related values. */ |
| 0 | 1538 typedef struct |
| 1539 { | |
| 1540 /* This is the number of registers of arguments scanned so far. */ | |
| 1541 int nregs; | |
| 1542 /* This is the number of iWMMXt register arguments scanned so far. */ | |
| 1543 int iwmmxt_nregs; | |
| 1544 int named_count; | |
| 1545 int nargs; | |
|
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1546 /* Which procedure call variant to use for this call. */ |
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1547 enum arm_pcs pcs_variant; |
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1548 |
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1549 /* AAPCS related state tracking. */ |
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1550 int aapcs_arg_processed; /* No need to lay out this argument again. */ |
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1551 int aapcs_cprc_slot; /* Index of co-processor rules to handle |
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1552 this argument, or -1 if using core |
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1553 registers. */ |
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1554 int aapcs_ncrn; |
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1555 int aapcs_next_ncrn; |
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1556 rtx aapcs_reg; /* Register assigned to this argument. */ |
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1557 int aapcs_partial; /* How many bytes are passed in regs (if |
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1558 split between core regs and stack. |
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1559 Zero otherwise. */ |
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1560 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; |
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1561 int can_split; /* Argument can be split between core regs |
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1562 and the stack. */ |
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1563 /* Private data for tracking VFP register allocation */ |
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1564 unsigned aapcs_vfp_regs_free; |
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1565 unsigned aapcs_vfp_reg_alloc; |
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1566 int aapcs_vfp_rcount; |
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1567 MACHMODE aapcs_vfp_rmode; |
| 0 | 1568 } CUMULATIVE_ARGS; |
| 1569 | |
| 1570 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ | |
| 1571 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) | |
| 1572 | |
| 1573 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ | |
| 1574 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) | |
| 1575 | |
| 1576 /* For AAPCS, padding should never be below the argument. For other ABIs, | |
| 1577 * mimic the default. */ | |
| 1578 #define PAD_VARARGS_DOWN \ | |
| 1579 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) | |
| 1580 | |
| 1581 /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
| 1582 for a call to a function whose data type is FNTYPE. | |
| 1583 For a library call, FNTYPE is 0. | |
| 1584 On the ARM, the offset starts at 0. */ | |
| 1585 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ | |
| 1586 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) | |
| 1587 | |
| 1588 /* 1 if N is a possible register number for function argument passing. | |
| 1589 On the ARM, r0-r3 are used to pass args. */ | |
|
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1590 #define FUNCTION_ARG_REGNO_P(REGNO) \ |
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1591 (IN_RANGE ((REGNO), 0, 3) \ |
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1592 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \ |
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1593 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ |
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1594 || (TARGET_IWMMXT_ABI \ |
| 0 | 1595 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) |
| 1596 | |
| 1597 | |
| 1598 /* If your target environment doesn't prefix user functions with an | |
| 1599 underscore, you may wish to re-define this to prevent any conflicts. */ | |
| 1600 #ifndef ARM_MCOUNT_NAME | |
| 1601 #define ARM_MCOUNT_NAME "*mcount" | |
| 1602 #endif | |
| 1603 | |
| 1604 /* Call the function profiler with a given profile label. The Acorn | |
| 1605 compiler puts this BEFORE the prolog but gcc puts it afterwards. | |
| 1606 On the ARM the full profile code will look like: | |
| 1607 .data | |
| 1608 LP1 | |
| 1609 .word 0 | |
| 1610 .text | |
| 1611 mov ip, lr | |
| 1612 bl mcount | |
| 1613 .word LP1 | |
| 1614 | |
| 1615 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER | |
| 1616 will output the .text section. | |
| 1617 | |
| 1618 The ``mov ip,lr'' seems like a good idea to stick with cc convention. | |
| 1619 ``prof'' doesn't seem to mind about this! | |
| 1620 | |
| 1621 Note - this version of the code is designed to work in both ARM and | |
| 1622 Thumb modes. */ | |
| 1623 #ifndef ARM_FUNCTION_PROFILER | |
| 1624 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ | |
| 1625 { \ | |
| 1626 char temp[20]; \ | |
| 1627 rtx sym; \ | |
| 1628 \ | |
| 1629 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ | |
| 1630 IP_REGNUM, LR_REGNUM); \ | |
| 1631 assemble_name (STREAM, ARM_MCOUNT_NAME); \ | |
| 1632 fputc ('\n', STREAM); \ | |
| 1633 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ | |
| 1634 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ | |
| 1635 assemble_aligned_integer (UNITS_PER_WORD, sym); \ | |
| 1636 } | |
| 1637 #endif | |
| 1638 | |
| 1639 #ifdef THUMB_FUNCTION_PROFILER | |
| 1640 #define FUNCTION_PROFILER(STREAM, LABELNO) \ | |
| 1641 if (TARGET_ARM) \ | |
| 1642 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ | |
| 1643 else \ | |
| 1644 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) | |
| 1645 #else | |
| 1646 #define FUNCTION_PROFILER(STREAM, LABELNO) \ | |
| 1647 ARM_FUNCTION_PROFILER (STREAM, LABELNO) | |
| 1648 #endif | |
| 1649 | |
| 1650 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
| 1651 the stack pointer does not matter. The value is tested only in | |
| 1652 functions that have frame pointers. | |
| 1653 No definition is equivalent to always zero. | |
| 1654 | |
| 1655 On the ARM, the function epilogue recovers the stack pointer from the | |
| 1656 frame. */ | |
| 1657 #define EXIT_IGNORE_STACK 1 | |
| 1658 | |
| 1659 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM) | |
| 1660 | |
| 1661 /* Determine if the epilogue should be output as RTL. | |
| 1662 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
| 1663 #define USE_RETURN_INSN(ISCOND) \ | |
|
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1664 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) |
| 0 | 1665 |
| 1666 /* Definitions for register eliminations. | |
| 1667 | |
| 1668 This is an array of structures. Each structure initializes one pair | |
| 1669 of eliminable registers. The "from" register number is given first, | |
| 1670 followed by "to". Eliminations of the same "from" register are listed | |
| 1671 in order of preference. | |
| 1672 | |
| 1673 We have two registers that can be eliminated on the ARM. First, the | |
| 1674 arg pointer register can often be eliminated in favor of the stack | |
| 1675 pointer register. Secondly, the pseudo frame pointer register can always | |
| 1676 be eliminated; it is replaced with either the stack or the real frame | |
| 1677 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM | |
| 1678 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ | |
| 1679 | |
| 1680 #define ELIMINABLE_REGS \ | |
| 1681 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
| 1682 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ | |
| 1683 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
| 1684 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ | |
| 1685 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
| 1686 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
| 1687 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} | |
| 1688 | |
| 1689 /* Define the offset between two registers, one to be eliminated, and the | |
| 1690 other its replacement, at the start of a routine. */ | |
| 1691 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
| 1692 if (TARGET_ARM) \ | |
| 1693 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ | |
| 1694 else \ | |
| 1695 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) | |
| 1696 | |
| 1697 /* Special case handling of the location of arguments passed on the stack. */ | |
| 1698 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) | |
| 1699 | |
| 1700 /* Initialize data used by insn expanders. This is called from insn_emit, | |
| 1701 once for every function before code is generated. */ | |
| 1702 #define INIT_EXPANDERS arm_init_expanders () | |
| 1703 | |
| 1704 /* Length in units of the trampoline for entering a nested function. */ | |
| 1705 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) | |
| 1706 | |
| 1707 /* Alignment required for a trampoline in bits. */ | |
| 1708 #define TRAMPOLINE_ALIGNMENT 32 | |
| 1709 | |
| 1710 /* Addressing modes, and classification of registers for them. */ | |
| 1711 #define HAVE_POST_INCREMENT 1 | |
| 1712 #define HAVE_PRE_INCREMENT TARGET_32BIT | |
| 1713 #define HAVE_POST_DECREMENT TARGET_32BIT | |
| 1714 #define HAVE_PRE_DECREMENT TARGET_32BIT | |
| 1715 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT | |
| 1716 #define HAVE_POST_MODIFY_DISP TARGET_32BIT | |
| 1717 #define HAVE_PRE_MODIFY_REG TARGET_32BIT | |
| 1718 #define HAVE_POST_MODIFY_REG TARGET_32BIT | |
| 1719 | |
| 1720 /* Macros to check register numbers against specific register classes. */ | |
| 1721 | |
| 1722 /* These assume that REGNO is a hard or pseudo reg number. | |
| 1723 They give nonzero only if REGNO is a hard reg of the suitable class | |
| 1724 or a pseudo reg currently allocated to a suitable hard reg. | |
| 1725 Since they use reg_renumber, they are safe only once reg_renumber | |
| 1726 has been allocated, which happens in local-alloc.c. */ | |
| 1727 #define TEST_REGNO(R, TEST, VALUE) \ | |
| 1728 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) | |
| 1729 | |
| 1730 /* Don't allow the pc to be used. */ | |
| 1731 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ | |
| 1732 (TEST_REGNO (REGNO, <, PC_REGNUM) \ | |
| 1733 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ | |
| 1734 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) | |
| 1735 | |
| 1736 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
| 1737 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ | |
| 1738 || (GET_MODE_SIZE (MODE) >= 4 \ | |
| 1739 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) | |
| 1740 | |
| 1741 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
| 1742 (TARGET_THUMB1 \ | |
| 1743 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ | |
| 1744 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) | |
| 1745 | |
| 1746 /* Nonzero if X can be the base register in a reg+reg addressing mode. | |
| 1747 For Thumb, we can not use SP + reg, so reject SP. */ | |
| 1748 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ | |
| 1749 REGNO_MODE_OK_FOR_BASE_P (X, QImode) | |
| 1750 | |
| 1751 /* For ARM code, we don't care about the mode, but for Thumb, the index | |
| 1752 must be suitable for use in a QImode load. */ | |
| 1753 #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
| 1754 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ | |
| 1755 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) | |
| 1756 | |
| 1757 /* Maximum number of registers that can appear in a valid memory address. | |
| 1758 Shifts in addresses can't be by a register. */ | |
| 1759 #define MAX_REGS_PER_ADDRESS 2 | |
| 1760 | |
| 1761 /* Recognize any constant value that is a valid address. */ | |
| 1762 /* XXX We can address any constant, eventually... */ | |
| 1763 /* ??? Should the TARGET_ARM here also apply to thumb2? */ | |
| 1764 #define CONSTANT_ADDRESS_P(X) \ | |
| 1765 (GET_CODE (X) == SYMBOL_REF \ | |
| 1766 && (CONSTANT_POOL_ADDRESS_P (X) \ | |
| 1767 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) | |
| 1768 | |
| 1769 /* True if SYMBOL + OFFSET constants must refer to something within | |
| 1770 SYMBOL's section. */ | |
| 1771 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 | |
| 1772 | |
| 1773 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ | |
| 1774 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS | |
| 1775 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 | |
| 1776 #endif | |
| 1777 | |
| 1778 /* Nonzero if the constant value X is a legitimate general operand. | |
| 1779 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
| 1780 | |
| 1781 On the ARM, allow any integer (invalid ones are removed later by insn | |
| 1782 patterns), nice doubles and symbol_refs which refer to the function's | |
| 1783 constant pool XXX. | |
| 1784 | |
| 1785 When generating pic allow anything. */ | |
| 1786 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) | |
| 1787 | |
| 1788 #define THUMB_LEGITIMATE_CONSTANT_P(X) \ | |
| 1789 ( GET_CODE (X) == CONST_INT \ | |
| 1790 || GET_CODE (X) == CONST_DOUBLE \ | |
| 1791 || CONSTANT_ADDRESS_P (X) \ | |
| 1792 || flag_pic) | |
| 1793 | |
| 1794 #define LEGITIMATE_CONSTANT_P(X) \ | |
| 1795 (!arm_cannot_force_const_mem (X) \ | |
| 1796 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \ | |
| 1797 : THUMB_LEGITIMATE_CONSTANT_P (X))) | |
| 1798 | |
| 1799 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS | |
| 1800 #define SUBTARGET_NAME_ENCODING_LENGTHS | |
| 1801 #endif | |
| 1802 | |
| 1803 /* This is a C fragment for the inside of a switch statement. | |
| 1804 Each case label should return the number of characters to | |
| 1805 be stripped from the start of a function's name, if that | |
| 1806 name starts with the indicated character. */ | |
| 1807 #define ARM_NAME_ENCODING_LENGTHS \ | |
| 1808 case '*': return 1; \ | |
| 1809 SUBTARGET_NAME_ENCODING_LENGTHS | |
| 1810 | |
| 1811 /* This is how to output a reference to a user-level label named NAME. | |
| 1812 `assemble_name' uses this. */ | |
| 1813 #undef ASM_OUTPUT_LABELREF | |
| 1814 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ | |
| 1815 arm_asm_output_labelref (FILE, NAME) | |
| 1816 | |
| 1817 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ | |
| 1818 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ | |
| 1819 if (TARGET_THUMB2) \ | |
| 1820 thumb2_asm_output_opcode (STREAM); | |
| 1821 | |
| 1822 /* The EABI specifies that constructors should go in .init_array. | |
| 1823 Other targets use .ctors for compatibility. */ | |
| 1824 #ifndef ARM_EABI_CTORS_SECTION_OP | |
| 1825 #define ARM_EABI_CTORS_SECTION_OP \ | |
| 1826 "\t.section\t.init_array,\"aw\",%init_array" | |
| 1827 #endif | |
| 1828 #ifndef ARM_EABI_DTORS_SECTION_OP | |
| 1829 #define ARM_EABI_DTORS_SECTION_OP \ | |
| 1830 "\t.section\t.fini_array,\"aw\",%fini_array" | |
| 1831 #endif | |
| 1832 #define ARM_CTORS_SECTION_OP \ | |
| 1833 "\t.section\t.ctors,\"aw\",%progbits" | |
| 1834 #define ARM_DTORS_SECTION_OP \ | |
| 1835 "\t.section\t.dtors,\"aw\",%progbits" | |
| 1836 | |
| 1837 /* Define CTORS_SECTION_ASM_OP. */ | |
| 1838 #undef CTORS_SECTION_ASM_OP | |
| 1839 #undef DTORS_SECTION_ASM_OP | |
| 1840 #ifndef IN_LIBGCC2 | |
| 1841 # define CTORS_SECTION_ASM_OP \ | |
| 1842 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) | |
| 1843 # define DTORS_SECTION_ASM_OP \ | |
| 1844 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) | |
| 1845 #else /* !defined (IN_LIBGCC2) */ | |
| 1846 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, | |
| 1847 so we cannot use the definition above. */ | |
| 1848 # ifdef __ARM_EABI__ | |
| 1849 /* The .ctors section is not part of the EABI, so we do not define | |
| 1850 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff | |
| 1851 from trying to use it. We do define it when doing normal | |
| 1852 compilation, as .init_array can be used instead of .ctors. */ | |
| 1853 /* There is no need to emit begin or end markers when using | |
| 1854 init_array; the dynamic linker will compute the size of the | |
| 1855 array itself based on special symbols created by the static | |
| 1856 linker. However, we do need to arrange to set up | |
| 1857 exception-handling here. */ | |
| 1858 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) | |
| 1859 # define CTOR_LIST_END /* empty */ | |
| 1860 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) | |
| 1861 # define DTOR_LIST_END /* empty */ | |
| 1862 # else /* !defined (__ARM_EABI__) */ | |
| 1863 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP | |
| 1864 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP | |
| 1865 # endif /* !defined (__ARM_EABI__) */ | |
| 1866 #endif /* !defined (IN_LIBCC2) */ | |
| 1867 | |
| 1868 /* True if the operating system can merge entities with vague linkage | |
| 1869 (e.g., symbols in COMDAT group) during dynamic linking. */ | |
| 1870 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P | |
| 1871 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true | |
| 1872 #endif | |
| 1873 | |
| 1874 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) | |
| 1875 | |
| 1876 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
| 1877 and check its validity for a certain class. | |
| 1878 We have two alternate definitions for each of them. | |
| 1879 The usual definition accepts all pseudo regs; the other rejects | |
| 1880 them unless they have been allocated suitable hard regs. | |
| 1881 The symbol REG_OK_STRICT causes the latter definition to be used. | |
| 1882 Thumb-2 has the same restrictions as arm. */ | |
| 1883 #ifndef REG_OK_STRICT | |
| 1884 | |
| 1885 #define ARM_REG_OK_FOR_BASE_P(X) \ | |
| 1886 (REGNO (X) <= LAST_ARM_REGNUM \ | |
| 1887 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
| 1888 || REGNO (X) == FRAME_POINTER_REGNUM \ | |
| 1889 || REGNO (X) == ARG_POINTER_REGNUM) | |
| 1890 | |
| 1891 #define ARM_REG_OK_FOR_INDEX_P(X) \ | |
| 1892 ((REGNO (X) <= LAST_ARM_REGNUM \ | |
| 1893 && REGNO (X) != STACK_POINTER_REGNUM) \ | |
| 1894 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
| 1895 || REGNO (X) == FRAME_POINTER_REGNUM \ | |
| 1896 || REGNO (X) == ARG_POINTER_REGNUM) | |
| 1897 | |
| 1898 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
| 1899 (REGNO (X) <= LAST_LO_REGNUM \ | |
| 1900 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
| 1901 || (GET_MODE_SIZE (MODE) >= 4 \ | |
| 1902 && (REGNO (X) == STACK_POINTER_REGNUM \ | |
| 1903 || (X) == hard_frame_pointer_rtx \ | |
| 1904 || (X) == arg_pointer_rtx))) | |
| 1905 | |
| 1906 #define REG_STRICT_P 0 | |
| 1907 | |
| 1908 #else /* REG_OK_STRICT */ | |
| 1909 | |
| 1910 #define ARM_REG_OK_FOR_BASE_P(X) \ | |
| 1911 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) | |
| 1912 | |
| 1913 #define ARM_REG_OK_FOR_INDEX_P(X) \ | |
| 1914 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
| 1915 | |
| 1916 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
| 1917 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) | |
| 1918 | |
| 1919 #define REG_STRICT_P 1 | |
| 1920 | |
| 1921 #endif /* REG_OK_STRICT */ | |
| 1922 | |
| 1923 /* Now define some helpers in terms of the above. */ | |
| 1924 | |
| 1925 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
| 1926 (TARGET_THUMB1 \ | |
| 1927 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ | |
| 1928 : ARM_REG_OK_FOR_BASE_P (X)) | |
| 1929 | |
| 1930 /* For 16-bit Thumb, a valid index register is anything that can be used in | |
| 1931 a byte load instruction. */ | |
| 1932 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ | |
| 1933 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) | |
| 1934 | |
| 1935 /* Nonzero if X is a hard reg that can be used as an index | |
| 1936 or if it is a pseudo reg. On the Thumb, the stack pointer | |
| 1937 is not suitable. */ | |
| 1938 #define REG_OK_FOR_INDEX_P(X) \ | |
| 1939 (TARGET_THUMB1 \ | |
| 1940 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ | |
| 1941 : ARM_REG_OK_FOR_INDEX_P (X)) | |
| 1942 | |
| 1943 /* Nonzero if X can be the base register in a reg+reg addressing mode. | |
| 1944 For Thumb, we can not use SP + reg, so reject SP. */ | |
| 1945 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ | |
| 1946 REG_OK_FOR_INDEX_P (X) | |
| 1947 | |
| 1948 #define ARM_BASE_REGISTER_RTX_P(X) \ | |
| 1949 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) | |
| 1950 | |
| 1951 #define ARM_INDEX_REGISTER_RTX_P(X) \ | |
| 1952 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) | |
| 1953 | |
| 1954 /* Specify the machine mode that this machine uses | |
| 1955 for the index in the tablejump instruction. */ | |
| 1956 #define CASE_VECTOR_MODE Pmode | |
| 1957 | |
|
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1958 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ |
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1959 || (TARGET_THUMB1 \ |
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1960 && (optimize_size || flag_pic))) |
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1961 |
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1962 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ |
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1963 (TARGET_THUMB1 \ |
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1964 ? (min >= 0 && max < 512 \ |
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1965 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ |
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1966 : min >= -256 && max < 256 \ |
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1967 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ |
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1968 : min >= 0 && max < 8192 \ |
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1969 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ |
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1970 : min >= -4096 && max < 4096 \ |
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1971 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ |
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1972 : SImode) \ |
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1973 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \ |
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1974 : (max >= 0x200) ? HImode \ |
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1975 : QImode)) |
| 0 | 1976 |
| 1977 /* signed 'char' is most compatible, but RISC OS wants it unsigned. | |
| 1978 unsigned is probably best, but may break some code. */ | |
| 1979 #ifndef DEFAULT_SIGNED_CHAR | |
| 1980 #define DEFAULT_SIGNED_CHAR 0 | |
| 1981 #endif | |
| 1982 | |
| 1983 /* Max number of bytes we can move from memory to memory | |
| 1984 in one reasonably fast instruction. */ | |
| 1985 #define MOVE_MAX 4 | |
| 1986 | |
| 1987 #undef MOVE_RATIO | |
| 1988 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) | |
| 1989 | |
| 1990 /* Define if operations between registers always perform the operation | |
| 1991 on the full register even if a narrower mode is specified. */ | |
| 1992 #define WORD_REGISTER_OPERATIONS | |
| 1993 | |
| 1994 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
| 1995 will either zero-extend or sign-extend. The value of this macro should | |
| 1996 be the code that says which one of the two operations is implicitly | |
| 1997 done, UNKNOWN if none. */ | |
| 1998 #define LOAD_EXTEND_OP(MODE) \ | |
| 1999 (TARGET_THUMB ? ZERO_EXTEND : \ | |
| 2000 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ | |
| 2001 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) | |
| 2002 | |
| 2003 /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
| 2004 #define SLOW_BYTE_ACCESS 0 | |
| 2005 | |
| 2006 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 | |
| 2007 | |
| 2008 /* Immediate shift counts are truncated by the output routines (or was it | |
| 2009 the assembler?). Shift counts in a register are truncated by ARM. Note | |
| 2010 that the native compiler puts too large (> 32) immediate shift counts | |
| 2011 into a register and shifts by the register, letting the ARM decide what | |
| 2012 to do instead of doing that itself. */ | |
| 2013 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that | |
| 2014 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
| 2015 On the arm, Y in a register is used modulo 256 for the shift. Only for | |
| 2016 rotates is modulo 32 used. */ | |
| 2017 /* #define SHIFT_COUNT_TRUNCATED 1 */ | |
| 2018 | |
| 2019 /* All integers have the same format so truncation is easy. */ | |
| 2020 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
| 2021 | |
| 2022 /* Calling from registers is a massive pain. */ | |
| 2023 #define NO_FUNCTION_CSE 1 | |
| 2024 | |
| 2025 /* The machine modes of pointers and functions */ | |
| 2026 #define Pmode SImode | |
| 2027 #define FUNCTION_MODE Pmode | |
| 2028 | |
| 2029 #define ARM_FRAME_RTX(X) \ | |
| 2030 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ | |
| 2031 || (X) == arg_pointer_rtx) | |
| 2032 | |
| 2033 /* Moves to and from memory are quite expensive */ | |
| 2034 #define MEMORY_MOVE_COST(M, CLASS, IN) \ | |
| 2035 (TARGET_32BIT ? 10 : \ | |
| 2036 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ | |
| 2037 * (CLASS == LO_REGS ? 1 : 2))) | |
| 2038 | |
| 2039 /* Try to generate sequences that don't involve branches, we can then use | |
| 2040 conditional instructions */ | |
| 2041 #define BRANCH_COST(speed_p, predictable_p) \ | |
| 2042 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0)) | |
| 2043 | |
| 2044 /* Position Independent Code. */ | |
| 2045 /* We decide which register to use based on the compilation options and | |
| 2046 the assembler in use; this is more general than the APCS restriction of | |
| 2047 using sb (r9) all the time. */ | |
| 2048 extern unsigned arm_pic_register; | |
| 2049 | |
| 2050 /* The register number of the register used to address a table of static | |
| 2051 data addresses in memory. */ | |
| 2052 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register | |
| 2053 | |
| 2054 /* We can't directly access anything that contains a symbol, | |
| 2055 nor can we indirect via the constant pool. One exception is | |
| 2056 UNSPEC_TLS, which is always PIC. */ | |
| 2057 #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
| 2058 (!(symbol_mentioned_p (X) \ | |
| 2059 || label_mentioned_p (X) \ | |
| 2060 || (GET_CODE (X) == SYMBOL_REF \ | |
| 2061 && CONSTANT_POOL_ADDRESS_P (X) \ | |
| 2062 && (symbol_mentioned_p (get_pool_constant (X)) \ | |
| 2063 || label_mentioned_p (get_pool_constant (X))))) \ | |
| 2064 || tls_mentioned_p (X)) | |
| 2065 | |
| 2066 /* We need to know when we are making a constant pool; this determines | |
| 2067 whether data needs to be in the GOT or can be referenced via a GOT | |
| 2068 offset. */ | |
| 2069 extern int making_const_table; | |
| 2070 | |
| 2071 /* Handle pragmas for compatibility with Intel's compilers. */ | |
| 2072 /* Also abuse this to register additional C specific EABI attributes. */ | |
| 2073 #define REGISTER_TARGET_PRAGMAS() do { \ | |
| 2074 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ | |
| 2075 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ | |
| 2076 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ | |
| 2077 arm_lang_object_attributes_init(); \ | |
| 2078 } while (0) | |
| 2079 | |
| 2080 /* Condition code information. */ | |
| 2081 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
| 2082 return the mode to be used for the comparison. */ | |
| 2083 | |
| 2084 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) | |
| 2085 | |
| 2086 #define REVERSIBLE_CC_MODE(MODE) 1 | |
| 2087 | |
| 2088 #define REVERSE_CONDITION(CODE,MODE) \ | |
| 2089 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ | |
| 2090 ? reverse_condition_maybe_unordered (code) \ | |
| 2091 : reverse_condition (code)) | |
| 2092 | |
| 2093 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ | |
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2094 (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1)) |
| 0 | 2095 |
| 2096 /* The arm5 clz instruction returns 32. */ | |
| 2097 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) | |
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2098 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) |
| 0 | 2099 |
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2100 #define CC_STATUS_INIT \ |
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2101 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) |
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2102 |
| 0 | 2103 #undef ASM_APP_OFF |
| 2104 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \ | |
| 2105 TARGET_THUMB2 ? "\t.thumb\n" : "") | |
| 2106 | |
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2107 /* Output a push or a pop instruction (only used when profiling). |
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2108 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know |
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2109 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and |
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2110 that r7 isn't used by the function profiler, so we can use it as a |
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2111 scratch reg. WARNING: This isn't safe in the general case! It may be |
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2112 sensitive to future changes in final.c:profile_function. */ |
| 0 | 2113 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ |
| 2114 do \ | |
| 2115 { \ | |
| 2116 if (TARGET_ARM) \ | |
| 2117 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ | |
| 2118 STACK_POINTER_REGNUM, REGNO); \ | |
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2119 else if (TARGET_THUMB1 \ |
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2120 && (REGNO) == STATIC_CHAIN_REGNUM) \ |
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2121 { \ |
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2122 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ |
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2123 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ |
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2124 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ |
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2125 } \ |
| 0 | 2126 else \ |
| 2127 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ | |
| 2128 } while (0) | |
| 2129 | |
| 2130 | |
|
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2131 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ |
| 0 | 2132 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ |
| 2133 do \ | |
| 2134 { \ | |
| 2135 if (TARGET_ARM) \ | |
| 2136 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ | |
| 2137 STACK_POINTER_REGNUM, REGNO); \ | |
|
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2138 else if (TARGET_THUMB1 \ |
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2139 && (REGNO) == STATIC_CHAIN_REGNUM) \ |
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2140 { \ |
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2141 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ |
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2142 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ |
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2143 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ |
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2144 } \ |
| 0 | 2145 else \ |
| 2146 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ | |
| 2147 } while (0) | |
| 2148 | |
| 2149 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ | |
| 2150 #define ADDR_VEC_ALIGN(JUMPTABLE) 0 | |
| 2151 | |
| 2152 /* This is how to output a label which precedes a jumptable. Since | |
| 2153 Thumb instructions are 2 bytes, we may need explicit alignment here. */ | |
| 2154 #undef ASM_OUTPUT_CASE_LABEL | |
| 2155 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ | |
| 2156 do \ | |
| 2157 { \ | |
| 2158 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \ | |
| 2159 ASM_OUTPUT_ALIGN (FILE, 2); \ | |
| 2160 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \ | |
| 2161 } \ | |
| 2162 while (0) | |
| 2163 | |
| 2164 /* Make sure subsequent insns are aligned after a TBB. */ | |
| 2165 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ | |
| 2166 do \ | |
| 2167 { \ | |
| 2168 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \ | |
| 2169 ASM_OUTPUT_ALIGN (FILE, 1); \ | |
| 2170 } \ | |
| 2171 while (0) | |
| 2172 | |
| 2173 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ | |
| 2174 do \ | |
| 2175 { \ | |
| 2176 if (TARGET_THUMB) \ | |
| 2177 { \ | |
| 2178 if (is_called_in_ARM_mode (DECL) \ | |
| 2179 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \ | |
| 2180 && cfun->is_thunk)) \ | |
| 2181 fprintf (STREAM, "\t.code 32\n") ; \ | |
| 2182 else if (TARGET_THUMB1) \ | |
| 2183 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \ | |
| 2184 else \ | |
| 2185 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \ | |
| 2186 } \ | |
| 2187 if (TARGET_POKE_FUNCTION_NAME) \ | |
| 2188 arm_poke_function_name (STREAM, (const char *) NAME); \ | |
| 2189 } \ | |
| 2190 while (0) | |
| 2191 | |
| 2192 /* For aliases of functions we use .thumb_set instead. */ | |
| 2193 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ | |
| 2194 do \ | |
| 2195 { \ | |
| 2196 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ | |
| 2197 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ | |
| 2198 \ | |
| 2199 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ | |
| 2200 { \ | |
| 2201 fprintf (FILE, "\t.thumb_set "); \ | |
| 2202 assemble_name (FILE, LABEL1); \ | |
| 2203 fprintf (FILE, ","); \ | |
| 2204 assemble_name (FILE, LABEL2); \ | |
| 2205 fprintf (FILE, "\n"); \ | |
| 2206 } \ | |
| 2207 else \ | |
| 2208 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ | |
| 2209 } \ | |
| 2210 while (0) | |
| 2211 | |
| 2212 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN | |
| 2213 /* To support -falign-* switches we need to use .p2align so | |
| 2214 that alignment directives in code sections will be padded | |
| 2215 with no-op instructions, rather than zeroes. */ | |
| 2216 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ | |
| 2217 if ((LOG) != 0) \ | |
| 2218 { \ | |
| 2219 if ((MAX_SKIP) == 0) \ | |
| 2220 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ | |
| 2221 else \ | |
| 2222 fprintf ((FILE), "\t.p2align %d,,%d\n", \ | |
| 2223 (int) (LOG), (int) (MAX_SKIP)); \ | |
| 2224 } | |
| 2225 #endif | |
| 2226 | |
| 2227 /* Add two bytes to the length of conditionally executed Thumb-2 | |
| 2228 instructions for the IT instruction. */ | |
| 2229 #define ADJUST_INSN_LENGTH(insn, length) \ | |
| 2230 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ | |
| 2231 length += 2; | |
| 2232 | |
| 2233 /* Only perform branch elimination (by making instructions conditional) if | |
| 2234 we're optimizing. For Thumb-2 check if any IT instructions need | |
| 2235 outputting. */ | |
| 2236 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
| 2237 if (TARGET_ARM && optimize) \ | |
| 2238 arm_final_prescan_insn (INSN); \ | |
| 2239 else if (TARGET_THUMB2) \ | |
| 2240 thumb2_final_prescan_insn (INSN); \ | |
| 2241 else if (TARGET_THUMB1) \ | |
| 2242 thumb1_final_prescan_insn (INSN) | |
| 2243 | |
| 2244 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ | |
| 2245 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ | |
| 2246 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ | |
| 2247 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ | |
| 2248 ? ((~ (unsigned HOST_WIDE_INT) 0) \ | |
| 2249 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ | |
| 2250 : 0)))) | |
| 2251 | |
| 2252 /* A C expression whose value is RTL representing the value of the return | |
| 2253 address for the frame COUNT steps up from the current frame. */ | |
| 2254 | |
| 2255 #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
| 2256 arm_return_addr (COUNT, FRAME) | |
| 2257 | |
| 2258 /* Mask of the bits in the PC that contain the real return address | |
| 2259 when running in 26-bit mode. */ | |
| 2260 #define RETURN_ADDR_MASK26 (0x03fffffc) | |
| 2261 | |
| 2262 /* Pick up the return address upon entry to a procedure. Used for | |
| 2263 dwarf2 unwind information. This also enables the table driven | |
| 2264 mechanism. */ | |
| 2265 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) | |
| 2266 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) | |
| 2267 | |
| 2268 /* Used to mask out junk bits from the return address, such as | |
| 2269 processor state, interrupt status, condition codes and the like. */ | |
| 2270 #define MASK_RETURN_ADDR \ | |
| 2271 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ | |
| 2272 in 26 bit mode, the condition codes must be masked out of the \ | |
| 2273 return address. This does not apply to ARM6 and later processors \ | |
| 2274 when running in 32 bit mode. */ \ | |
| 2275 ((arm_arch4 || TARGET_THUMB) \ | |
| 2276 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ | |
| 2277 : arm_gen_return_addr_mask ()) | |
| 2278 | |
| 2279 | |
| 2280 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have | |
| 2281 symbolic names defined here (which would require too much duplication). | |
| 2282 FIXME? */ | |
| 2283 enum arm_builtins | |
| 2284 { | |
| 2285 ARM_BUILTIN_GETWCX, | |
| 2286 ARM_BUILTIN_SETWCX, | |
| 2287 | |
| 2288 ARM_BUILTIN_WZERO, | |
| 2289 | |
| 2290 ARM_BUILTIN_WAVG2BR, | |
| 2291 ARM_BUILTIN_WAVG2HR, | |
| 2292 ARM_BUILTIN_WAVG2B, | |
| 2293 ARM_BUILTIN_WAVG2H, | |
| 2294 | |
| 2295 ARM_BUILTIN_WACCB, | |
| 2296 ARM_BUILTIN_WACCH, | |
| 2297 ARM_BUILTIN_WACCW, | |
| 2298 | |
| 2299 ARM_BUILTIN_WMACS, | |
| 2300 ARM_BUILTIN_WMACSZ, | |
| 2301 ARM_BUILTIN_WMACU, | |
| 2302 ARM_BUILTIN_WMACUZ, | |
| 2303 | |
| 2304 ARM_BUILTIN_WSADB, | |
| 2305 ARM_BUILTIN_WSADBZ, | |
| 2306 ARM_BUILTIN_WSADH, | |
| 2307 ARM_BUILTIN_WSADHZ, | |
| 2308 | |
| 2309 ARM_BUILTIN_WALIGN, | |
| 2310 | |
| 2311 ARM_BUILTIN_TMIA, | |
| 2312 ARM_BUILTIN_TMIAPH, | |
| 2313 ARM_BUILTIN_TMIABB, | |
| 2314 ARM_BUILTIN_TMIABT, | |
| 2315 ARM_BUILTIN_TMIATB, | |
| 2316 ARM_BUILTIN_TMIATT, | |
| 2317 | |
| 2318 ARM_BUILTIN_TMOVMSKB, | |
| 2319 ARM_BUILTIN_TMOVMSKH, | |
| 2320 ARM_BUILTIN_TMOVMSKW, | |
| 2321 | |
| 2322 ARM_BUILTIN_TBCSTB, | |
| 2323 ARM_BUILTIN_TBCSTH, | |
| 2324 ARM_BUILTIN_TBCSTW, | |
| 2325 | |
| 2326 ARM_BUILTIN_WMADDS, | |
| 2327 ARM_BUILTIN_WMADDU, | |
| 2328 | |
| 2329 ARM_BUILTIN_WPACKHSS, | |
| 2330 ARM_BUILTIN_WPACKWSS, | |
| 2331 ARM_BUILTIN_WPACKDSS, | |
| 2332 ARM_BUILTIN_WPACKHUS, | |
| 2333 ARM_BUILTIN_WPACKWUS, | |
| 2334 ARM_BUILTIN_WPACKDUS, | |
| 2335 | |
| 2336 ARM_BUILTIN_WADDB, | |
| 2337 ARM_BUILTIN_WADDH, | |
| 2338 ARM_BUILTIN_WADDW, | |
| 2339 ARM_BUILTIN_WADDSSB, | |
| 2340 ARM_BUILTIN_WADDSSH, | |
| 2341 ARM_BUILTIN_WADDSSW, | |
| 2342 ARM_BUILTIN_WADDUSB, | |
| 2343 ARM_BUILTIN_WADDUSH, | |
| 2344 ARM_BUILTIN_WADDUSW, | |
| 2345 ARM_BUILTIN_WSUBB, | |
| 2346 ARM_BUILTIN_WSUBH, | |
| 2347 ARM_BUILTIN_WSUBW, | |
| 2348 ARM_BUILTIN_WSUBSSB, | |
| 2349 ARM_BUILTIN_WSUBSSH, | |
| 2350 ARM_BUILTIN_WSUBSSW, | |
| 2351 ARM_BUILTIN_WSUBUSB, | |
| 2352 ARM_BUILTIN_WSUBUSH, | |
| 2353 ARM_BUILTIN_WSUBUSW, | |
| 2354 | |
| 2355 ARM_BUILTIN_WAND, | |
| 2356 ARM_BUILTIN_WANDN, | |
| 2357 ARM_BUILTIN_WOR, | |
| 2358 ARM_BUILTIN_WXOR, | |
| 2359 | |
| 2360 ARM_BUILTIN_WCMPEQB, | |
| 2361 ARM_BUILTIN_WCMPEQH, | |
| 2362 ARM_BUILTIN_WCMPEQW, | |
| 2363 ARM_BUILTIN_WCMPGTUB, | |
| 2364 ARM_BUILTIN_WCMPGTUH, | |
| 2365 ARM_BUILTIN_WCMPGTUW, | |
| 2366 ARM_BUILTIN_WCMPGTSB, | |
| 2367 ARM_BUILTIN_WCMPGTSH, | |
| 2368 ARM_BUILTIN_WCMPGTSW, | |
| 2369 | |
| 2370 ARM_BUILTIN_TEXTRMSB, | |
| 2371 ARM_BUILTIN_TEXTRMSH, | |
| 2372 ARM_BUILTIN_TEXTRMSW, | |
| 2373 ARM_BUILTIN_TEXTRMUB, | |
| 2374 ARM_BUILTIN_TEXTRMUH, | |
| 2375 ARM_BUILTIN_TEXTRMUW, | |
| 2376 ARM_BUILTIN_TINSRB, | |
| 2377 ARM_BUILTIN_TINSRH, | |
| 2378 ARM_BUILTIN_TINSRW, | |
| 2379 | |
| 2380 ARM_BUILTIN_WMAXSW, | |
| 2381 ARM_BUILTIN_WMAXSH, | |
| 2382 ARM_BUILTIN_WMAXSB, | |
| 2383 ARM_BUILTIN_WMAXUW, | |
| 2384 ARM_BUILTIN_WMAXUH, | |
| 2385 ARM_BUILTIN_WMAXUB, | |
| 2386 ARM_BUILTIN_WMINSW, | |
| 2387 ARM_BUILTIN_WMINSH, | |
| 2388 ARM_BUILTIN_WMINSB, | |
| 2389 ARM_BUILTIN_WMINUW, | |
| 2390 ARM_BUILTIN_WMINUH, | |
| 2391 ARM_BUILTIN_WMINUB, | |
| 2392 | |
| 2393 ARM_BUILTIN_WMULUM, | |
| 2394 ARM_BUILTIN_WMULSM, | |
| 2395 ARM_BUILTIN_WMULUL, | |
| 2396 | |
| 2397 ARM_BUILTIN_PSADBH, | |
| 2398 ARM_BUILTIN_WSHUFH, | |
| 2399 | |
| 2400 ARM_BUILTIN_WSLLH, | |
| 2401 ARM_BUILTIN_WSLLW, | |
| 2402 ARM_BUILTIN_WSLLD, | |
| 2403 ARM_BUILTIN_WSRAH, | |
| 2404 ARM_BUILTIN_WSRAW, | |
| 2405 ARM_BUILTIN_WSRAD, | |
| 2406 ARM_BUILTIN_WSRLH, | |
| 2407 ARM_BUILTIN_WSRLW, | |
| 2408 ARM_BUILTIN_WSRLD, | |
| 2409 ARM_BUILTIN_WRORH, | |
| 2410 ARM_BUILTIN_WRORW, | |
| 2411 ARM_BUILTIN_WRORD, | |
| 2412 ARM_BUILTIN_WSLLHI, | |
| 2413 ARM_BUILTIN_WSLLWI, | |
| 2414 ARM_BUILTIN_WSLLDI, | |
| 2415 ARM_BUILTIN_WSRAHI, | |
| 2416 ARM_BUILTIN_WSRAWI, | |
| 2417 ARM_BUILTIN_WSRADI, | |
| 2418 ARM_BUILTIN_WSRLHI, | |
| 2419 ARM_BUILTIN_WSRLWI, | |
| 2420 ARM_BUILTIN_WSRLDI, | |
| 2421 ARM_BUILTIN_WRORHI, | |
| 2422 ARM_BUILTIN_WRORWI, | |
| 2423 ARM_BUILTIN_WRORDI, | |
| 2424 | |
| 2425 ARM_BUILTIN_WUNPCKIHB, | |
| 2426 ARM_BUILTIN_WUNPCKIHH, | |
| 2427 ARM_BUILTIN_WUNPCKIHW, | |
| 2428 ARM_BUILTIN_WUNPCKILB, | |
| 2429 ARM_BUILTIN_WUNPCKILH, | |
| 2430 ARM_BUILTIN_WUNPCKILW, | |
| 2431 | |
| 2432 ARM_BUILTIN_WUNPCKEHSB, | |
| 2433 ARM_BUILTIN_WUNPCKEHSH, | |
| 2434 ARM_BUILTIN_WUNPCKEHSW, | |
| 2435 ARM_BUILTIN_WUNPCKEHUB, | |
| 2436 ARM_BUILTIN_WUNPCKEHUH, | |
| 2437 ARM_BUILTIN_WUNPCKEHUW, | |
| 2438 ARM_BUILTIN_WUNPCKELSB, | |
| 2439 ARM_BUILTIN_WUNPCKELSH, | |
| 2440 ARM_BUILTIN_WUNPCKELSW, | |
| 2441 ARM_BUILTIN_WUNPCKELUB, | |
| 2442 ARM_BUILTIN_WUNPCKELUH, | |
| 2443 ARM_BUILTIN_WUNPCKELUW, | |
| 2444 | |
| 2445 ARM_BUILTIN_THREAD_POINTER, | |
| 2446 | |
| 2447 ARM_BUILTIN_NEON_BASE, | |
| 2448 | |
| 2449 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */ | |
| 2450 }; | |
| 2451 | |
| 2452 /* Do not emit .note.GNU-stack by default. */ | |
| 2453 #ifndef NEED_INDICATE_EXEC_STACK | |
| 2454 #define NEED_INDICATE_EXEC_STACK 0 | |
| 2455 #endif | |
| 2456 | |
|
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2457 /* The maximum number of parallel loads or stores we support in an ldm/stm |
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2458 instruction. */ |
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2459 #define MAX_LDM_STM_OPS 4 |
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2460 |
| 0 | 2461 #endif /* ! GCC_ARM_H */ |