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1 ;; ARM 1136J[F]-S Pipeline Description
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2 ;; Copyright (C) 2003, 2007 Free Software Foundation, Inc.
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3 ;; Written by CodeSourcery, LLC.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but
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13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 ;; General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>. */
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20
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21 ;; These descriptions are based on the information contained in the
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22 ;; ARM1136JF-S Technical Reference Manual, Copyright (c) 2003 ARM
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23 ;; Limited.
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24 ;;
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25
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26 ;; This automaton provides a pipeline description for the ARM
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27 ;; 1136J-S and 1136JF-S cores.
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28 ;;
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29 ;; The model given here assumes that the condition for all conditional
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30 ;; instructions is "true", i.e., that all of the instructions are
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31 ;; actually executed.
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32
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33 (define_automaton "arm1136jfs")
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34
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35 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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36 ;; Pipelines
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37 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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38
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39 ;; There are three distinct pipelines (page 1-26 and following):
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40 ;;
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41 ;; - A 4-stage decode pipeline, shared by all three. It has fetch (1),
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42 ;; fetch (2), decode, and issue stages. Since this is always involved,
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43 ;; we do not model it in the scheduler.
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44 ;;
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45 ;; - A 4-stage ALU pipeline. It has shifter, ALU (main integer operations),
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46 ;; and saturation stages. The fourth stage is writeback; see below.
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47 ;;
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48 ;; - A 4-stage multiply-accumulate pipeline. It has three stages, called
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49 ;; MAC1 through MAC3, and a fourth writeback stage.
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50 ;;
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51 ;; The 4th-stage writeback is shared between the ALU and MAC pipelines,
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52 ;; which operate in lockstep. Results from either pipeline will be
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53 ;; moved into the writeback stage. Because the two pipelines operate
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54 ;; in lockstep, we schedule them as a single "execute" pipeline.
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55 ;;
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56 ;; - A 4-stage LSU pipeline. It has address generation, data cache (1),
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57 ;; data cache (2), and writeback stages. (Note that this pipeline,
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58 ;; including the writeback stage, is independent from the ALU & LSU pipes.)
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59
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60 (define_cpu_unit "e_1,e_2,e_3,e_wb" "arm1136jfs") ; ALU and MAC
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61 ; e_1 = Sh/Mac1, e_2 = ALU/Mac2, e_3 = SAT/Mac3
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62 (define_cpu_unit "l_a,l_dc1,l_dc2,l_wb" "arm1136jfs") ; Load/Store
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63
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64 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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65 ;; ALU Instructions
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66 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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67
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68 ;; ALU instructions require eight cycles to execute, and use the ALU
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69 ;; pipeline in each of the eight stages. The results are available
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70 ;; after the alu stage has finished.
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71 ;;
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72 ;; If the destination register is the PC, the pipelines are stalled
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73 ;; for several cycles. That case is not modelled here.
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74
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75 ;; ALU operations with no shifted operand
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76 (define_insn_reservation "11_alu_op" 2
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77 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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78 (eq_attr "type" "alu"))
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79 "e_1,e_2,e_3,e_wb")
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80
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81 ;; ALU operations with a shift-by-constant operand
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82 (define_insn_reservation "11_alu_shift_op" 2
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83 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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84 (eq_attr "type" "alu_shift"))
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85 "e_1,e_2,e_3,e_wb")
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86
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87 ;; ALU operations with a shift-by-register operand
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88 ;; These really stall in the decoder, in order to read
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89 ;; the shift value in a second cycle. Pretend we take two cycles in
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90 ;; the shift stage.
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91 (define_insn_reservation "11_alu_shift_reg_op" 3
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92 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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93 (eq_attr "type" "alu_shift_reg"))
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94 "e_1*2,e_2,e_3,e_wb")
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95
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96 ;; alu_ops can start sooner, if there is no shifter dependency
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97 (define_bypass 1 "11_alu_op,11_alu_shift_op"
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98 "11_alu_op")
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99 (define_bypass 1 "11_alu_op,11_alu_shift_op"
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100 "11_alu_shift_op"
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101 "arm_no_early_alu_shift_value_dep")
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102 (define_bypass 1 "11_alu_op,11_alu_shift_op"
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103 "11_alu_shift_reg_op"
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104 "arm_no_early_alu_shift_dep")
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105 (define_bypass 2 "11_alu_shift_reg_op"
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106 "11_alu_op")
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107 (define_bypass 2 "11_alu_shift_reg_op"
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108 "11_alu_shift_op"
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109 "arm_no_early_alu_shift_value_dep")
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110 (define_bypass 2 "11_alu_shift_reg_op"
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111 "11_alu_shift_reg_op"
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112 "arm_no_early_alu_shift_dep")
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113
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114 (define_bypass 1 "11_alu_op,11_alu_shift_op"
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115 "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
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116 "arm_no_early_mul_dep")
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117 (define_bypass 2 "11_alu_shift_reg_op"
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118 "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
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119 "arm_no_early_mul_dep")
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120
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121 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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122 ;; Multiplication Instructions
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123 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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124
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125 ;; Multiplication instructions loop in the first two execute stages until
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126 ;; the instruction has been passed through the multiplier array enough
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127 ;; times.
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128
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129 ;; Multiply and multiply-accumulate results are available after four stages.
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130 (define_insn_reservation "11_mult1" 4
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131 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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132 (eq_attr "insn" "mul,mla"))
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133 "e_1*2,e_2,e_3,e_wb")
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134
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135 ;; The *S variants set the condition flags, which requires three more cycles.
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136 (define_insn_reservation "11_mult2" 4
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137 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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138 (eq_attr "insn" "muls,mlas"))
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139 "e_1*2,e_2,e_3,e_wb")
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140
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141 (define_bypass 3 "11_mult1,11_mult2"
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142 "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
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143 "arm_no_early_mul_dep")
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144 (define_bypass 3 "11_mult1,11_mult2"
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145 "11_alu_op")
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146 (define_bypass 3 "11_mult1,11_mult2"
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147 "11_alu_shift_op"
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148 "arm_no_early_alu_shift_value_dep")
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149 (define_bypass 3 "11_mult1,11_mult2"
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150 "11_alu_shift_reg_op"
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151 "arm_no_early_alu_shift_dep")
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152 (define_bypass 3 "11_mult1,11_mult2"
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153 "11_store1"
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154 "arm_no_early_store_addr_dep")
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155
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156 ;; Signed and unsigned multiply long results are available across two cycles;
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157 ;; the less significant word is available one cycle before the more significant
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158 ;; word. Here we conservatively wait until both are available, which is
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159 ;; after three iterations and the memory cycle. The same is also true of
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160 ;; the two multiply-accumulate instructions.
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161 (define_insn_reservation "11_mult3" 5
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162 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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163 (eq_attr "insn" "smull,umull,smlal,umlal"))
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164 "e_1*3,e_2,e_3,e_wb*2")
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165
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166 ;; The *S variants set the condition flags, which requires three more cycles.
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167 (define_insn_reservation "11_mult4" 5
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168 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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169 (eq_attr "insn" "smulls,umulls,smlals,umlals"))
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170 "e_1*3,e_2,e_3,e_wb*2")
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171
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172 (define_bypass 4 "11_mult3,11_mult4"
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173 "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
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174 "arm_no_early_mul_dep")
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175 (define_bypass 4 "11_mult3,11_mult4"
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176 "11_alu_op")
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177 (define_bypass 4 "11_mult3,11_mult4"
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178 "11_alu_shift_op"
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179 "arm_no_early_alu_shift_value_dep")
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180 (define_bypass 4 "11_mult3,11_mult4"
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181 "11_alu_shift_reg_op"
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182 "arm_no_early_alu_shift_dep")
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183 (define_bypass 4 "11_mult3,11_mult4"
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184 "11_store1"
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185 "arm_no_early_store_addr_dep")
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186
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187 ;; Various 16x16->32 multiplies and multiply-accumulates, using combinations
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188 ;; of high and low halves of the argument registers. They take a single
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189 ;; pass through the pipeline and make the result available after three
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190 ;; cycles.
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191 (define_insn_reservation "11_mult5" 3
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192 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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193 (eq_attr "insn" "smulxy,smlaxy,smulwy,smlawy,smuad,smuadx,smlad,smladx,smusd,smusdx,smlsd,smlsdx"))
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194 "e_1,e_2,e_3,e_wb")
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195
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196 (define_bypass 2 "11_mult5"
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197 "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
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198 "arm_no_early_mul_dep")
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199 (define_bypass 2 "11_mult5"
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200 "11_alu_op")
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201 (define_bypass 2 "11_mult5"
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202 "11_alu_shift_op"
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203 "arm_no_early_alu_shift_value_dep")
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204 (define_bypass 2 "11_mult5"
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205 "11_alu_shift_reg_op"
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206 "arm_no_early_alu_shift_dep")
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207 (define_bypass 2 "11_mult5"
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208 "11_store1"
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209 "arm_no_early_store_addr_dep")
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210
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211 ;; The same idea, then the 32-bit result is added to a 64-bit quantity.
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212 (define_insn_reservation "11_mult6" 4
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213 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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214 (eq_attr "insn" "smlalxy"))
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215 "e_1*2,e_2,e_3,e_wb*2")
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216
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217 ;; Signed 32x32 multiply, then the most significant 32 bits are extracted
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218 ;; and are available after the memory stage.
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219 (define_insn_reservation "11_mult7" 4
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220 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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221 (eq_attr "insn" "smmul,smmulr"))
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222 "e_1*2,e_2,e_3,e_wb")
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223
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224 (define_bypass 3 "11_mult6,11_mult7"
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225 "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
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226 "arm_no_early_mul_dep")
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227 (define_bypass 3 "11_mult6,11_mult7"
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228 "11_alu_op")
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229 (define_bypass 3 "11_mult6,11_mult7"
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230 "11_alu_shift_op"
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231 "arm_no_early_alu_shift_value_dep")
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232 (define_bypass 3 "11_mult6,11_mult7"
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233 "11_alu_shift_reg_op"
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234 "arm_no_early_alu_shift_dep")
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235 (define_bypass 3 "11_mult6,11_mult7"
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236 "11_store1"
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237 "arm_no_early_store_addr_dep")
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238
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239 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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240 ;; Branch Instructions
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241 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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242
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243 ;; These vary greatly depending on their arguments and the results of
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244 ;; stat prediction. Cycle count ranges from zero (unconditional branch,
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245 ;; folded dynamic prediction) to seven (incorrect predictions, etc). We
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246 ;; assume an optimal case for now, because the cost of a cache miss
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247 ;; overwhelms the cost of everything else anyhow.
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248
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249 (define_insn_reservation "11_branches" 0
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250 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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251 (eq_attr "type" "branch"))
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252 "nothing")
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253
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254 ;; Call latencies are not predictable. A semi-arbitrary very large
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255 ;; number is used as "positive infinity" so that everything should be
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256 ;; finished by the time of return.
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257 (define_insn_reservation "11_call" 32
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258 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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259 (eq_attr "type" "call"))
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260 "nothing")
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261
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262 ;; Branches are predicted. A correctly predicted branch will be no
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263 ;; cost, but we're conservative here, and use the timings a
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264 ;; late-register would give us.
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265 (define_bypass 1 "11_alu_op,11_alu_shift_op"
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266 "11_branches")
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267 (define_bypass 2 "11_alu_shift_reg_op"
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268 "11_branches")
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269 (define_bypass 2 "11_load1,11_load2"
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270 "11_branches")
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271 (define_bypass 3 "11_load34"
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272 "11_branches")
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273
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274 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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275 ;; Load/Store Instructions
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276 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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277
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278 ;; The models for load/store instructions do not accurately describe
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279 ;; the difference between operations with a base register writeback.
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280 ;; These models assume that all memory references hit in dcache. Also,
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281 ;; if the PC is one of the registers involved, there are additional stalls
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282 ;; not modelled here. Addressing modes are also not modelled.
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283
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284 (define_insn_reservation "11_load1" 3
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285 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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286 (eq_attr "type" "load1"))
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287 "l_a+e_1,l_dc1,l_dc2,l_wb")
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288
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289 ;; Load byte results are not available until the writeback stage, where
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290 ;; the correct byte is extracted.
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291
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292 (define_insn_reservation "11_loadb" 4
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293 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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294 (eq_attr "type" "load_byte"))
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295 "l_a+e_1,l_dc1,l_dc2,l_wb")
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296
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297 (define_insn_reservation "11_store1" 0
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298 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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299 (eq_attr "type" "store1"))
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300 "l_a+e_1,l_dc1,l_dc2,l_wb")
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301
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302 ;; Load/store double words into adjacent registers. The timing and
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303 ;; latencies are different depending on whether the address is 64-bit
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304 ;; aligned. This model assumes that it is.
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305 (define_insn_reservation "11_load2" 3
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306 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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307 (eq_attr "type" "load2"))
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308 "l_a+e_1,l_dc1,l_dc2,l_wb")
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309
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310 (define_insn_reservation "11_store2" 0
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311 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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312 (eq_attr "type" "store2"))
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313 "l_a+e_1,l_dc1,l_dc2,l_wb")
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314
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315 ;; Load/store multiple registers. Two registers are stored per cycle.
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316 ;; Actual timing depends on how many registers are affected, so we
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317 ;; optimistically schedule a low latency.
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318 (define_insn_reservation "11_load34" 4
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319 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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320 (eq_attr "type" "load3,load4"))
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321 "l_a+e_1,l_dc1*2,l_dc2,l_wb")
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322
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323 (define_insn_reservation "11_store34" 0
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324 (and (eq_attr "tune" "arm1136js,arm1136jfs")
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325 (eq_attr "type" "store3,store4"))
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326 "l_a+e_1,l_dc1*2,l_dc2,l_wb")
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327
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328 ;; A store can start immediately after an alu op, if that alu op does
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329 ;; not provide part of the address to access.
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330 (define_bypass 1 "11_alu_op,11_alu_shift_op"
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331 "11_store1"
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332 "arm_no_early_store_addr_dep")
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333 (define_bypass 2 "11_alu_shift_reg_op"
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334 "11_store1"
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335 "arm_no_early_store_addr_dep")
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336
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337 ;; An alu op can start sooner after a load, if that alu op does not
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338 ;; have an early register dependency on the load
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339 (define_bypass 2 "11_load1"
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340 "11_alu_op")
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341 (define_bypass 2 "11_load1"
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342 "11_alu_shift_op"
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343 "arm_no_early_alu_shift_value_dep")
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344 (define_bypass 2 "11_load1"
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345 "11_alu_shift_reg_op"
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346 "arm_no_early_alu_shift_dep")
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347
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348 (define_bypass 3 "11_loadb"
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349 "11_alu_op")
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350 (define_bypass 3 "11_loadb"
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351 "11_alu_shift_op"
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352 "arm_no_early_alu_shift_value_dep")
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353 (define_bypass 3 "11_loadb"
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354 "11_alu_shift_reg_op"
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355 "arm_no_early_alu_shift_dep")
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356
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357 ;; A mul op can start sooner after a load, if that mul op does not
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358 ;; have an early multiply dependency
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359 (define_bypass 2 "11_load1"
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360 "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
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361 "arm_no_early_mul_dep")
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362 (define_bypass 3 "11_load34"
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363 "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
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364 "arm_no_early_mul_dep")
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365 (define_bypass 3 "11_loadb"
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366 "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
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367 "arm_no_early_mul_dep")
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368
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369 ;; A store can start sooner after a load, if that load does not
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370 ;; produce part of the address to access
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371 (define_bypass 2 "11_load1"
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372 "11_store1"
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373 "arm_no_early_store_addr_dep")
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374 (define_bypass 3 "11_loadb"
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375 "11_store1"
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376 "arm_no_early_store_addr_dep")
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