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annotate gcc/config/arm/cortex-a9.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents 77e2b8dfacca
children 04ced10e8804
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55
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1 ;; ARM Cortex-A9 pipeline description
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2 ;; Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
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3 ;; Originally written by CodeSourcery for VFP.
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4 ;;
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5 ;; Rewritten by Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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6 ;; Integer Pipeline description contributed by ARM Ltd.
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7 ;; VFP Pipeline description rewritten and contributed by ARM Ltd.
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8
0
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9 ;; This file is part of GCC.
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10 ;;
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11 ;; GCC is free software; you can redistribute it and/or modify it
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12 ;; under the terms of the GNU General Public License as published by
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13 ;; the Free Software Foundation; either version 3, or (at your option)
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14 ;; any later version.
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15 ;;
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16 ;; GCC is distributed in the hope that it will be useful, but
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17 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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19 ;; General Public License for more details.
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20 ;;
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21 ;; You should have received a copy of the GNU General Public License
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22 ;; along with GCC; see the file COPYING3. If not see
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23 ;; <http://www.gnu.org/licenses/>.
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24
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25 (define_automaton "cortex_a9")
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27 ;; The Cortex-A9 core is modelled as a dual issue pipeline that has
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28 ;; the following components.
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29 ;; 1. 1 Load Store Pipeline.
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30 ;; 2. P0 / main pipeline for data processing instructions.
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31 ;; 3. P1 / Dual pipeline for Data processing instructions.
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32 ;; 4. MAC pipeline for multiply as well as multiply
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33 ;; and accumulate instructions.
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34 ;; 5. 1 VFP and an optional Neon unit.
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35 ;; The Load/Store, VFP and Neon issue pipeline are multiplexed.
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36 ;; The P0 / main pipeline and M1 stage of the MAC pipeline are
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37 ;; multiplexed.
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38 ;; The P1 / dual pipeline and M2 stage of the MAC pipeline are
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39 ;; multiplexed.
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40 ;; There are only 4 integer register read ports and hence at any point of
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41 ;; time we can't have issue down the E1 and the E2 ports unless
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42 ;; of course there are bypass paths that get exercised.
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43 ;; Both P0 and P1 have 2 stages E1 and E2.
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44 ;; Data processing instructions issue to E1 or E2 depending on
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45 ;; whether they have an early shift or not.
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47 (define_cpu_unit "ca9_issue_vfp_neon, cortex_a9_ls" "cortex_a9")
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48 (define_cpu_unit "cortex_a9_p0_e1, cortex_a9_p0_e2" "cortex_a9")
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49 (define_cpu_unit "cortex_a9_p1_e1, cortex_a9_p1_e2" "cortex_a9")
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50 (define_cpu_unit "cortex_a9_p0_wb, cortex_a9_p1_wb" "cortex_a9")
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51 (define_cpu_unit "cortex_a9_mac_m1, cortex_a9_mac_m2" "cortex_a9")
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52 (define_cpu_unit "cortex_a9_branch, cortex_a9_issue_branch" "cortex_a9")
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53
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54 (define_reservation "cortex_a9_p0_default" "cortex_a9_p0_e2, cortex_a9_p0_wb")
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55 (define_reservation "cortex_a9_p1_default" "cortex_a9_p1_e2, cortex_a9_p1_wb")
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56 (define_reservation "cortex_a9_p0_shift" "cortex_a9_p0_e1, cortex_a9_p0_default")
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57 (define_reservation "cortex_a9_p1_shift" "cortex_a9_p1_e1, cortex_a9_p1_default")
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58
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59 (define_reservation "cortex_a9_multcycle1"
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60 "cortex_a9_p0_e2 + cortex_a9_mac_m1 + cortex_a9_mac_m2 + \
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61 cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
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62
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63 (define_reservation "cortex_a9_mult16"
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64 "cortex_a9_mac_m1, cortex_a9_mac_m2, cortex_a9_p0_wb")
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65 (define_reservation "cortex_a9_mac16"
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66 "cortex_a9_multcycle1, cortex_a9_mac_m2, cortex_a9_p0_wb")
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67 (define_reservation "cortex_a9_mult"
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68 "cortex_a9_mac_m1*2, cortex_a9_mac_m2, cortex_a9_p0_wb")
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69 (define_reservation "cortex_a9_mac"
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70 "cortex_a9_multcycle1*2 ,cortex_a9_mac_m2, cortex_a9_p0_wb")
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71
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72
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73 ;; Issue at the same time along the load store pipeline and
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74 ;; the VFP / Neon pipeline is not possible.
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75 (exclusion_set "cortex_a9_ls" "ca9_issue_vfp_neon")
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76
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77 ;; Default data processing instruction without any shift
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78 ;; The only exception to this is the mov instruction
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79 ;; which can go down E2 without any problem.
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80 (define_insn_reservation "cortex_a9_dp" 2
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81 (and (eq_attr "tune" "cortexa9")
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82 (ior (and (eq_attr "type" "alu")
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83 (eq_attr "neon_type" "none"))
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84 (and (and (eq_attr "type" "alu_shift_reg, alu_shift")
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85 (eq_attr "insn" "mov"))
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86 (eq_attr "neon_type" "none"))))
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87 "cortex_a9_p0_default|cortex_a9_p1_default")
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88
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89 ;; An instruction using the shifter will go down E1.
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90 (define_insn_reservation "cortex_a9_dp_shift" 3
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91 (and (eq_attr "tune" "cortexa9")
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92 (and (eq_attr "type" "alu_shift_reg, alu_shift")
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93 (not (eq_attr "insn" "mov"))))
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94 "cortex_a9_p0_shift | cortex_a9_p1_shift")
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95
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96 ;; Loads have a latency of 4 cycles.
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97 ;; We don't model autoincrement instructions. These
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98 ;; instructions use the load store pipeline and 1 of
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99 ;; the E2 units to write back the result of the increment.
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100
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101 (define_insn_reservation "cortex_a9_load1_2" 4
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102 (and (eq_attr "tune" "cortexa9")
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103 (eq_attr "type" "load1, load2, load_byte, f_loads, f_loadd"))
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104 "cortex_a9_ls")
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105
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106 ;; Loads multiples and store multiples can't be issued for 2 cycles in a
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107 ;; row. The description below assumes that addresses are 64 bit aligned.
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108 ;; If not, there is an extra cycle latency which is not modelled.
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109
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110 (define_insn_reservation "cortex_a9_load3_4" 5
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
111 (and (eq_attr "tune" "cortexa9")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
112 (eq_attr "type" "load3, load4"))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
113 "cortex_a9_ls, cortex_a9_ls")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
114
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
115 (define_insn_reservation "cortex_a9_store1_2" 0
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
116 (and (eq_attr "tune" "cortexa9")
67
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
117 (eq_attr "type" "store1, store2, f_stores, f_stored"))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
118 "cortex_a9_ls")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
119
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
120 ;; Almost all our store multiples use an auto-increment
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
121 ;; form. Don't issue back to back load and store multiples
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
122 ;; because the load store unit will stall.
67
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
123
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
124 (define_insn_reservation "cortex_a9_store3_4" 0
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
125 (and (eq_attr "tune" "cortexa9")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
126 (eq_attr "type" "store3, store4"))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
127 "cortex_a9_ls+(cortex_a9_p0_default | cortex_a9_p1_default), cortex_a9_ls")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
128
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
129 ;; We get 16*16 multiply / mac results in 3 cycles.
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
130 (define_insn_reservation "cortex_a9_mult16" 3
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
131 (and (eq_attr "tune" "cortexa9")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
132 (eq_attr "insn" "smulxy"))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
133 "cortex_a9_mult16")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
134
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
135 ;; The 16*16 mac is slightly different that it
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
136 ;; reserves M1 and M2 in the same cycle.
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
137 (define_insn_reservation "cortex_a9_mac16" 3
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
138 (and (eq_attr "tune" "cortexa9")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
139 (eq_attr "insn" "smlaxy"))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
140 "cortex_a9_mac16")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
141
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
142
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
143 (define_insn_reservation "cortex_a9_multiply" 4
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
144 (and (eq_attr "tune" "cortexa9")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
145 (eq_attr "insn" "mul"))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
146 "cortex_a9_mult")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
147
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
148 (define_insn_reservation "cortex_a9_mac" 4
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
149 (and (eq_attr "tune" "cortexa9")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
150 (eq_attr "insn" "mla"))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
151 "cortex_a9_mac")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
152
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
153 ;; An instruction with a result in E2 can be forwarded
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
154 ;; to E2 or E1 or M1 or the load store unit in the next cycle.
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
155
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
156 (define_bypass 1 "cortex_a9_dp"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
157 "cortex_a9_dp_shift, cortex_a9_multiply,
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
158 cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2,
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
159 cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
160
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
161 (define_bypass 2 "cortex_a9_dp_shift"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
162 "cortex_a9_dp_shift, cortex_a9_multiply,
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
163 cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2,
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
164 cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
165
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
166 ;; An instruction in the load store pipeline can provide
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
167 ;; read access to a DP instruction in the P0 default pipeline
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
168 ;; before the writeback stage.
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
169
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
170 (define_bypass 3 "cortex_a9_load1_2" "cortex_a9_dp, cortex_a9_load1_2,
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
171 cortex_a9_store3_4, cortex_a9_store1_2")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
172
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
173 (define_bypass 4 "cortex_a9_load3_4" "cortex_a9_dp, cortex_a9_load1_2,
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
174 cortex_a9_store3_4, cortex_a9_store1_2, cortex_a9_load3_4")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
175
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
176 ;; Calls and branches.
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
177
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
178 ;; Branch instructions
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
179
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
180 (define_insn_reservation "cortex_a9_branch" 0
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
181 (and (eq_attr "tune" "cortexa9")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
182 (eq_attr "type" "branch"))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
183 "cortex_a9_branch")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
184
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
185 ;; Call latencies are essentially 0 but make sure
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
186 ;; dual issue doesn't happen i.e the next instruction
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
187 ;; starts at the next cycle.
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
188 (define_insn_reservation "cortex_a9_call" 0
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
189 (and (eq_attr "tune" "cortexa9")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
190 (eq_attr "type" "call"))
67
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
191 "cortex_a9_issue_branch + cortex_a9_multcycle1 + cortex_a9_ls + ca9_issue_vfp_neon")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
192
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
193
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
194 ;; Pipelining for VFP instructions.
67
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
195 ;; Issue happens either along load store unit or the VFP / Neon unit.
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
196 ;; Pipeline Instruction Classification.
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
197 ;; FPS - fcpys, ffariths, ffarithd,r_2_f,f_2_r
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
198 ;; FP_ADD - fadds, faddd, fcmps (1)
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
199 ;; FPMUL - fmul{s,d}, fmac{s,d}
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
200 ;; FPDIV - fdiv{s,d}
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
201 (define_cpu_unit "ca9fps" "cortex_a9")
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
202 (define_cpu_unit "ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4" "cortex_a9")
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
203 (define_cpu_unit "ca9fp_mul1, ca9fp_mul2 , ca9fp_mul3, ca9fp_mul4" "cortex_a9")
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
204 (define_cpu_unit "ca9fp_ds1" "cortex_a9")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
205
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
206
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
207 ;; fmrs, fmrrd, fmstat and fmrx - The data is available after 1 cycle.
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
208 (define_insn_reservation "cortex_a9_fps" 2
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
209 (and (eq_attr "tune" "cortexa9")
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
210 (eq_attr "type" "fcpys, fconsts, fconstd, ffariths, ffarithd, r_2_f, f_2_r, f_flag"))
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
211 "ca9_issue_vfp_neon + ca9fps")
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
212
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
213 (define_bypass 1
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
214 "cortex_a9_fps"
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
215 "cortex_a9_fadd, cortex_a9_fps, cortex_a9_fcmp, cortex_a9_dp, cortex_a9_dp_shift, cortex_a9_multiply")
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
216
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
217 ;; Scheduling on the FP_ADD pipeline.
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
218 (define_reservation "ca9fp_add" "ca9_issue_vfp_neon + ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
219
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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220 (define_insn_reservation "cortex_a9_fadd" 4
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221 (and (eq_attr "tune" "cortexa9")
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222 (eq_attr "type" "fadds, faddd, f_cvt"))
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223 "ca9fp_add")
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224
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225 (define_insn_reservation "cortex_a9_fcmp" 1
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226 (and (eq_attr "tune" "cortexa9")
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227 (eq_attr "type" "fcmps, fcmpd"))
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228 "ca9_issue_vfp_neon + ca9fp_add1")
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229
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230 ;; Scheduling for the Multiply and MAC instructions.
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231 (define_reservation "ca9fmuls"
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232 "ca9fp_mul1 + ca9_issue_vfp_neon, ca9fp_mul2, ca9fp_mul3, ca9fp_mul4")
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233
67
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234 (define_reservation "ca9fmuld"
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235 "ca9fp_mul1 + ca9_issue_vfp_neon, (ca9fp_mul1 + ca9fp_mul2), ca9fp_mul2, ca9fp_mul3, ca9fp_mul4")
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236
67
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237 (define_insn_reservation "cortex_a9_fmuls" 4
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238 (and (eq_attr "tune" "cortexa9")
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239 (eq_attr "type" "fmuls"))
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240 "ca9fmuls")
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241
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242 (define_insn_reservation "cortex_a9_fmuld" 5
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243 (and (eq_attr "tune" "cortexa9")
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diff changeset
244 (eq_attr "type" "fmuld"))
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parents: 55
diff changeset
245 "ca9fmuld")
0
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246
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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247 (define_insn_reservation "cortex_a9_fmacs" 8
67
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248 (and (eq_attr "tune" "cortexa9")
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diff changeset
249 (eq_attr "type" "fmacs"))
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff changeset
250 "ca9fmuls, ca9fp_add")
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251
67
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252 (define_insn_reservation "cortex_a9_fmacd" 9
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253 (and (eq_attr "tune" "cortexa9")
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254 (eq_attr "type" "fmacd"))
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff changeset
255 "ca9fmuld, ca9fp_add")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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256
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257 ;; Division pipeline description.
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258 (define_insn_reservation "cortex_a9_fdivs" 15
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diff changeset
259 (and (eq_attr "tune" "cortexa9")
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diff changeset
260 (eq_attr "type" "fdivs"))
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diff changeset
261 "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*14")
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262
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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263 (define_insn_reservation "cortex_a9_fdivd" 25
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diff changeset
264 (and (eq_attr "tune" "cortexa9")
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265 (eq_attr "type" "fdivd"))
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parents: 55
diff changeset
266 "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*24")
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267
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268 ;; Include Neon pipeline description
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269 (include "cortex-a9-neon.md")