Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/i386/mmx.md @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | b7f97abdc517 |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 ;; GCC machine description for MMX and 3dNOW! instructions |
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2 ;; Copyright (C) 2005, 2007, 2008, 2009, 2010 |
| 0 | 3 ;; Free Software Foundation, Inc. |
| 4 ;; | |
| 5 ;; This file is part of GCC. | |
| 6 ;; | |
| 7 ;; GCC is free software; you can redistribute it and/or modify | |
| 8 ;; it under the terms of the GNU General Public License as published by | |
| 9 ;; the Free Software Foundation; either version 3, or (at your option) | |
| 10 ;; any later version. | |
| 11 ;; | |
| 12 ;; GCC is distributed in the hope that it will be useful, | |
| 13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 ;; GNU General Public License for more details. | |
| 16 ;; | |
| 17 ;; You should have received a copy of the GNU General Public License | |
| 18 ;; along with GCC; see the file COPYING3. If not see | |
| 19 ;; <http://www.gnu.org/licenses/>. | |
| 20 | |
| 21 ;; The MMX and 3dNOW! patterns are in the same file because they use | |
| 22 ;; the same register file, and 3dNOW! adds a number of extensions to | |
| 23 ;; the base integer MMX isa. | |
| 24 | |
| 25 ;; Note! Except for the basic move instructions, *all* of these | |
| 26 ;; patterns are outside the normal optabs namespace. This is because | |
| 27 ;; use of these registers requires the insertion of emms or femms | |
| 28 ;; instructions to return to normal fpu mode. The compiler doesn't | |
| 29 ;; know how to do that itself, which means it's up to the user. Which | |
| 30 ;; means that we should never use any of these patterns except at the | |
| 31 ;; direction of the user via a builtin. | |
| 32 | |
| 33 ;; 8 byte integral modes handled by MMX (and by extension, SSE) | |
| 34 (define_mode_iterator MMXMODEI [V8QI V4HI V2SI]) | |
| 35 (define_mode_iterator MMXMODEI8 [V8QI V4HI V2SI V1DI]) | |
| 36 | |
| 37 ;; All 8-byte vector modes handled by MMX | |
| 38 (define_mode_iterator MMXMODE [V8QI V4HI V2SI V1DI V2SF]) | |
| 39 | |
| 40 ;; Mix-n-match | |
| 41 (define_mode_iterator MMXMODE12 [V8QI V4HI]) | |
| 42 (define_mode_iterator MMXMODE24 [V4HI V2SI]) | |
| 43 (define_mode_iterator MMXMODE248 [V4HI V2SI V1DI]) | |
| 44 | |
| 45 ;; Mapping from integer vector mode to mnemonic suffix | |
| 46 (define_mode_attr mmxvecsize [(V8QI "b") (V4HI "w") (V2SI "d") (V1DI "q")]) | |
| 47 | |
| 48 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 49 ;; | |
| 50 ;; Move patterns | |
| 51 ;; | |
| 52 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 53 | |
| 54 ;; All of these patterns are enabled for MMX as well as 3dNOW. | |
| 55 ;; This is essential for maintaining stable calling conventions. | |
| 56 | |
| 57 (define_expand "mov<mode>" | |
| 58 [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand" "") | |
| 59 (match_operand:MMXMODEI8 1 "nonimmediate_operand" ""))] | |
| 60 "TARGET_MMX" | |
| 61 { | |
| 62 ix86_expand_vector_move (<MODE>mode, operands); | |
| 63 DONE; | |
| 64 }) | |
| 65 | |
| 66 (define_insn "*mov<mode>_internal_rex64" | |
| 67 [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand" | |
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68 "=rm,r,!?y,!y,!?y,m ,!y ,*Y2,x,x ,m,r ,Yi") |
| 0 | 69 (match_operand:MMXMODEI8 1 "vector_move_operand" |
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70 "Cr ,m,C ,!y,m ,!?y,*Y2,!y ,C,xm,x,Yi,r"))] |
| 0 | 71 "TARGET_64BIT && TARGET_MMX |
| 72 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" | |
| 73 "@ | |
| 74 mov{q}\t{%1, %0|%0, %1} | |
| 75 mov{q}\t{%1, %0|%0, %1} | |
| 76 pxor\t%0, %0 | |
| 77 movq\t{%1, %0|%0, %1} | |
| 78 movq\t{%1, %0|%0, %1} | |
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79 movq\t{%1, %0|%0, %1} |
| 0 | 80 movdq2q\t{%1, %0|%0, %1} |
| 81 movq2dq\t{%1, %0|%0, %1} | |
| 82 %vpxor\t%0, %d0 | |
| 83 %vmovq\t{%1, %0|%0, %1} | |
| 84 %vmovq\t{%1, %0|%0, %1} | |
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85 %vmovd\t{%1, %0|%0, %1} |
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86 %vmovd\t{%1, %0|%0, %1}" |
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87 [(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,ssemov") |
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88 (set_attr "unit" "*,*,*,*,*,*,mmx,mmx,*,*,*,*,*") |
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89 (set_attr "prefix_rep" "*,*,*,*,*,*,1,1,*,1,*,*,*") |
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90 (set_attr "prefix_data16" "*,*,*,*,*,*,*,*,*,*,1,1,1") |
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91 (set (attr "prefix_rex") |
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92 (if_then_else (eq_attr "alternative" "9,10") |
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93 (symbol_ref "x86_extended_reg_mentioned_p (insn)") |
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94 (const_string "*"))) |
| 0 | 95 (set (attr "prefix") |
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96 (if_then_else (eq_attr "alternative" "8,9,10,11,12") |
| 0 | 97 (const_string "maybe_vex") |
| 98 (const_string "orig"))) | |
| 99 (set_attr "mode" "DI")]) | |
| 100 | |
| 101 (define_insn "*mov<mode>_internal_avx" | |
| 102 [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand" | |
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103 "=!?y,!y,!?y,m ,!y ,*Y2,*Y2,*Y2 ,m ,r ,m") |
| 0 | 104 (match_operand:MMXMODEI8 1 "vector_move_operand" |
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105 "C ,!y,m ,!?y,*Y2,!y ,C ,*Y2m,*Y2,irm,r"))] |
| 0 | 106 "TARGET_AVX |
| 107 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" | |
| 108 "@ | |
| 109 pxor\t%0, %0 | |
| 110 movq\t{%1, %0|%0, %1} | |
| 111 movq\t{%1, %0|%0, %1} | |
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112 movq\t{%1, %0|%0, %1} |
| 0 | 113 movdq2q\t{%1, %0|%0, %1} |
| 114 movq2dq\t{%1, %0|%0, %1} | |
| 115 vpxor\t%0, %0, %0 | |
| 116 vmovq\t{%1, %0|%0, %1} | |
| 117 vmovq\t{%1, %0|%0, %1} | |
| 118 # | |
| 119 #" | |
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120 [(set_attr "type" "mmx,mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,*,*") |
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121 (set_attr "unit" "*,*,*,*,mmx,mmx,*,*,*,*,*") |
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122 (set_attr "prefix_rep" "*,*,*,*,1,1,*,*,*,*,*") |
| 0 | 123 (set (attr "prefix") |
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124 (if_then_else (eq_attr "alternative" "6,7,8") |
| 0 | 125 (const_string "vex") |
| 126 (const_string "orig"))) | |
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127 (set_attr "mode" "DI,DI,DI,DI,DI,DI,TI,DI,DI,DI,DI")]) |
| 0 | 128 |
| 129 (define_insn "*mov<mode>_internal" | |
| 130 [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand" | |
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131 "=!?y,!y,!?y,m ,!y ,*Y2,*Y2,*Y2 ,m ,*x,*x,*x,m ,r ,m") |
| 0 | 132 (match_operand:MMXMODEI8 1 "vector_move_operand" |
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133 "C ,!y,m ,!?y,*Y2,!y ,C ,*Y2m,*Y2,C ,*x,m ,*x,irm,r"))] |
| 0 | 134 "TARGET_MMX |
| 135 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" | |
| 136 "@ | |
| 137 pxor\t%0, %0 | |
| 138 movq\t{%1, %0|%0, %1} | |
| 139 movq\t{%1, %0|%0, %1} | |
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140 movq\t{%1, %0|%0, %1} |
| 0 | 141 movdq2q\t{%1, %0|%0, %1} |
| 142 movq2dq\t{%1, %0|%0, %1} | |
| 143 pxor\t%0, %0 | |
| 144 movq\t{%1, %0|%0, %1} | |
| 145 movq\t{%1, %0|%0, %1} | |
| 146 xorps\t%0, %0 | |
| 147 movaps\t{%1, %0|%0, %1} | |
| 148 movlps\t{%1, %0|%0, %1} | |
| 149 movlps\t{%1, %0|%0, %1} | |
| 150 # | |
| 151 #" | |
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152 [(set_attr "type" "mmx,mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,sselog1,ssemov,ssemov,ssemov,*,*") |
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153 (set_attr "unit" "*,*,*,*,mmx,mmx,*,*,*,*,*,*,*,*,*") |
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154 (set_attr "prefix_rep" "*,*,*,*,1,1,*,1,*,*,*,*,*,*,*") |
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155 (set_attr "prefix_data16" "*,*,*,*,*,*,*,*,1,*,*,*,*,*,*") |
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156 (set_attr "mode" "DI,DI,DI,DI,DI,DI,TI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")]) |
| 0 | 157 |
| 158 (define_expand "movv2sf" | |
| 159 [(set (match_operand:V2SF 0 "nonimmediate_operand" "") | |
| 160 (match_operand:V2SF 1 "nonimmediate_operand" ""))] | |
| 161 "TARGET_MMX" | |
| 162 { | |
| 163 ix86_expand_vector_move (V2SFmode, operands); | |
| 164 DONE; | |
| 165 }) | |
| 166 | |
| 167 (define_insn "*movv2sf_internal_rex64_avx" | |
| 168 [(set (match_operand:V2SF 0 "nonimmediate_operand" | |
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169 "=rm,r,!?y,!y,!?y,m ,!y,Y2,x,x,x,m,r,x") |
| 0 | 170 (match_operand:V2SF 1 "vector_move_operand" |
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171 "Cr ,m,C ,!y,m ,!?y,Y2,!y,C,x,m,x,x,r"))] |
| 0 | 172 "TARGET_64BIT && TARGET_AVX |
| 173 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" | |
| 174 "@ | |
| 175 mov{q}\t{%1, %0|%0, %1} | |
| 176 mov{q}\t{%1, %0|%0, %1} | |
| 177 pxor\t%0, %0 | |
| 178 movq\t{%1, %0|%0, %1} | |
| 179 movq\t{%1, %0|%0, %1} | |
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180 movq\t{%1, %0|%0, %1} |
| 0 | 181 movdq2q\t{%1, %0|%0, %1} |
| 182 movq2dq\t{%1, %0|%0, %1} | |
| 183 vxorps\t%0, %0, %0 | |
| 184 vmovaps\t{%1, %0|%0, %1} | |
| 185 vmovlps\t{%1, %0, %0|%0, %0, %1} | |
| 186 vmovlps\t{%1, %0|%0, %1} | |
| 187 vmovq\t{%1, %0|%0, %1} | |
| 188 vmovq\t{%1, %0|%0, %1}" | |
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189 [(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,sselog1,ssemov,ssemov,ssemov,ssemov") |
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190 (set_attr "unit" "*,*,*,*,*,*,mmx,mmx,*,*,*,*,*,*") |
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191 (set_attr "prefix_rep" "*,*,*,*,*,*,1,1,*,*,*,*,*,*") |
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192 (set_attr "length_vex" "*,*,*,*,*,*,*,*,*,*,*,*,4,4") |
| 0 | 193 (set (attr "prefix") |
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194 (if_then_else (eq_attr "alternative" "8,9,10,11,12,13") |
| 0 | 195 (const_string "vex") |
| 196 (const_string "orig"))) | |
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197 (set_attr "mode" "DI,DI,DI,DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")]) |
| 0 | 198 |
| 199 (define_insn "*movv2sf_internal_rex64" | |
| 200 [(set (match_operand:V2SF 0 "nonimmediate_operand" | |
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201 "=rm,r,!?y,!y,!?y,m ,!y ,*Y2,x,x,x,m,r ,Yi") |
| 0 | 202 (match_operand:V2SF 1 "vector_move_operand" |
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203 "Cr ,m,C ,!y,m ,!?y,*Y2,!y ,C,x,m,x,Yi,r"))] |
| 0 | 204 "TARGET_64BIT && TARGET_MMX |
| 205 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" | |
| 206 "@ | |
| 207 mov{q}\t{%1, %0|%0, %1} | |
| 208 mov{q}\t{%1, %0|%0, %1} | |
| 209 pxor\t%0, %0 | |
| 210 movq\t{%1, %0|%0, %1} | |
| 211 movq\t{%1, %0|%0, %1} | |
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212 movq\t{%1, %0|%0, %1} |
| 0 | 213 movdq2q\t{%1, %0|%0, %1} |
| 214 movq2dq\t{%1, %0|%0, %1} | |
| 215 xorps\t%0, %0 | |
| 216 movaps\t{%1, %0|%0, %1} | |
| 217 movlps\t{%1, %0|%0, %1} | |
| 218 movlps\t{%1, %0|%0, %1} | |
| 219 movd\t{%1, %0|%0, %1} | |
| 220 movd\t{%1, %0|%0, %1}" | |
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221 [(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,sselog1,ssemov,ssemov,ssemov,ssemov") |
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222 (set_attr "unit" "*,*,*,*,*,*,mmx,mmx,*,*,*,*,*,*") |
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223 (set_attr "prefix_rep" "*,*,*,*,*,*,1,1,*,*,*,*,*,*") |
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224 (set_attr "mode" "DI,DI,DI,DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")]) |
| 0 | 225 |
| 226 (define_insn "*movv2sf_internal_avx" | |
| 227 [(set (match_operand:V2SF 0 "nonimmediate_operand" | |
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228 "=!?y,!y,!?y,m ,!y ,*Y2,*x,*x,*x,m ,r ,m") |
| 0 | 229 (match_operand:V2SF 1 "vector_move_operand" |
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230 "C ,!y,m ,!?y,*Y2,!y ,C ,*x,m ,*x,irm,r"))] |
| 0 | 231 "TARGET_AVX |
| 232 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" | |
| 233 "@ | |
| 234 pxor\t%0, %0 | |
| 235 movq\t{%1, %0|%0, %1} | |
| 236 movq\t{%1, %0|%0, %1} | |
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237 movq\t{%1, %0|%0, %1} |
| 0 | 238 movdq2q\t{%1, %0|%0, %1} |
| 239 movq2dq\t{%1, %0|%0, %1} | |
| 240 vxorps\t%0, %0, %0 | |
| 241 vmovaps\t{%1, %0|%0, %1} | |
| 242 vmovlps\t{%1, %0, %0|%0, %0, %1} | |
| 243 vmovlps\t{%1, %0|%0, %1} | |
| 244 # | |
| 245 #" | |
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246 [(set_attr "type" "mmx,mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,*,*") |
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247 (set_attr "unit" "*,*,*,*,mmx,mmx,*,*,*,*,*,*") |
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248 (set_attr "prefix_rep" "*,*,*,*,1,1,*,*,*,*,*,*") |
| 0 | 249 (set (attr "prefix") |
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250 (if_then_else (eq_attr "alternative" "6,7,8,9") |
| 0 | 251 (const_string "vex") |
| 252 (const_string "orig"))) | |
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253 (set_attr "mode" "DI,DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")]) |
| 0 | 254 |
| 255 (define_insn "*movv2sf_internal" | |
| 256 [(set (match_operand:V2SF 0 "nonimmediate_operand" | |
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257 "=!?y,!y,!?y,m ,!y ,*Y2,*x,*x,*x,m ,r ,m") |
| 0 | 258 (match_operand:V2SF 1 "vector_move_operand" |
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259 "C ,!y,m ,!?y,*Y2,!y ,C ,*x,m ,*x,irm,r"))] |
| 0 | 260 "TARGET_MMX |
| 261 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" | |
| 262 "@ | |
| 263 pxor\t%0, %0 | |
| 264 movq\t{%1, %0|%0, %1} | |
| 265 movq\t{%1, %0|%0, %1} | |
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266 movq\t{%1, %0|%0, %1} |
| 0 | 267 movdq2q\t{%1, %0|%0, %1} |
| 268 movq2dq\t{%1, %0|%0, %1} | |
| 269 xorps\t%0, %0 | |
| 270 movaps\t{%1, %0|%0, %1} | |
| 271 movlps\t{%1, %0|%0, %1} | |
| 272 movlps\t{%1, %0|%0, %1} | |
| 273 # | |
| 274 #" | |
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275 [(set_attr "type" "mmx,mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,*,*") |
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276 (set_attr "unit" "*,*,*,*,mmx,mmx,*,*,*,*,*,*") |
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277 (set_attr "prefix_rep" "*,*,*,*,1,1,*,*,*,*,*,*") |
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278 (set_attr "mode" "DI,DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")]) |
| 0 | 279 |
| 280 ;; %%% This multiword shite has got to go. | |
| 281 (define_split | |
| 282 [(set (match_operand:MMXMODE 0 "nonimmediate_operand" "") | |
| 283 (match_operand:MMXMODE 1 "general_operand" ""))] | |
| 284 "!TARGET_64BIT && reload_completed | |
| 285 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0])) | |
| 286 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))" | |
| 287 [(const_int 0)] | |
| 288 "ix86_split_long_move (operands); DONE;") | |
| 289 | |
| 290 (define_expand "push<mode>1" | |
| 291 [(match_operand:MMXMODE 0 "register_operand" "")] | |
| 292 "TARGET_MMX" | |
| 293 { | |
| 294 ix86_expand_push (<MODE>mode, operands[0]); | |
| 295 DONE; | |
| 296 }) | |
| 297 | |
| 298 (define_expand "movmisalign<mode>" | |
| 299 [(set (match_operand:MMXMODE 0 "nonimmediate_operand" "") | |
| 300 (match_operand:MMXMODE 1 "nonimmediate_operand" ""))] | |
| 301 "TARGET_MMX" | |
| 302 { | |
| 303 ix86_expand_vector_move (<MODE>mode, operands); | |
| 304 DONE; | |
| 305 }) | |
| 306 | |
| 307 (define_insn "sse_movntdi" | |
| 308 [(set (match_operand:DI 0 "memory_operand" "=m") | |
| 309 (unspec:DI [(match_operand:DI 1 "register_operand" "y")] | |
| 310 UNSPEC_MOVNT))] | |
| 311 "TARGET_SSE || TARGET_3DNOW_A" | |
| 312 "movntq\t{%1, %0|%0, %1}" | |
| 313 [(set_attr "type" "mmxmov") | |
| 314 (set_attr "mode" "DI")]) | |
| 315 | |
| 316 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 317 ;; | |
| 318 ;; Parallel single-precision floating point arithmetic | |
| 319 ;; | |
| 320 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 321 | |
| 322 (define_expand "mmx_addv2sf3" | |
| 323 [(set (match_operand:V2SF 0 "register_operand" "") | |
| 324 (plus:V2SF | |
| 325 (match_operand:V2SF 1 "nonimmediate_operand" "") | |
| 326 (match_operand:V2SF 2 "nonimmediate_operand" "")))] | |
| 327 "TARGET_3DNOW" | |
| 328 "ix86_fixup_binary_operands_no_copy (PLUS, V2SFmode, operands);") | |
| 329 | |
| 330 (define_insn "*mmx_addv2sf3" | |
| 331 [(set (match_operand:V2SF 0 "register_operand" "=y") | |
| 332 (plus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0") | |
| 333 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
| 334 "TARGET_3DNOW && ix86_binary_operator_ok (PLUS, V2SFmode, operands)" | |
| 335 "pfadd\t{%2, %0|%0, %2}" | |
| 336 [(set_attr "type" "mmxadd") | |
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337 (set_attr "prefix_extra" "1") |
| 0 | 338 (set_attr "mode" "V2SF")]) |
| 339 | |
| 340 (define_expand "mmx_subv2sf3" | |
| 341 [(set (match_operand:V2SF 0 "register_operand" "") | |
| 342 (minus:V2SF (match_operand:V2SF 1 "register_operand" "") | |
| 343 (match_operand:V2SF 2 "nonimmediate_operand" "")))] | |
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344 "TARGET_3DNOW") |
| 0 | 345 |
| 346 (define_expand "mmx_subrv2sf3" | |
| 347 [(set (match_operand:V2SF 0 "register_operand" "") | |
| 348 (minus:V2SF (match_operand:V2SF 2 "register_operand" "") | |
| 349 (match_operand:V2SF 1 "nonimmediate_operand" "")))] | |
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350 "TARGET_3DNOW") |
| 0 | 351 |
| 352 (define_insn "*mmx_subv2sf3" | |
| 353 [(set (match_operand:V2SF 0 "register_operand" "=y,y") | |
| 354 (minus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "0,ym") | |
| 355 (match_operand:V2SF 2 "nonimmediate_operand" "ym,0")))] | |
| 356 "TARGET_3DNOW && !(MEM_P (operands[0]) && MEM_P (operands[1]))" | |
| 357 "@ | |
| 358 pfsub\t{%2, %0|%0, %2} | |
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359 pfsubr\t{%1, %0|%0, %1}" |
| 0 | 360 [(set_attr "type" "mmxadd") |
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361 (set_attr "prefix_extra" "1") |
| 0 | 362 (set_attr "mode" "V2SF")]) |
| 363 | |
| 364 (define_expand "mmx_mulv2sf3" | |
| 365 [(set (match_operand:V2SF 0 "register_operand" "") | |
| 366 (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "") | |
| 367 (match_operand:V2SF 2 "nonimmediate_operand" "")))] | |
| 368 "TARGET_3DNOW" | |
| 369 "ix86_fixup_binary_operands_no_copy (MULT, V2SFmode, operands);") | |
| 370 | |
| 371 (define_insn "*mmx_mulv2sf3" | |
| 372 [(set (match_operand:V2SF 0 "register_operand" "=y") | |
| 373 (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0") | |
| 374 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
| 375 "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V2SFmode, operands)" | |
| 376 "pfmul\t{%2, %0|%0, %2}" | |
| 377 [(set_attr "type" "mmxmul") | |
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378 (set_attr "prefix_extra" "1") |
| 0 | 379 (set_attr "mode" "V2SF")]) |
| 380 | |
| 381 ;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX | |
| 382 ;; isn't really correct, as those rtl operators aren't defined when | |
| 383 ;; applied to NaNs. Hopefully the optimizers won't get too smart on us. | |
| 384 | |
| 385 (define_expand "mmx_<code>v2sf3" | |
| 386 [(set (match_operand:V2SF 0 "register_operand" "") | |
| 387 (smaxmin:V2SF | |
| 388 (match_operand:V2SF 1 "nonimmediate_operand" "") | |
| 389 (match_operand:V2SF 2 "nonimmediate_operand" "")))] | |
| 390 "TARGET_3DNOW" | |
| 391 { | |
| 392 if (!flag_finite_math_only) | |
| 393 operands[1] = force_reg (V2SFmode, operands[1]); | |
| 394 ix86_fixup_binary_operands_no_copy (<CODE>, V2SFmode, operands); | |
| 395 }) | |
| 396 | |
| 397 (define_insn "*mmx_<code>v2sf3_finite" | |
| 398 [(set (match_operand:V2SF 0 "register_operand" "=y") | |
| 399 (smaxmin:V2SF | |
| 400 (match_operand:V2SF 1 "nonimmediate_operand" "%0") | |
| 401 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
| 402 "TARGET_3DNOW && flag_finite_math_only | |
| 403 && ix86_binary_operator_ok (<CODE>, V2SFmode, operands)" | |
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404 "pf<maxmin_float>\t{%2, %0|%0, %2}" |
| 0 | 405 [(set_attr "type" "mmxadd") |
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406 (set_attr "prefix_extra" "1") |
| 0 | 407 (set_attr "mode" "V2SF")]) |
| 408 | |
| 409 (define_insn "*mmx_<code>v2sf3" | |
| 410 [(set (match_operand:V2SF 0 "register_operand" "=y") | |
| 411 (smaxmin:V2SF | |
| 412 (match_operand:V2SF 1 "register_operand" "0") | |
| 413 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
| 414 "TARGET_3DNOW" | |
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415 "pf<maxmin_float>\t{%2, %0|%0, %2}" |
| 0 | 416 [(set_attr "type" "mmxadd") |
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417 (set_attr "prefix_extra" "1") |
| 0 | 418 (set_attr "mode" "V2SF")]) |
| 419 | |
| 420 (define_insn "mmx_rcpv2sf2" | |
| 421 [(set (match_operand:V2SF 0 "register_operand" "=y") | |
| 422 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] | |
| 423 UNSPEC_PFRCP))] | |
| 424 "TARGET_3DNOW" | |
| 425 "pfrcp\t{%1, %0|%0, %1}" | |
| 426 [(set_attr "type" "mmx") | |
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427 (set_attr "prefix_extra" "1") |
| 0 | 428 (set_attr "mode" "V2SF")]) |
| 429 | |
| 430 (define_insn "mmx_rcpit1v2sf3" | |
| 431 [(set (match_operand:V2SF 0 "register_operand" "=y") | |
| 432 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0") | |
| 433 (match_operand:V2SF 2 "nonimmediate_operand" "ym")] | |
| 434 UNSPEC_PFRCPIT1))] | |
| 435 "TARGET_3DNOW" | |
| 436 "pfrcpit1\t{%2, %0|%0, %2}" | |
| 437 [(set_attr "type" "mmx") | |
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438 (set_attr "prefix_extra" "1") |
| 0 | 439 (set_attr "mode" "V2SF")]) |
| 440 | |
| 441 (define_insn "mmx_rcpit2v2sf3" | |
| 442 [(set (match_operand:V2SF 0 "register_operand" "=y") | |
| 443 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0") | |
| 444 (match_operand:V2SF 2 "nonimmediate_operand" "ym")] | |
| 445 UNSPEC_PFRCPIT2))] | |
| 446 "TARGET_3DNOW" | |
| 447 "pfrcpit2\t{%2, %0|%0, %2}" | |
| 448 [(set_attr "type" "mmx") | |
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449 (set_attr "prefix_extra" "1") |
| 0 | 450 (set_attr "mode" "V2SF")]) |
| 451 | |
| 452 (define_insn "mmx_rsqrtv2sf2" | |
| 453 [(set (match_operand:V2SF 0 "register_operand" "=y") | |
| 454 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] | |
| 455 UNSPEC_PFRSQRT))] | |
| 456 "TARGET_3DNOW" | |
| 457 "pfrsqrt\t{%1, %0|%0, %1}" | |
| 458 [(set_attr "type" "mmx") | |
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459 (set_attr "prefix_extra" "1") |
| 0 | 460 (set_attr "mode" "V2SF")]) |
| 461 | |
| 462 (define_insn "mmx_rsqit1v2sf3" | |
| 463 [(set (match_operand:V2SF 0 "register_operand" "=y") | |
| 464 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0") | |
| 465 (match_operand:V2SF 2 "nonimmediate_operand" "ym")] | |
| 466 UNSPEC_PFRSQIT1))] | |
| 467 "TARGET_3DNOW" | |
| 468 "pfrsqit1\t{%2, %0|%0, %2}" | |
| 469 [(set_attr "type" "mmx") | |
|
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470 (set_attr "prefix_extra" "1") |
| 0 | 471 (set_attr "mode" "V2SF")]) |
| 472 | |
| 473 (define_insn "mmx_haddv2sf3" | |
| 474 [(set (match_operand:V2SF 0 "register_operand" "=y") | |
| 475 (vec_concat:V2SF | |
| 476 (plus:SF | |
| 477 (vec_select:SF | |
| 478 (match_operand:V2SF 1 "register_operand" "0") | |
| 479 (parallel [(const_int 0)])) | |
| 480 (vec_select:SF (match_dup 1) (parallel [(const_int 1)]))) | |
| 481 (plus:SF | |
| 482 (vec_select:SF | |
| 483 (match_operand:V2SF 2 "nonimmediate_operand" "ym") | |
| 484 (parallel [(const_int 0)])) | |
| 485 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))] | |
| 486 "TARGET_3DNOW" | |
| 487 "pfacc\t{%2, %0|%0, %2}" | |
| 488 [(set_attr "type" "mmxadd") | |
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489 (set_attr "prefix_extra" "1") |
| 0 | 490 (set_attr "mode" "V2SF")]) |
| 491 | |
| 492 (define_insn "mmx_hsubv2sf3" | |
| 493 [(set (match_operand:V2SF 0 "register_operand" "=y") | |
| 494 (vec_concat:V2SF | |
| 495 (minus:SF | |
| 496 (vec_select:SF | |
| 497 (match_operand:V2SF 1 "register_operand" "0") | |
| 498 (parallel [(const_int 0)])) | |
| 499 (vec_select:SF (match_dup 1) (parallel [(const_int 1)]))) | |
| 500 (minus:SF | |
| 501 (vec_select:SF | |
| 502 (match_operand:V2SF 2 "nonimmediate_operand" "ym") | |
| 503 (parallel [(const_int 0)])) | |
| 504 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))] | |
| 505 "TARGET_3DNOW_A" | |
| 506 "pfnacc\t{%2, %0|%0, %2}" | |
| 507 [(set_attr "type" "mmxadd") | |
|
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508 (set_attr "prefix_extra" "1") |
| 0 | 509 (set_attr "mode" "V2SF")]) |
| 510 | |
| 511 (define_insn "mmx_addsubv2sf3" | |
| 512 [(set (match_operand:V2SF 0 "register_operand" "=y") | |
| 513 (vec_merge:V2SF | |
| 514 (plus:V2SF | |
| 515 (match_operand:V2SF 1 "register_operand" "0") | |
| 516 (match_operand:V2SF 2 "nonimmediate_operand" "ym")) | |
| 517 (minus:V2SF (match_dup 1) (match_dup 2)) | |
| 518 (const_int 1)))] | |
| 519 "TARGET_3DNOW_A" | |
| 520 "pfpnacc\t{%2, %0|%0, %2}" | |
| 521 [(set_attr "type" "mmxadd") | |
|
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522 (set_attr "prefix_extra" "1") |
| 0 | 523 (set_attr "mode" "V2SF")]) |
| 524 | |
| 525 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 526 ;; | |
| 527 ;; Parallel single-precision floating point comparisons | |
| 528 ;; | |
| 529 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 530 | |
| 531 (define_expand "mmx_eqv2sf3" | |
| 532 [(set (match_operand:V2SI 0 "register_operand" "") | |
| 533 (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "") | |
| 534 (match_operand:V2SF 2 "nonimmediate_operand" "")))] | |
| 535 "TARGET_3DNOW" | |
| 536 "ix86_fixup_binary_operands_no_copy (EQ, V2SFmode, operands);") | |
| 537 | |
| 538 (define_insn "*mmx_eqv2sf3" | |
| 539 [(set (match_operand:V2SI 0 "register_operand" "=y") | |
| 540 (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "%0") | |
| 541 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
| 542 "TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)" | |
| 543 "pfcmpeq\t{%2, %0|%0, %2}" | |
| 544 [(set_attr "type" "mmxcmp") | |
|
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545 (set_attr "prefix_extra" "1") |
| 0 | 546 (set_attr "mode" "V2SF")]) |
| 547 | |
| 548 (define_insn "mmx_gtv2sf3" | |
| 549 [(set (match_operand:V2SI 0 "register_operand" "=y") | |
| 550 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0") | |
| 551 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
| 552 "TARGET_3DNOW" | |
| 553 "pfcmpgt\t{%2, %0|%0, %2}" | |
| 554 [(set_attr "type" "mmxcmp") | |
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555 (set_attr "prefix_extra" "1") |
| 0 | 556 (set_attr "mode" "V2SF")]) |
| 557 | |
| 558 (define_insn "mmx_gev2sf3" | |
| 559 [(set (match_operand:V2SI 0 "register_operand" "=y") | |
| 560 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0") | |
| 561 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
| 562 "TARGET_3DNOW" | |
| 563 "pfcmpge\t{%2, %0|%0, %2}" | |
| 564 [(set_attr "type" "mmxcmp") | |
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565 (set_attr "prefix_extra" "1") |
| 0 | 566 (set_attr "mode" "V2SF")]) |
| 567 | |
| 568 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 569 ;; | |
| 570 ;; Parallel single-precision floating point conversion operations | |
| 571 ;; | |
| 572 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 573 | |
| 574 (define_insn "mmx_pf2id" | |
| 575 [(set (match_operand:V2SI 0 "register_operand" "=y") | |
| 576 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))] | |
| 577 "TARGET_3DNOW" | |
| 578 "pf2id\t{%1, %0|%0, %1}" | |
| 579 [(set_attr "type" "mmxcvt") | |
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580 (set_attr "prefix_extra" "1") |
| 0 | 581 (set_attr "mode" "V2SF")]) |
| 582 | |
| 583 (define_insn "mmx_pf2iw" | |
| 584 [(set (match_operand:V2SI 0 "register_operand" "=y") | |
| 585 (sign_extend:V2SI | |
| 586 (ss_truncate:V2HI | |
| 587 (fix:V2SI | |
| 588 (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))] | |
| 589 "TARGET_3DNOW_A" | |
| 590 "pf2iw\t{%1, %0|%0, %1}" | |
| 591 [(set_attr "type" "mmxcvt") | |
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592 (set_attr "prefix_extra" "1") |
| 0 | 593 (set_attr "mode" "V2SF")]) |
| 594 | |
| 595 (define_insn "mmx_pi2fw" | |
| 596 [(set (match_operand:V2SF 0 "register_operand" "=y") | |
| 597 (float:V2SF | |
| 598 (sign_extend:V2SI | |
| 599 (truncate:V2HI | |
| 600 (match_operand:V2SI 1 "nonimmediate_operand" "ym")))))] | |
| 601 "TARGET_3DNOW_A" | |
| 602 "pi2fw\t{%1, %0|%0, %1}" | |
| 603 [(set_attr "type" "mmxcvt") | |
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604 (set_attr "prefix_extra" "1") |
| 0 | 605 (set_attr "mode" "V2SF")]) |
| 606 | |
| 607 (define_insn "mmx_floatv2si2" | |
| 608 [(set (match_operand:V2SF 0 "register_operand" "=y") | |
| 609 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))] | |
| 610 "TARGET_3DNOW" | |
| 611 "pi2fd\t{%1, %0|%0, %1}" | |
| 612 [(set_attr "type" "mmxcvt") | |
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613 (set_attr "prefix_extra" "1") |
| 0 | 614 (set_attr "mode" "V2SF")]) |
| 615 | |
| 616 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 617 ;; | |
| 618 ;; Parallel single-precision floating point element swizzling | |
| 619 ;; | |
| 620 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 621 | |
| 622 (define_insn "mmx_pswapdv2sf2" | |
| 623 [(set (match_operand:V2SF 0 "register_operand" "=y") | |
| 624 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym") | |
| 625 (parallel [(const_int 1) (const_int 0)])))] | |
| 626 "TARGET_3DNOW_A" | |
| 627 "pswapd\t{%1, %0|%0, %1}" | |
| 628 [(set_attr "type" "mmxcvt") | |
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629 (set_attr "prefix_extra" "1") |
| 0 | 630 (set_attr "mode" "V2SF")]) |
| 631 | |
| 632 (define_insn "*vec_dupv2sf" | |
| 633 [(set (match_operand:V2SF 0 "register_operand" "=y") | |
| 634 (vec_duplicate:V2SF | |
| 635 (match_operand:SF 1 "register_operand" "0")))] | |
| 636 "TARGET_MMX" | |
| 637 "punpckldq\t%0, %0" | |
| 638 [(set_attr "type" "mmxcvt") | |
| 639 (set_attr "mode" "DI")]) | |
| 640 | |
| 641 (define_insn "*mmx_concatv2sf" | |
| 642 [(set (match_operand:V2SF 0 "register_operand" "=y,y") | |
| 643 (vec_concat:V2SF | |
| 644 (match_operand:SF 1 "nonimmediate_operand" " 0,rm") | |
| 645 (match_operand:SF 2 "vector_move_operand" "ym,C")))] | |
| 646 "TARGET_MMX && !TARGET_SSE" | |
| 647 "@ | |
| 648 punpckldq\t{%2, %0|%0, %2} | |
| 649 movd\t{%1, %0|%0, %1}" | |
| 650 [(set_attr "type" "mmxcvt,mmxmov") | |
| 651 (set_attr "mode" "DI")]) | |
| 652 | |
| 653 (define_expand "vec_setv2sf" | |
| 654 [(match_operand:V2SF 0 "register_operand" "") | |
| 655 (match_operand:SF 1 "register_operand" "") | |
| 656 (match_operand 2 "const_int_operand" "")] | |
| 657 "TARGET_MMX" | |
| 658 { | |
| 659 ix86_expand_vector_set (false, operands[0], operands[1], | |
| 660 INTVAL (operands[2])); | |
| 661 DONE; | |
| 662 }) | |
| 663 | |
| 664 ;; Avoid combining registers from different units in a single alternative, | |
| 665 ;; see comment above inline_secondary_memory_needed function in i386.c | |
| 666 (define_insn_and_split "*vec_extractv2sf_0" | |
| 667 [(set (match_operand:SF 0 "nonimmediate_operand" "=x, m,y ,m,f,r") | |
| 668 (vec_select:SF | |
| 669 (match_operand:V2SF 1 "nonimmediate_operand" " xm,x,ym,y,m,m") | |
| 670 (parallel [(const_int 0)])))] | |
| 671 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" | |
| 672 "#" | |
| 673 "&& reload_completed" | |
| 674 [(const_int 0)] | |
| 675 { | |
| 676 rtx op1 = operands[1]; | |
| 677 if (REG_P (op1)) | |
| 678 op1 = gen_rtx_REG (SFmode, REGNO (op1)); | |
| 679 else | |
| 680 op1 = gen_lowpart (SFmode, op1); | |
| 681 emit_move_insn (operands[0], op1); | |
| 682 DONE; | |
| 683 }) | |
| 684 | |
| 685 ;; Avoid combining registers from different units in a single alternative, | |
| 686 ;; see comment above inline_secondary_memory_needed function in i386.c | |
| 687 (define_insn "*vec_extractv2sf_1" | |
| 688 [(set (match_operand:SF 0 "nonimmediate_operand" "=y,x,y,x,f,r") | |
| 689 (vec_select:SF | |
| 690 (match_operand:V2SF 1 "nonimmediate_operand" " 0,0,o,o,o,o") | |
| 691 (parallel [(const_int 1)])))] | |
| 692 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" | |
| 693 "@ | |
| 694 punpckhdq\t%0, %0 | |
| 695 unpckhps\t%0, %0 | |
| 696 # | |
| 697 # | |
| 698 # | |
| 699 #" | |
| 700 [(set_attr "type" "mmxcvt,sselog1,mmxmov,ssemov,fmov,imov") | |
| 701 (set_attr "mode" "DI,V4SF,SF,SF,SF,SF")]) | |
| 702 | |
| 703 (define_split | |
| 704 [(set (match_operand:SF 0 "register_operand" "") | |
| 705 (vec_select:SF | |
| 706 (match_operand:V2SF 1 "memory_operand" "") | |
| 707 (parallel [(const_int 1)])))] | |
| 708 "TARGET_MMX && reload_completed" | |
| 709 [(const_int 0)] | |
| 710 { | |
| 711 operands[1] = adjust_address (operands[1], SFmode, 4); | |
| 712 emit_move_insn (operands[0], operands[1]); | |
| 713 DONE; | |
| 714 }) | |
| 715 | |
| 716 (define_expand "vec_extractv2sf" | |
| 717 [(match_operand:SF 0 "register_operand" "") | |
| 718 (match_operand:V2SF 1 "register_operand" "") | |
| 719 (match_operand 2 "const_int_operand" "")] | |
| 720 "TARGET_MMX" | |
| 721 { | |
| 722 ix86_expand_vector_extract (false, operands[0], operands[1], | |
| 723 INTVAL (operands[2])); | |
| 724 DONE; | |
| 725 }) | |
| 726 | |
| 727 (define_expand "vec_initv2sf" | |
| 728 [(match_operand:V2SF 0 "register_operand" "") | |
| 729 (match_operand 1 "" "")] | |
| 730 "TARGET_SSE" | |
| 731 { | |
| 732 ix86_expand_vector_init (false, operands[0], operands[1]); | |
| 733 DONE; | |
| 734 }) | |
| 735 | |
| 736 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 737 ;; | |
| 738 ;; Parallel integral arithmetic | |
| 739 ;; | |
| 740 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 741 | |
| 742 (define_expand "mmx_<plusminus_insn><mode>3" | |
| 743 [(set (match_operand:MMXMODEI8 0 "register_operand" "") | |
| 744 (plusminus:MMXMODEI8 | |
| 745 (match_operand:MMXMODEI8 1 "nonimmediate_operand" "") | |
| 746 (match_operand:MMXMODEI8 2 "nonimmediate_operand" "")))] | |
| 747 "TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode)" | |
| 748 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") | |
| 749 | |
| 750 (define_insn "*mmx_<plusminus_insn><mode>3" | |
| 751 [(set (match_operand:MMXMODEI8 0 "register_operand" "=y") | |
| 752 (plusminus:MMXMODEI8 | |
| 753 (match_operand:MMXMODEI8 1 "nonimmediate_operand" "<comm>0") | |
| 754 (match_operand:MMXMODEI8 2 "nonimmediate_operand" "ym")))] | |
| 755 "(TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode)) | |
| 756 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" | |
| 757 "p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}" | |
| 758 [(set_attr "type" "mmxadd") | |
| 759 (set_attr "mode" "DI")]) | |
| 760 | |
| 761 (define_expand "mmx_<plusminus_insn><mode>3" | |
| 762 [(set (match_operand:MMXMODE12 0 "register_operand" "") | |
| 763 (sat_plusminus:MMXMODE12 | |
| 764 (match_operand:MMXMODE12 1 "nonimmediate_operand" "") | |
| 765 (match_operand:MMXMODE12 2 "nonimmediate_operand" "")))] | |
| 766 "TARGET_MMX" | |
| 767 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") | |
| 768 | |
| 769 (define_insn "*mmx_<plusminus_insn><mode>3" | |
| 770 [(set (match_operand:MMXMODE12 0 "register_operand" "=y") | |
| 771 (sat_plusminus:MMXMODE12 | |
| 772 (match_operand:MMXMODE12 1 "nonimmediate_operand" "<comm>0") | |
| 773 (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))] | |
| 774 "TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" | |
| 775 "p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}" | |
| 776 [(set_attr "type" "mmxadd") | |
| 777 (set_attr "mode" "DI")]) | |
| 778 | |
| 779 (define_expand "mmx_mulv4hi3" | |
| 780 [(set (match_operand:V4HI 0 "register_operand" "") | |
| 781 (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "") | |
| 782 (match_operand:V4HI 2 "nonimmediate_operand" "")))] | |
| 783 "TARGET_MMX" | |
| 784 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") | |
| 785 | |
| 786 (define_insn "*mmx_mulv4hi3" | |
| 787 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 788 (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0") | |
| 789 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
| 790 "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)" | |
| 791 "pmullw\t{%2, %0|%0, %2}" | |
| 792 [(set_attr "type" "mmxmul") | |
| 793 (set_attr "mode" "DI")]) | |
| 794 | |
| 795 (define_expand "mmx_smulv4hi3_highpart" | |
| 796 [(set (match_operand:V4HI 0 "register_operand" "") | |
| 797 (truncate:V4HI | |
| 798 (lshiftrt:V4SI | |
| 799 (mult:V4SI | |
| 800 (sign_extend:V4SI | |
| 801 (match_operand:V4HI 1 "nonimmediate_operand" "")) | |
| 802 (sign_extend:V4SI | |
| 803 (match_operand:V4HI 2 "nonimmediate_operand" ""))) | |
| 804 (const_int 16))))] | |
| 805 "TARGET_MMX" | |
| 806 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") | |
| 807 | |
| 808 (define_insn "*mmx_smulv4hi3_highpart" | |
| 809 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 810 (truncate:V4HI | |
| 811 (lshiftrt:V4SI | |
| 812 (mult:V4SI | |
| 813 (sign_extend:V4SI | |
| 814 (match_operand:V4HI 1 "nonimmediate_operand" "%0")) | |
| 815 (sign_extend:V4SI | |
| 816 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) | |
| 817 (const_int 16))))] | |
| 818 "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)" | |
| 819 "pmulhw\t{%2, %0|%0, %2}" | |
| 820 [(set_attr "type" "mmxmul") | |
| 821 (set_attr "mode" "DI")]) | |
| 822 | |
| 823 (define_expand "mmx_umulv4hi3_highpart" | |
| 824 [(set (match_operand:V4HI 0 "register_operand" "") | |
| 825 (truncate:V4HI | |
| 826 (lshiftrt:V4SI | |
| 827 (mult:V4SI | |
| 828 (zero_extend:V4SI | |
| 829 (match_operand:V4HI 1 "nonimmediate_operand" "")) | |
| 830 (zero_extend:V4SI | |
| 831 (match_operand:V4HI 2 "nonimmediate_operand" ""))) | |
| 832 (const_int 16))))] | |
| 833 "TARGET_SSE || TARGET_3DNOW_A" | |
| 834 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") | |
| 835 | |
| 836 (define_insn "*mmx_umulv4hi3_highpart" | |
| 837 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 838 (truncate:V4HI | |
| 839 (lshiftrt:V4SI | |
| 840 (mult:V4SI | |
| 841 (zero_extend:V4SI | |
| 842 (match_operand:V4HI 1 "nonimmediate_operand" "%0")) | |
| 843 (zero_extend:V4SI | |
| 844 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) | |
| 845 (const_int 16))))] | |
| 846 "(TARGET_SSE || TARGET_3DNOW_A) | |
| 847 && ix86_binary_operator_ok (MULT, V4HImode, operands)" | |
| 848 "pmulhuw\t{%2, %0|%0, %2}" | |
| 849 [(set_attr "type" "mmxmul") | |
| 850 (set_attr "mode" "DI")]) | |
| 851 | |
| 852 (define_expand "mmx_pmaddwd" | |
| 853 [(set (match_operand:V2SI 0 "register_operand" "") | |
| 854 (plus:V2SI | |
| 855 (mult:V2SI | |
| 856 (sign_extend:V2SI | |
| 857 (vec_select:V2HI | |
| 858 (match_operand:V4HI 1 "nonimmediate_operand" "") | |
| 859 (parallel [(const_int 0) (const_int 2)]))) | |
| 860 (sign_extend:V2SI | |
| 861 (vec_select:V2HI | |
| 862 (match_operand:V4HI 2 "nonimmediate_operand" "") | |
| 863 (parallel [(const_int 0) (const_int 2)])))) | |
| 864 (mult:V2SI | |
| 865 (sign_extend:V2SI | |
| 866 (vec_select:V2HI (match_dup 1) | |
| 867 (parallel [(const_int 1) (const_int 3)]))) | |
| 868 (sign_extend:V2SI | |
| 869 (vec_select:V2HI (match_dup 2) | |
| 870 (parallel [(const_int 1) (const_int 3)]))))))] | |
| 871 "TARGET_MMX" | |
| 872 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") | |
| 873 | |
| 874 (define_insn "*mmx_pmaddwd" | |
| 875 [(set (match_operand:V2SI 0 "register_operand" "=y") | |
| 876 (plus:V2SI | |
| 877 (mult:V2SI | |
| 878 (sign_extend:V2SI | |
| 879 (vec_select:V2HI | |
| 880 (match_operand:V4HI 1 "nonimmediate_operand" "%0") | |
| 881 (parallel [(const_int 0) (const_int 2)]))) | |
| 882 (sign_extend:V2SI | |
| 883 (vec_select:V2HI | |
| 884 (match_operand:V4HI 2 "nonimmediate_operand" "ym") | |
| 885 (parallel [(const_int 0) (const_int 2)])))) | |
| 886 (mult:V2SI | |
| 887 (sign_extend:V2SI | |
| 888 (vec_select:V2HI (match_dup 1) | |
| 889 (parallel [(const_int 1) (const_int 3)]))) | |
| 890 (sign_extend:V2SI | |
| 891 (vec_select:V2HI (match_dup 2) | |
| 892 (parallel [(const_int 1) (const_int 3)]))))))] | |
| 893 "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)" | |
| 894 "pmaddwd\t{%2, %0|%0, %2}" | |
| 895 [(set_attr "type" "mmxmul") | |
| 896 (set_attr "mode" "DI")]) | |
| 897 | |
| 898 (define_expand "mmx_pmulhrwv4hi3" | |
| 899 [(set (match_operand:V4HI 0 "register_operand" "") | |
| 900 (truncate:V4HI | |
| 901 (lshiftrt:V4SI | |
| 902 (plus:V4SI | |
| 903 (mult:V4SI | |
| 904 (sign_extend:V4SI | |
| 905 (match_operand:V4HI 1 "nonimmediate_operand" "")) | |
| 906 (sign_extend:V4SI | |
| 907 (match_operand:V4HI 2 "nonimmediate_operand" ""))) | |
| 908 (const_vector:V4SI [(const_int 32768) (const_int 32768) | |
| 909 (const_int 32768) (const_int 32768)])) | |
| 910 (const_int 16))))] | |
| 911 "TARGET_3DNOW" | |
| 912 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") | |
| 913 | |
| 914 (define_insn "*mmx_pmulhrwv4hi3" | |
| 915 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 916 (truncate:V4HI | |
| 917 (lshiftrt:V4SI | |
| 918 (plus:V4SI | |
| 919 (mult:V4SI | |
| 920 (sign_extend:V4SI | |
| 921 (match_operand:V4HI 1 "nonimmediate_operand" "%0")) | |
| 922 (sign_extend:V4SI | |
| 923 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) | |
| 924 (const_vector:V4SI [(const_int 32768) (const_int 32768) | |
| 925 (const_int 32768) (const_int 32768)])) | |
| 926 (const_int 16))))] | |
| 927 "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V4HImode, operands)" | |
| 928 "pmulhrw\t{%2, %0|%0, %2}" | |
| 929 [(set_attr "type" "mmxmul") | |
|
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930 (set_attr "prefix_extra" "1") |
| 0 | 931 (set_attr "mode" "DI")]) |
| 932 | |
| 933 (define_expand "sse2_umulv1siv1di3" | |
| 934 [(set (match_operand:V1DI 0 "register_operand" "") | |
| 935 (mult:V1DI | |
| 936 (zero_extend:V1DI | |
| 937 (vec_select:V1SI | |
| 938 (match_operand:V2SI 1 "nonimmediate_operand" "") | |
| 939 (parallel [(const_int 0)]))) | |
| 940 (zero_extend:V1DI | |
| 941 (vec_select:V1SI | |
| 942 (match_operand:V2SI 2 "nonimmediate_operand" "") | |
| 943 (parallel [(const_int 0)])))))] | |
| 944 "TARGET_SSE2" | |
| 945 "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);") | |
| 946 | |
| 947 (define_insn "*sse2_umulv1siv1di3" | |
| 948 [(set (match_operand:V1DI 0 "register_operand" "=y") | |
| 949 (mult:V1DI | |
| 950 (zero_extend:V1DI | |
| 951 (vec_select:V1SI | |
| 952 (match_operand:V2SI 1 "nonimmediate_operand" "%0") | |
| 953 (parallel [(const_int 0)]))) | |
| 954 (zero_extend:V1DI | |
| 955 (vec_select:V1SI | |
| 956 (match_operand:V2SI 2 "nonimmediate_operand" "ym") | |
| 957 (parallel [(const_int 0)])))))] | |
| 958 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V2SImode, operands)" | |
| 959 "pmuludq\t{%2, %0|%0, %2}" | |
| 960 [(set_attr "type" "mmxmul") | |
| 961 (set_attr "mode" "DI")]) | |
| 962 | |
| 963 (define_expand "mmx_<code>v4hi3" | |
| 964 [(set (match_operand:V4HI 0 "register_operand" "") | |
| 965 (smaxmin:V4HI | |
| 966 (match_operand:V4HI 1 "nonimmediate_operand" "") | |
| 967 (match_operand:V4HI 2 "nonimmediate_operand" "")))] | |
| 968 "TARGET_SSE || TARGET_3DNOW_A" | |
| 969 "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);") | |
| 970 | |
| 971 (define_insn "*mmx_<code>v4hi3" | |
| 972 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 973 (smaxmin:V4HI | |
| 974 (match_operand:V4HI 1 "nonimmediate_operand" "%0") | |
| 975 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
| 976 "(TARGET_SSE || TARGET_3DNOW_A) | |
| 977 && ix86_binary_operator_ok (<CODE>, V4HImode, operands)" | |
|
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978 "p<maxmin_int>w\t{%2, %0|%0, %2}" |
| 0 | 979 [(set_attr "type" "mmxadd") |
| 980 (set_attr "mode" "DI")]) | |
| 981 | |
| 982 (define_expand "mmx_<code>v8qi3" | |
| 983 [(set (match_operand:V8QI 0 "register_operand" "") | |
| 984 (umaxmin:V8QI | |
| 985 (match_operand:V8QI 1 "nonimmediate_operand" "") | |
| 986 (match_operand:V8QI 2 "nonimmediate_operand" "")))] | |
| 987 "TARGET_SSE || TARGET_3DNOW_A" | |
| 988 "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);") | |
| 989 | |
| 990 (define_insn "*mmx_<code>v8qi3" | |
| 991 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 992 (umaxmin:V8QI | |
| 993 (match_operand:V8QI 1 "nonimmediate_operand" "%0") | |
| 994 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
| 995 "(TARGET_SSE || TARGET_3DNOW_A) | |
| 996 && ix86_binary_operator_ok (<CODE>, V8QImode, operands)" | |
|
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997 "p<maxmin_int>b\t{%2, %0|%0, %2}" |
| 0 | 998 [(set_attr "type" "mmxadd") |
| 999 (set_attr "mode" "DI")]) | |
| 1000 | |
| 1001 (define_insn "mmx_ashr<mode>3" | |
| 1002 [(set (match_operand:MMXMODE24 0 "register_operand" "=y") | |
| 1003 (ashiftrt:MMXMODE24 | |
| 1004 (match_operand:MMXMODE24 1 "register_operand" "0") | |
| 1005 (match_operand:SI 2 "nonmemory_operand" "yN")))] | |
| 1006 "TARGET_MMX" | |
| 1007 "psra<mmxvecsize>\t{%2, %0|%0, %2}" | |
| 1008 [(set_attr "type" "mmxshft") | |
|
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1009 (set (attr "length_immediate") |
|
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1010 (if_then_else (match_operand 2 "const_int_operand" "") |
|
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1011 (const_string "1") |
|
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|
1012 (const_string "0"))) |
| 0 | 1013 (set_attr "mode" "DI")]) |
| 1014 | |
| 1015 (define_insn "mmx_lshr<mode>3" | |
| 1016 [(set (match_operand:MMXMODE248 0 "register_operand" "=y") | |
| 1017 (lshiftrt:MMXMODE248 | |
| 1018 (match_operand:MMXMODE248 1 "register_operand" "0") | |
| 1019 (match_operand:SI 2 "nonmemory_operand" "yN")))] | |
| 1020 "TARGET_MMX" | |
| 1021 "psrl<mmxvecsize>\t{%2, %0|%0, %2}" | |
| 1022 [(set_attr "type" "mmxshft") | |
|
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1023 (set (attr "length_immediate") |
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1024 (if_then_else (match_operand 2 "const_int_operand" "") |
|
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1025 (const_string "1") |
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1026 (const_string "0"))) |
| 0 | 1027 (set_attr "mode" "DI")]) |
| 1028 | |
| 1029 (define_insn "mmx_ashl<mode>3" | |
| 1030 [(set (match_operand:MMXMODE248 0 "register_operand" "=y") | |
| 1031 (ashift:MMXMODE248 | |
| 1032 (match_operand:MMXMODE248 1 "register_operand" "0") | |
| 1033 (match_operand:SI 2 "nonmemory_operand" "yN")))] | |
| 1034 "TARGET_MMX" | |
| 1035 "psll<mmxvecsize>\t{%2, %0|%0, %2}" | |
| 1036 [(set_attr "type" "mmxshft") | |
|
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1037 (set (attr "length_immediate") |
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1038 (if_then_else (match_operand 2 "const_int_operand" "") |
|
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1039 (const_string "1") |
|
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1040 (const_string "0"))) |
| 0 | 1041 (set_attr "mode" "DI")]) |
| 1042 | |
| 1043 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 1044 ;; | |
| 1045 ;; Parallel integral comparisons | |
| 1046 ;; | |
| 1047 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 1048 | |
| 1049 (define_expand "mmx_eq<mode>3" | |
| 1050 [(set (match_operand:MMXMODEI 0 "register_operand" "") | |
| 1051 (eq:MMXMODEI | |
| 1052 (match_operand:MMXMODEI 1 "nonimmediate_operand" "") | |
| 1053 (match_operand:MMXMODEI 2 "nonimmediate_operand" "")))] | |
| 1054 "TARGET_MMX" | |
| 1055 "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);") | |
| 1056 | |
| 1057 (define_insn "*mmx_eq<mode>3" | |
| 1058 [(set (match_operand:MMXMODEI 0 "register_operand" "=y") | |
| 1059 (eq:MMXMODEI | |
| 1060 (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0") | |
| 1061 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))] | |
| 1062 "TARGET_MMX && ix86_binary_operator_ok (EQ, <MODE>mode, operands)" | |
| 1063 "pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}" | |
| 1064 [(set_attr "type" "mmxcmp") | |
| 1065 (set_attr "mode" "DI")]) | |
| 1066 | |
| 1067 (define_insn "mmx_gt<mode>3" | |
| 1068 [(set (match_operand:MMXMODEI 0 "register_operand" "=y") | |
| 1069 (gt:MMXMODEI | |
| 1070 (match_operand:MMXMODEI 1 "register_operand" "0") | |
| 1071 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))] | |
| 1072 "TARGET_MMX" | |
| 1073 "pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}" | |
| 1074 [(set_attr "type" "mmxcmp") | |
| 1075 (set_attr "mode" "DI")]) | |
| 1076 | |
| 1077 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 1078 ;; | |
| 1079 ;; Parallel integral logical operations | |
| 1080 ;; | |
| 1081 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 1082 | |
| 1083 (define_insn "mmx_andnot<mode>3" | |
| 1084 [(set (match_operand:MMXMODEI 0 "register_operand" "=y") | |
| 1085 (and:MMXMODEI | |
| 1086 (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0")) | |
| 1087 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))] | |
| 1088 "TARGET_MMX" | |
| 1089 "pandn\t{%2, %0|%0, %2}" | |
| 1090 [(set_attr "type" "mmxadd") | |
| 1091 (set_attr "mode" "DI")]) | |
| 1092 | |
| 1093 (define_expand "mmx_<code><mode>3" | |
| 1094 [(set (match_operand:MMXMODEI 0 "register_operand" "") | |
|
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|
1095 (any_logic:MMXMODEI |
| 0 | 1096 (match_operand:MMXMODEI 1 "nonimmediate_operand" "") |
| 1097 (match_operand:MMXMODEI 2 "nonimmediate_operand" "")))] | |
| 1098 "TARGET_MMX" | |
| 1099 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") | |
| 1100 | |
| 1101 (define_insn "*mmx_<code><mode>3" | |
| 1102 [(set (match_operand:MMXMODEI 0 "register_operand" "=y") | |
|
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1103 (any_logic:MMXMODEI |
| 0 | 1104 (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0") |
| 1105 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))] | |
| 1106 "TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" | |
|
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1107 "p<logic>\t{%2, %0|%0, %2}" |
| 0 | 1108 [(set_attr "type" "mmxadd") |
| 1109 (set_attr "mode" "DI")]) | |
| 1110 | |
| 1111 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 1112 ;; | |
| 1113 ;; Parallel integral element swizzling | |
| 1114 ;; | |
| 1115 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 1116 | |
| 1117 (define_insn "mmx_packsswb" | |
| 1118 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 1119 (vec_concat:V8QI | |
| 1120 (ss_truncate:V4QI | |
| 1121 (match_operand:V4HI 1 "register_operand" "0")) | |
| 1122 (ss_truncate:V4QI | |
| 1123 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))))] | |
| 1124 "TARGET_MMX" | |
| 1125 "packsswb\t{%2, %0|%0, %2}" | |
| 1126 [(set_attr "type" "mmxshft") | |
| 1127 (set_attr "mode" "DI")]) | |
| 1128 | |
| 1129 (define_insn "mmx_packssdw" | |
| 1130 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 1131 (vec_concat:V4HI | |
| 1132 (ss_truncate:V2HI | |
| 1133 (match_operand:V2SI 1 "register_operand" "0")) | |
| 1134 (ss_truncate:V2HI | |
| 1135 (match_operand:V2SI 2 "nonimmediate_operand" "ym"))))] | |
| 1136 "TARGET_MMX" | |
| 1137 "packssdw\t{%2, %0|%0, %2}" | |
| 1138 [(set_attr "type" "mmxshft") | |
| 1139 (set_attr "mode" "DI")]) | |
| 1140 | |
| 1141 (define_insn "mmx_packuswb" | |
| 1142 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 1143 (vec_concat:V8QI | |
| 1144 (us_truncate:V4QI | |
| 1145 (match_operand:V4HI 1 "register_operand" "0")) | |
| 1146 (us_truncate:V4QI | |
| 1147 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))))] | |
| 1148 "TARGET_MMX" | |
| 1149 "packuswb\t{%2, %0|%0, %2}" | |
| 1150 [(set_attr "type" "mmxshft") | |
| 1151 (set_attr "mode" "DI")]) | |
| 1152 | |
| 1153 (define_insn "mmx_punpckhbw" | |
| 1154 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 1155 (vec_select:V8QI | |
| 1156 (vec_concat:V16QI | |
| 1157 (match_operand:V8QI 1 "register_operand" "0") | |
| 1158 (match_operand:V8QI 2 "nonimmediate_operand" "ym")) | |
| 1159 (parallel [(const_int 4) (const_int 12) | |
| 1160 (const_int 5) (const_int 13) | |
| 1161 (const_int 6) (const_int 14) | |
| 1162 (const_int 7) (const_int 15)])))] | |
| 1163 "TARGET_MMX" | |
| 1164 "punpckhbw\t{%2, %0|%0, %2}" | |
| 1165 [(set_attr "type" "mmxcvt") | |
| 1166 (set_attr "mode" "DI")]) | |
| 1167 | |
| 1168 (define_insn "mmx_punpcklbw" | |
| 1169 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 1170 (vec_select:V8QI | |
| 1171 (vec_concat:V16QI | |
| 1172 (match_operand:V8QI 1 "register_operand" "0") | |
| 1173 (match_operand:V8QI 2 "nonimmediate_operand" "ym")) | |
| 1174 (parallel [(const_int 0) (const_int 8) | |
| 1175 (const_int 1) (const_int 9) | |
| 1176 (const_int 2) (const_int 10) | |
| 1177 (const_int 3) (const_int 11)])))] | |
| 1178 "TARGET_MMX" | |
| 1179 "punpcklbw\t{%2, %0|%0, %2}" | |
| 1180 [(set_attr "type" "mmxcvt") | |
| 1181 (set_attr "mode" "DI")]) | |
| 1182 | |
| 1183 (define_insn "mmx_punpckhwd" | |
| 1184 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 1185 (vec_select:V4HI | |
| 1186 (vec_concat:V8HI | |
| 1187 (match_operand:V4HI 1 "register_operand" "0") | |
| 1188 (match_operand:V4HI 2 "nonimmediate_operand" "ym")) | |
| 1189 (parallel [(const_int 2) (const_int 6) | |
| 1190 (const_int 3) (const_int 7)])))] | |
| 1191 "TARGET_MMX" | |
| 1192 "punpckhwd\t{%2, %0|%0, %2}" | |
| 1193 [(set_attr "type" "mmxcvt") | |
| 1194 (set_attr "mode" "DI")]) | |
| 1195 | |
| 1196 (define_insn "mmx_punpcklwd" | |
| 1197 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 1198 (vec_select:V4HI | |
| 1199 (vec_concat:V8HI | |
| 1200 (match_operand:V4HI 1 "register_operand" "0") | |
| 1201 (match_operand:V4HI 2 "nonimmediate_operand" "ym")) | |
| 1202 (parallel [(const_int 0) (const_int 4) | |
| 1203 (const_int 1) (const_int 5)])))] | |
| 1204 "TARGET_MMX" | |
| 1205 "punpcklwd\t{%2, %0|%0, %2}" | |
| 1206 [(set_attr "type" "mmxcvt") | |
| 1207 (set_attr "mode" "DI")]) | |
| 1208 | |
| 1209 (define_insn "mmx_punpckhdq" | |
| 1210 [(set (match_operand:V2SI 0 "register_operand" "=y") | |
| 1211 (vec_select:V2SI | |
| 1212 (vec_concat:V4SI | |
| 1213 (match_operand:V2SI 1 "register_operand" "0") | |
| 1214 (match_operand:V2SI 2 "nonimmediate_operand" "ym")) | |
| 1215 (parallel [(const_int 1) | |
| 1216 (const_int 3)])))] | |
| 1217 "TARGET_MMX" | |
| 1218 "punpckhdq\t{%2, %0|%0, %2}" | |
| 1219 [(set_attr "type" "mmxcvt") | |
| 1220 (set_attr "mode" "DI")]) | |
| 1221 | |
| 1222 (define_insn "mmx_punpckldq" | |
| 1223 [(set (match_operand:V2SI 0 "register_operand" "=y") | |
| 1224 (vec_select:V2SI | |
| 1225 (vec_concat:V4SI | |
| 1226 (match_operand:V2SI 1 "register_operand" "0") | |
| 1227 (match_operand:V2SI 2 "nonimmediate_operand" "ym")) | |
| 1228 (parallel [(const_int 0) | |
| 1229 (const_int 2)])))] | |
| 1230 "TARGET_MMX" | |
| 1231 "punpckldq\t{%2, %0|%0, %2}" | |
| 1232 [(set_attr "type" "mmxcvt") | |
| 1233 (set_attr "mode" "DI")]) | |
| 1234 | |
| 1235 (define_expand "mmx_pinsrw" | |
| 1236 [(set (match_operand:V4HI 0 "register_operand" "") | |
| 1237 (vec_merge:V4HI | |
| 1238 (vec_duplicate:V4HI | |
| 1239 (match_operand:SI 2 "nonimmediate_operand" "")) | |
| 1240 (match_operand:V4HI 1 "register_operand" "") | |
| 1241 (match_operand:SI 3 "const_0_to_3_operand" "")))] | |
| 1242 "TARGET_SSE || TARGET_3DNOW_A" | |
| 1243 { | |
| 1244 operands[2] = gen_lowpart (HImode, operands[2]); | |
| 1245 operands[3] = GEN_INT (1 << INTVAL (operands[3])); | |
| 1246 }) | |
| 1247 | |
| 1248 (define_insn "*mmx_pinsrw" | |
| 1249 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 1250 (vec_merge:V4HI | |
| 1251 (vec_duplicate:V4HI | |
| 1252 (match_operand:HI 2 "nonimmediate_operand" "rm")) | |
| 1253 (match_operand:V4HI 1 "register_operand" "0") | |
| 1254 (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))] | |
| 1255 "TARGET_SSE || TARGET_3DNOW_A" | |
| 1256 { | |
| 1257 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3]))); | |
|
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0
diff
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|
1258 if (MEM_P (operands[2])) |
|
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diff
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|
1259 return "pinsrw\t{%3, %2, %0|%0, %2, %3}"; |
|
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diff
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|
1260 else |
|
3bfb6c00c1e0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1261 return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}"; |
| 0 | 1262 } |
| 1263 [(set_attr "type" "mmxcvt") | |
|
55
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parents:
47
diff
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|
1264 (set_attr "length_immediate" "1") |
| 0 | 1265 (set_attr "mode" "DI")]) |
| 1266 | |
| 1267 (define_insn "mmx_pextrw" | |
| 1268 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1269 (zero_extend:SI | |
| 1270 (vec_select:HI | |
| 1271 (match_operand:V4HI 1 "register_operand" "y") | |
| 1272 (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))] | |
| 1273 "TARGET_SSE || TARGET_3DNOW_A" | |
| 1274 "pextrw\t{%2, %1, %0|%0, %1, %2}" | |
| 1275 [(set_attr "type" "mmxcvt") | |
|
55
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diff
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|
1276 (set_attr "length_immediate" "1") |
| 0 | 1277 (set_attr "mode" "DI")]) |
| 1278 | |
| 1279 (define_expand "mmx_pshufw" | |
| 1280 [(match_operand:V4HI 0 "register_operand" "") | |
| 1281 (match_operand:V4HI 1 "nonimmediate_operand" "") | |
| 1282 (match_operand:SI 2 "const_int_operand" "")] | |
| 1283 "TARGET_SSE || TARGET_3DNOW_A" | |
| 1284 { | |
| 1285 int mask = INTVAL (operands[2]); | |
| 1286 emit_insn (gen_mmx_pshufw_1 (operands[0], operands[1], | |
| 1287 GEN_INT ((mask >> 0) & 3), | |
| 1288 GEN_INT ((mask >> 2) & 3), | |
| 1289 GEN_INT ((mask >> 4) & 3), | |
| 1290 GEN_INT ((mask >> 6) & 3))); | |
| 1291 DONE; | |
| 1292 }) | |
| 1293 | |
| 1294 (define_insn "mmx_pshufw_1" | |
| 1295 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 1296 (vec_select:V4HI | |
| 1297 (match_operand:V4HI 1 "nonimmediate_operand" "ym") | |
| 1298 (parallel [(match_operand 2 "const_0_to_3_operand" "") | |
| 1299 (match_operand 3 "const_0_to_3_operand" "") | |
| 1300 (match_operand 4 "const_0_to_3_operand" "") | |
| 1301 (match_operand 5 "const_0_to_3_operand" "")])))] | |
| 1302 "TARGET_SSE || TARGET_3DNOW_A" | |
| 1303 { | |
| 1304 int mask = 0; | |
| 1305 mask |= INTVAL (operands[2]) << 0; | |
| 1306 mask |= INTVAL (operands[3]) << 2; | |
| 1307 mask |= INTVAL (operands[4]) << 4; | |
| 1308 mask |= INTVAL (operands[5]) << 6; | |
| 1309 operands[2] = GEN_INT (mask); | |
| 1310 | |
| 1311 return "pshufw\t{%2, %1, %0|%0, %1, %2}"; | |
| 1312 } | |
| 1313 [(set_attr "type" "mmxcvt") | |
|
55
77e2b8dfacca
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parents:
47
diff
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|
1314 (set_attr "length_immediate" "1") |
| 0 | 1315 (set_attr "mode" "DI")]) |
| 1316 | |
| 1317 (define_insn "mmx_pswapdv2si2" | |
| 1318 [(set (match_operand:V2SI 0 "register_operand" "=y") | |
| 1319 (vec_select:V2SI | |
| 1320 (match_operand:V2SI 1 "nonimmediate_operand" "ym") | |
| 1321 (parallel [(const_int 1) (const_int 0)])))] | |
| 1322 "TARGET_3DNOW_A" | |
| 1323 "pswapd\t{%1, %0|%0, %1}" | |
| 1324 [(set_attr "type" "mmxcvt") | |
|
55
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parents:
47
diff
changeset
|
1325 (set_attr "prefix_extra" "1") |
| 0 | 1326 (set_attr "mode" "DI")]) |
| 1327 | |
| 1328 (define_insn "*vec_dupv4hi" | |
| 1329 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 1330 (vec_duplicate:V4HI | |
| 1331 (truncate:HI | |
| 1332 (match_operand:SI 1 "register_operand" "0"))))] | |
| 1333 "TARGET_SSE || TARGET_3DNOW_A" | |
| 1334 "pshufw\t{$0, %0, %0|%0, %0, 0}" | |
| 1335 [(set_attr "type" "mmxcvt") | |
|
55
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parents:
47
diff
changeset
|
1336 (set_attr "length_immediate" "1") |
| 0 | 1337 (set_attr "mode" "DI")]) |
| 1338 | |
| 1339 (define_insn "*vec_dupv2si" | |
| 1340 [(set (match_operand:V2SI 0 "register_operand" "=y") | |
| 1341 (vec_duplicate:V2SI | |
| 1342 (match_operand:SI 1 "register_operand" "0")))] | |
| 1343 "TARGET_MMX" | |
| 1344 "punpckldq\t%0, %0" | |
| 1345 [(set_attr "type" "mmxcvt") | |
| 1346 (set_attr "mode" "DI")]) | |
| 1347 | |
| 1348 (define_insn "*mmx_concatv2si" | |
| 1349 [(set (match_operand:V2SI 0 "register_operand" "=y,y") | |
| 1350 (vec_concat:V2SI | |
| 1351 (match_operand:SI 1 "nonimmediate_operand" " 0,rm") | |
| 1352 (match_operand:SI 2 "vector_move_operand" "ym,C")))] | |
| 1353 "TARGET_MMX && !TARGET_SSE" | |
| 1354 "@ | |
| 1355 punpckldq\t{%2, %0|%0, %2} | |
| 1356 movd\t{%1, %0|%0, %1}" | |
| 1357 [(set_attr "type" "mmxcvt,mmxmov") | |
| 1358 (set_attr "mode" "DI")]) | |
| 1359 | |
| 1360 (define_expand "vec_setv2si" | |
| 1361 [(match_operand:V2SI 0 "register_operand" "") | |
| 1362 (match_operand:SI 1 "register_operand" "") | |
| 1363 (match_operand 2 "const_int_operand" "")] | |
| 1364 "TARGET_MMX" | |
| 1365 { | |
| 1366 ix86_expand_vector_set (false, operands[0], operands[1], | |
| 1367 INTVAL (operands[2])); | |
| 1368 DONE; | |
| 1369 }) | |
| 1370 | |
| 1371 ;; Avoid combining registers from different units in a single alternative, | |
| 1372 ;; see comment above inline_secondary_memory_needed function in i386.c | |
| 1373 (define_insn_and_split "*vec_extractv2si_0" | |
| 1374 [(set (match_operand:SI 0 "nonimmediate_operand" "=x,m,y, m,r") | |
| 1375 (vec_select:SI | |
| 1376 (match_operand:V2SI 1 "nonimmediate_operand" "xm,x,ym,y,m") | |
| 1377 (parallel [(const_int 0)])))] | |
| 1378 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" | |
| 1379 "#" | |
| 1380 "&& reload_completed" | |
| 1381 [(const_int 0)] | |
| 1382 { | |
| 1383 rtx op1 = operands[1]; | |
| 1384 if (REG_P (op1)) | |
| 1385 op1 = gen_rtx_REG (SImode, REGNO (op1)); | |
| 1386 else | |
| 1387 op1 = gen_lowpart (SImode, op1); | |
| 1388 emit_move_insn (operands[0], op1); | |
| 1389 DONE; | |
| 1390 }) | |
| 1391 | |
| 1392 ;; Avoid combining registers from different units in a single alternative, | |
| 1393 ;; see comment above inline_secondary_memory_needed function in i386.c | |
| 1394 (define_insn "*vec_extractv2si_1" | |
| 1395 [(set (match_operand:SI 0 "nonimmediate_operand" "=y,Y2,Y2,x,y,x,r") | |
| 1396 (vec_select:SI | |
| 1397 (match_operand:V2SI 1 "nonimmediate_operand" " 0,0 ,Y2,0,o,o,o") | |
| 1398 (parallel [(const_int 1)])))] | |
| 1399 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" | |
| 1400 "@ | |
| 1401 punpckhdq\t%0, %0 | |
| 1402 punpckhdq\t%0, %0 | |
| 1403 pshufd\t{$85, %1, %0|%0, %1, 85} | |
| 1404 unpckhps\t%0, %0 | |
| 1405 # | |
| 1406 # | |
| 1407 #" | |
| 1408 [(set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,mmxmov,ssemov,imov") | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1409 (set_attr "length_immediate" "*,*,1,*,*,*,*") |
| 0 | 1410 (set_attr "mode" "DI,TI,TI,V4SF,SI,SI,SI")]) |
| 1411 | |
| 1412 (define_split | |
| 1413 [(set (match_operand:SI 0 "register_operand" "") | |
| 1414 (vec_select:SI | |
| 1415 (match_operand:V2SI 1 "memory_operand" "") | |
| 1416 (parallel [(const_int 1)])))] | |
| 1417 "TARGET_MMX && reload_completed" | |
| 1418 [(const_int 0)] | |
| 1419 { | |
| 1420 operands[1] = adjust_address (operands[1], SImode, 4); | |
| 1421 emit_move_insn (operands[0], operands[1]); | |
| 1422 DONE; | |
| 1423 }) | |
| 1424 | |
| 1425 (define_expand "vec_extractv2si" | |
| 1426 [(match_operand:SI 0 "register_operand" "") | |
| 1427 (match_operand:V2SI 1 "register_operand" "") | |
| 1428 (match_operand 2 "const_int_operand" "")] | |
| 1429 "TARGET_MMX" | |
| 1430 { | |
| 1431 ix86_expand_vector_extract (false, operands[0], operands[1], | |
| 1432 INTVAL (operands[2])); | |
| 1433 DONE; | |
| 1434 }) | |
| 1435 | |
| 1436 (define_expand "vec_initv2si" | |
| 1437 [(match_operand:V2SI 0 "register_operand" "") | |
| 1438 (match_operand 1 "" "")] | |
| 1439 "TARGET_SSE" | |
| 1440 { | |
| 1441 ix86_expand_vector_init (false, operands[0], operands[1]); | |
| 1442 DONE; | |
| 1443 }) | |
| 1444 | |
| 1445 (define_expand "vec_setv4hi" | |
| 1446 [(match_operand:V4HI 0 "register_operand" "") | |
| 1447 (match_operand:HI 1 "register_operand" "") | |
| 1448 (match_operand 2 "const_int_operand" "")] | |
| 1449 "TARGET_MMX" | |
| 1450 { | |
| 1451 ix86_expand_vector_set (false, operands[0], operands[1], | |
| 1452 INTVAL (operands[2])); | |
| 1453 DONE; | |
| 1454 }) | |
| 1455 | |
| 1456 (define_expand "vec_extractv4hi" | |
| 1457 [(match_operand:HI 0 "register_operand" "") | |
| 1458 (match_operand:V4HI 1 "register_operand" "") | |
| 1459 (match_operand 2 "const_int_operand" "")] | |
| 1460 "TARGET_MMX" | |
| 1461 { | |
| 1462 ix86_expand_vector_extract (false, operands[0], operands[1], | |
| 1463 INTVAL (operands[2])); | |
| 1464 DONE; | |
| 1465 }) | |
| 1466 | |
| 1467 (define_expand "vec_initv4hi" | |
| 1468 [(match_operand:V4HI 0 "register_operand" "") | |
| 1469 (match_operand 1 "" "")] | |
| 1470 "TARGET_SSE" | |
| 1471 { | |
| 1472 ix86_expand_vector_init (false, operands[0], operands[1]); | |
| 1473 DONE; | |
| 1474 }) | |
| 1475 | |
| 1476 (define_expand "vec_setv8qi" | |
| 1477 [(match_operand:V8QI 0 "register_operand" "") | |
| 1478 (match_operand:QI 1 "register_operand" "") | |
| 1479 (match_operand 2 "const_int_operand" "")] | |
| 1480 "TARGET_MMX" | |
| 1481 { | |
| 1482 ix86_expand_vector_set (false, operands[0], operands[1], | |
| 1483 INTVAL (operands[2])); | |
| 1484 DONE; | |
| 1485 }) | |
| 1486 | |
| 1487 (define_expand "vec_extractv8qi" | |
| 1488 [(match_operand:QI 0 "register_operand" "") | |
| 1489 (match_operand:V8QI 1 "register_operand" "") | |
| 1490 (match_operand 2 "const_int_operand" "")] | |
| 1491 "TARGET_MMX" | |
| 1492 { | |
| 1493 ix86_expand_vector_extract (false, operands[0], operands[1], | |
| 1494 INTVAL (operands[2])); | |
| 1495 DONE; | |
| 1496 }) | |
| 1497 | |
| 1498 (define_expand "vec_initv8qi" | |
| 1499 [(match_operand:V8QI 0 "register_operand" "") | |
| 1500 (match_operand 1 "" "")] | |
| 1501 "TARGET_SSE" | |
| 1502 { | |
| 1503 ix86_expand_vector_init (false, operands[0], operands[1]); | |
| 1504 DONE; | |
| 1505 }) | |
| 1506 | |
| 1507 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 1508 ;; | |
| 1509 ;; Miscellaneous | |
| 1510 ;; | |
| 1511 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
| 1512 | |
| 1513 (define_expand "mmx_uavgv8qi3" | |
| 1514 [(set (match_operand:V8QI 0 "register_operand" "") | |
| 1515 (truncate:V8QI | |
| 1516 (lshiftrt:V8HI | |
| 1517 (plus:V8HI | |
| 1518 (plus:V8HI | |
| 1519 (zero_extend:V8HI | |
| 1520 (match_operand:V8QI 1 "nonimmediate_operand" "")) | |
| 1521 (zero_extend:V8HI | |
| 1522 (match_operand:V8QI 2 "nonimmediate_operand" ""))) | |
| 1523 (const_vector:V8HI [(const_int 1) (const_int 1) | |
| 1524 (const_int 1) (const_int 1) | |
| 1525 (const_int 1) (const_int 1) | |
| 1526 (const_int 1) (const_int 1)])) | |
| 1527 (const_int 1))))] | |
| 1528 "TARGET_SSE || TARGET_3DNOW" | |
| 1529 "ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);") | |
| 1530 | |
| 1531 (define_insn "*mmx_uavgv8qi3" | |
| 1532 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 1533 (truncate:V8QI | |
| 1534 (lshiftrt:V8HI | |
| 1535 (plus:V8HI | |
| 1536 (plus:V8HI | |
| 1537 (zero_extend:V8HI | |
| 1538 (match_operand:V8QI 1 "nonimmediate_operand" "%0")) | |
| 1539 (zero_extend:V8HI | |
| 1540 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))) | |
| 1541 (const_vector:V8HI [(const_int 1) (const_int 1) | |
| 1542 (const_int 1) (const_int 1) | |
| 1543 (const_int 1) (const_int 1) | |
| 1544 (const_int 1) (const_int 1)])) | |
| 1545 (const_int 1))))] | |
| 1546 "(TARGET_SSE || TARGET_3DNOW) | |
| 1547 && ix86_binary_operator_ok (PLUS, V8QImode, operands)" | |
| 1548 { | |
| 1549 /* These two instructions have the same operation, but their encoding | |
| 1550 is different. Prefer the one that is de facto standard. */ | |
| 1551 if (TARGET_SSE || TARGET_3DNOW_A) | |
| 1552 return "pavgb\t{%2, %0|%0, %2}"; | |
| 1553 else | |
| 1554 return "pavgusb\t{%2, %0|%0, %2}"; | |
| 1555 } | |
| 1556 [(set_attr "type" "mmxshft") | |
|
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
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|
1557 (set (attr "prefix_extra") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
47
diff
changeset
|
1558 (if_then_else |
|
77e2b8dfacca
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parents:
47
diff
changeset
|
1559 (eq (symbol_ref "(TARGET_SSE || TARGET_3DNOW_A)") (const_int 0)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
47
diff
changeset
|
1560 (const_string "1") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1561 (const_string "*"))) |
| 0 | 1562 (set_attr "mode" "DI")]) |
| 1563 | |
| 1564 (define_expand "mmx_uavgv4hi3" | |
| 1565 [(set (match_operand:V4HI 0 "register_operand" "") | |
| 1566 (truncate:V4HI | |
| 1567 (lshiftrt:V4SI | |
| 1568 (plus:V4SI | |
| 1569 (plus:V4SI | |
| 1570 (zero_extend:V4SI | |
| 1571 (match_operand:V4HI 1 "nonimmediate_operand" "")) | |
| 1572 (zero_extend:V4SI | |
| 1573 (match_operand:V4HI 2 "nonimmediate_operand" ""))) | |
| 1574 (const_vector:V4SI [(const_int 1) (const_int 1) | |
| 1575 (const_int 1) (const_int 1)])) | |
| 1576 (const_int 1))))] | |
| 1577 "TARGET_SSE || TARGET_3DNOW_A" | |
| 1578 "ix86_fixup_binary_operands_no_copy (PLUS, V4HImode, operands);") | |
| 1579 | |
| 1580 (define_insn "*mmx_uavgv4hi3" | |
| 1581 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 1582 (truncate:V4HI | |
| 1583 (lshiftrt:V4SI | |
| 1584 (plus:V4SI | |
| 1585 (plus:V4SI | |
| 1586 (zero_extend:V4SI | |
| 1587 (match_operand:V4HI 1 "nonimmediate_operand" "%0")) | |
| 1588 (zero_extend:V4SI | |
| 1589 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) | |
| 1590 (const_vector:V4SI [(const_int 1) (const_int 1) | |
| 1591 (const_int 1) (const_int 1)])) | |
| 1592 (const_int 1))))] | |
| 1593 "(TARGET_SSE || TARGET_3DNOW_A) | |
| 1594 && ix86_binary_operator_ok (PLUS, V4HImode, operands)" | |
| 1595 "pavgw\t{%2, %0|%0, %2}" | |
| 1596 [(set_attr "type" "mmxshft") | |
| 1597 (set_attr "mode" "DI")]) | |
| 1598 | |
| 1599 (define_insn "mmx_psadbw" | |
| 1600 [(set (match_operand:V1DI 0 "register_operand" "=y") | |
| 1601 (unspec:V1DI [(match_operand:V8QI 1 "register_operand" "0") | |
| 1602 (match_operand:V8QI 2 "nonimmediate_operand" "ym")] | |
| 1603 UNSPEC_PSADBW))] | |
| 1604 "TARGET_SSE || TARGET_3DNOW_A" | |
| 1605 "psadbw\t{%2, %0|%0, %2}" | |
| 1606 [(set_attr "type" "mmxshft") | |
| 1607 (set_attr "mode" "DI")]) | |
| 1608 | |
| 1609 (define_insn "mmx_pmovmskb" | |
| 1610 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1611 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] | |
| 1612 UNSPEC_MOVMSK))] | |
| 1613 "TARGET_SSE || TARGET_3DNOW_A" | |
| 1614 "pmovmskb\t{%1, %0|%0, %1}" | |
| 1615 [(set_attr "type" "mmxcvt") | |
| 1616 (set_attr "mode" "DI")]) | |
| 1617 | |
| 1618 (define_expand "mmx_maskmovq" | |
| 1619 [(set (match_operand:V8QI 0 "memory_operand" "") | |
| 1620 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "") | |
| 1621 (match_operand:V8QI 2 "register_operand" "") | |
| 1622 (match_dup 0)] | |
| 1623 UNSPEC_MASKMOV))] | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
63
diff
changeset
|
1624 "TARGET_SSE || TARGET_3DNOW_A") |
| 0 | 1625 |
| 1626 (define_insn "*mmx_maskmovq" | |
| 1627 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D")) | |
| 1628 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") | |
| 1629 (match_operand:V8QI 2 "register_operand" "y") | |
| 1630 (mem:V8QI (match_dup 0))] | |
| 1631 UNSPEC_MASKMOV))] | |
| 1632 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT" | |
| 1633 ;; @@@ check ordering of operands in intel/nonintel syntax | |
| 1634 "maskmovq\t{%2, %1|%1, %2}" | |
| 1635 [(set_attr "type" "mmxcvt") | |
| 1636 (set_attr "mode" "DI")]) | |
| 1637 | |
| 1638 (define_insn "*mmx_maskmovq_rex" | |
| 1639 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D")) | |
| 1640 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") | |
| 1641 (match_operand:V8QI 2 "register_operand" "y") | |
| 1642 (mem:V8QI (match_dup 0))] | |
| 1643 UNSPEC_MASKMOV))] | |
| 1644 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT" | |
| 1645 ;; @@@ check ordering of operands in intel/nonintel syntax | |
| 1646 "maskmovq\t{%2, %1|%1, %2}" | |
| 1647 [(set_attr "type" "mmxcvt") | |
| 1648 (set_attr "mode" "DI")]) | |
| 1649 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
47
diff
changeset
|
1650 (define_expand "mmx_emms" |
|
77e2b8dfacca
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parents:
47
diff
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|
1651 [(match_par_dup 0 [(const_int 0)])] |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1652 "TARGET_MMX" |
|
77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1653 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1654 int regno; |
|
77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1655 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1656 operands[0] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (17)); |
|
77e2b8dfacca
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parents:
47
diff
changeset
|
1657 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1658 XVECEXP (operands[0], 0, 0) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
47
diff
changeset
|
1659 = gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, const0_rtx), |
|
77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1660 UNSPECV_EMMS); |
|
77e2b8dfacca
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parents:
47
diff
changeset
|
1661 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1662 for (regno = 0; regno < 8; regno++) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
47
diff
changeset
|
1663 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1664 XVECEXP (operands[0], 0, regno + 1) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1665 = gen_rtx_CLOBBER (VOIDmode, |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
47
diff
changeset
|
1666 gen_rtx_REG (XFmode, FIRST_STACK_REG + regno)); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
47
diff
changeset
|
1667 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1668 XVECEXP (operands[0], 0, regno + 9) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1669 = gen_rtx_CLOBBER (VOIDmode, |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1670 gen_rtx_REG (DImode, FIRST_MMX_REG + regno)); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1671 } |
|
77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1672 }) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1673 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1674 (define_insn "*mmx_emms" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1675 [(match_parallel 0 "emms_operation" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1676 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)])] |
| 0 | 1677 "TARGET_MMX" |
| 1678 "emms" | |
| 1679 [(set_attr "type" "mmx") | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
47
diff
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|
1680 (set_attr "modrm" "0") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1681 (set_attr "memory" "none")]) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1682 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1683 (define_expand "mmx_femms" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1684 [(match_par_dup 0 [(const_int 0)])] |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1685 "TARGET_3DNOW" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1686 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1687 int regno; |
|
77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1688 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1689 operands[0] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (17)); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1690 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1691 XVECEXP (operands[0], 0, 0) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1692 = gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, const0_rtx), |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1693 UNSPECV_FEMMS); |
| 0 | 1694 |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1695 for (regno = 0; regno < 8; regno++) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1696 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1697 XVECEXP (operands[0], 0, regno + 1) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1698 = gen_rtx_CLOBBER (VOIDmode, |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1699 gen_rtx_REG (XFmode, FIRST_STACK_REG + regno)); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1700 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1701 XVECEXP (operands[0], 0, regno + 9) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1702 = gen_rtx_CLOBBER (VOIDmode, |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1703 gen_rtx_REG (DImode, FIRST_MMX_REG + regno)); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1704 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1705 }) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1706 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1707 (define_insn "*mmx_femms" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1708 [(match_parallel 0 "emms_operation" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
47
diff
changeset
|
1709 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)])] |
| 0 | 1710 "TARGET_3DNOW" |
| 1711 "femms" | |
| 1712 [(set_attr "type" "mmx") | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
47
diff
changeset
|
1713 (set_attr "modrm" "0") |
| 0 | 1714 (set_attr "memory" "none")]) |