Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/m32r/m32r.h @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | 77e2b8dfacca |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 /* Definitions of target machine for GNU compiler, Renesas M32R cpu. |
| 2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
3 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. |
| 0 | 4 |
| 5 This file is part of GCC. | |
| 6 | |
| 7 GCC is free software; you can redistribute it and/or modify it | |
| 8 under the terms of the GNU General Public License as published | |
| 9 by the Free Software Foundation; either version 3, or (at your | |
| 10 option) any later version. | |
| 11 | |
| 12 GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 15 License for more details. | |
| 16 | |
| 17 You should have received a copy of the GNU General Public License | |
| 18 along with GCC; see the file COPYING3. If not see | |
| 19 <http://www.gnu.org/licenses/>. */ | |
| 20 | |
| 21 /* Things to do: | |
| 22 - longlong.h? | |
| 23 */ | |
| 24 | |
| 25 #undef SIZE_TYPE | |
| 26 #undef PTRDIFF_TYPE | |
| 27 #undef WCHAR_TYPE | |
| 28 #undef WCHAR_TYPE_SIZE | |
| 29 #undef TARGET_VERSION | |
| 30 #undef CPP_SPEC | |
| 31 #undef ASM_SPEC | |
| 32 #undef LINK_SPEC | |
| 33 #undef STARTFILE_SPEC | |
| 34 #undef ENDFILE_SPEC | |
| 35 | |
| 36 #undef ASM_APP_ON | |
| 37 #undef ASM_APP_OFF | |
| 38 | |
| 39 | |
| 40 /* M32R/X overrides. */ | |
| 41 /* Print subsidiary information on the compiler version in use. */ | |
| 42 #define TARGET_VERSION fprintf (stderr, " (m32r/x/2)"); | |
| 43 | |
| 44 /* Additional flags for the preprocessor. */ | |
| 45 #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \ | |
| 46 %{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \ | |
| 47 %{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \ | |
| 48 " | |
| 49 | |
| 50 /* Assembler switches. */ | |
| 51 #define ASM_CPU_SPEC \ | |
| 52 "%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts" | |
| 53 | |
| 54 /* Use m32rx specific crt0/crtinit/crtfini files. */ | |
| 55 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}" | |
| 56 #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}" | |
| 57 | |
| 58 /* Define this macro as a C expression for the initializer of an array of | |
| 59 strings to tell the driver program which options are defaults for this | |
| 60 target and thus do not need to be handled specially when using | |
| 61 `MULTILIB_OPTIONS'. */ | |
| 62 #define SUBTARGET_MULTILIB_DEFAULTS , "m32r" | |
| 63 | |
| 64 /* Number of additional registers the subtarget defines. */ | |
| 65 #define SUBTARGET_NUM_REGISTERS 1 | |
| 66 | |
| 67 /* 1 for registers that cannot be allocated. */ | |
| 68 #define SUBTARGET_FIXED_REGISTERS , 1 | |
| 69 | |
| 70 /* 1 for registers that are not available across function calls. */ | |
| 71 #define SUBTARGET_CALL_USED_REGISTERS , 1 | |
| 72 | |
| 73 /* Order to allocate model specific registers. */ | |
| 74 #define SUBTARGET_REG_ALLOC_ORDER , 19 | |
| 75 | |
| 76 /* Registers which are accumulators. */ | |
| 77 #define SUBTARGET_REG_CLASS_ACCUM 0x80000 | |
| 78 | |
| 79 /* All registers added. */ | |
| 80 #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM | |
| 81 | |
| 82 /* Additional accumulator registers. */ | |
| 83 #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19) | |
| 84 | |
| 85 /* Define additional register names. */ | |
| 86 #define SUBTARGET_REGISTER_NAMES , "a1" | |
| 87 /* end M32R/X overrides. */ | |
| 88 | |
| 89 /* Print subsidiary information on the compiler version in use. */ | |
| 90 #ifndef TARGET_VERSION | |
| 91 #define TARGET_VERSION fprintf (stderr, " (m32r)") | |
| 92 #endif | |
| 93 | |
| 94 /* Names to predefine in the preprocessor for this target machine. */ | |
| 95 /* __M32R__ is defined by the existing compiler so we use that. */ | |
| 96 #define TARGET_CPU_CPP_BUILTINS() \ | |
| 97 do \ | |
| 98 { \ | |
| 99 builtin_define ("__M32R__"); \ | |
| 100 builtin_define ("__m32r__"); \ | |
| 101 builtin_assert ("cpu=m32r"); \ | |
| 102 builtin_assert ("machine=m32r"); \ | |
| 103 builtin_define (TARGET_BIG_ENDIAN \ | |
| 104 ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \ | |
| 105 } \ | |
| 106 while (0) | |
| 107 | |
| 108 /* This macro defines names of additional specifications to put in the specs | |
| 109 that can be used in various specifications like CC1_SPEC. Its definition | |
| 110 is an initializer with a subgrouping for each command option. | |
| 111 | |
| 112 Each subgrouping contains a string constant, that defines the | |
| 113 specification name, and a string constant that used by the GCC driver | |
| 114 program. | |
| 115 | |
| 116 Do not define this macro if it does not need to do anything. */ | |
| 117 | |
| 118 #ifndef SUBTARGET_EXTRA_SPECS | |
| 119 #define SUBTARGET_EXTRA_SPECS | |
| 120 #endif | |
| 121 | |
| 122 #ifndef ASM_CPU_SPEC | |
| 123 #define ASM_CPU_SPEC "" | |
| 124 #endif | |
| 125 | |
| 126 #ifndef CPP_CPU_SPEC | |
| 127 #define CPP_CPU_SPEC "" | |
| 128 #endif | |
| 129 | |
| 130 #ifndef CC1_CPU_SPEC | |
| 131 #define CC1_CPU_SPEC "" | |
| 132 #endif | |
| 133 | |
| 134 #ifndef LINK_CPU_SPEC | |
| 135 #define LINK_CPU_SPEC "" | |
| 136 #endif | |
| 137 | |
| 138 #ifndef STARTFILE_CPU_SPEC | |
| 139 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s" | |
| 140 #endif | |
| 141 | |
| 142 #ifndef ENDFILE_CPU_SPEC | |
| 143 #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s" | |
| 144 #endif | |
| 145 | |
| 146 #ifndef RELAX_SPEC | |
| 147 #if 0 /* Not supported yet. */ | |
| 148 #define RELAX_SPEC "%{mrelax:-relax}" | |
| 149 #else | |
| 150 #define RELAX_SPEC "" | |
| 151 #endif | |
| 152 #endif | |
| 153 | |
| 154 #define EXTRA_SPECS \ | |
| 155 { "asm_cpu", ASM_CPU_SPEC }, \ | |
| 156 { "cpp_cpu", CPP_CPU_SPEC }, \ | |
| 157 { "cc1_cpu", CC1_CPU_SPEC }, \ | |
| 158 { "link_cpu", LINK_CPU_SPEC }, \ | |
| 159 { "startfile_cpu", STARTFILE_CPU_SPEC }, \ | |
| 160 { "endfile_cpu", ENDFILE_CPU_SPEC }, \ | |
| 161 { "relax", RELAX_SPEC }, \ | |
| 162 SUBTARGET_EXTRA_SPECS | |
| 163 | |
| 164 #define CPP_SPEC "%(cpp_cpu)" | |
| 165 | |
| 166 #undef CC1_SPEC | |
| 167 #define CC1_SPEC "%{G*} %(cc1_cpu)" | |
| 168 | |
| 169 /* Options to pass on to the assembler. */ | |
| 170 #undef ASM_SPEC | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
171 #define ASM_SPEC "%(asm_cpu) %(relax) %{fpic|fpie:-K PIC} %{fPIC|fPIE:-K PIC}" |
| 0 | 172 |
| 173 #define LINK_SPEC "%{v} %(link_cpu) %(relax)" | |
| 174 | |
| 175 #undef STARTFILE_SPEC | |
| 176 #define STARTFILE_SPEC "%(startfile_cpu)" | |
| 177 | |
| 178 #undef ENDFILE_SPEC | |
| 179 #define ENDFILE_SPEC "%(endfile_cpu)" | |
| 180 | |
| 181 #undef LIB_SPEC | |
| 182 | |
| 183 /* Run-time compilation parameters selecting different hardware subsets. */ | |
| 184 | |
| 185 #define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2) | |
| 186 | |
| 187 #ifndef TARGET_LITTLE_ENDIAN | |
| 188 #define TARGET_LITTLE_ENDIAN 0 | |
| 189 #endif | |
| 190 #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) | |
| 191 | |
| 192 /* This defaults us to m32r. */ | |
| 193 #ifndef TARGET_CPU_DEFAULT | |
| 194 #define TARGET_CPU_DEFAULT 0 | |
| 195 #endif | |
| 196 | |
| 197 /* Code Models | |
| 198 | |
| 199 Code models are used to select between two choices of two separate | |
| 200 possibilities (address space size, call insn to use): | |
| 201 | |
| 202 small: addresses use 24 bits, use bl to make calls | |
| 203 medium: addresses use 32 bits, use bl to make calls (*1) | |
| 204 large: addresses use 32 bits, use seth/add3/jl to make calls (*2) | |
| 205 | |
| 206 The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but | |
| 207 using this one doesn't make much sense. | |
| 208 | |
| 209 (*1) The linker may eventually be able to relax seth/add3 -> ld24. | |
| 210 (*2) The linker may eventually be able to relax seth/add3/jl -> bl. | |
| 211 | |
| 212 Internally these are recorded as TARGET_ADDR{24,32} and | |
| 213 TARGET_CALL{26,32}. | |
| 214 | |
| 215 The __model__ attribute can be used to select the code model to use when | |
| 216 accessing particular objects. */ | |
| 217 | |
| 218 enum m32r_model { M32R_MODEL_SMALL, M32R_MODEL_MEDIUM, M32R_MODEL_LARGE }; | |
| 219 | |
| 220 extern enum m32r_model m32r_model; | |
| 221 #define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL) | |
| 222 #define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM) | |
| 223 #define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE) | |
| 224 #define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL) | |
| 225 #define TARGET_ADDR32 (! TARGET_ADDR24) | |
| 226 #define TARGET_CALL26 (! TARGET_CALL32) | |
| 227 #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE) | |
| 228 | |
| 229 /* The default is the small model. */ | |
| 230 #ifndef M32R_MODEL_DEFAULT | |
| 231 #define M32R_MODEL_DEFAULT M32R_MODEL_SMALL | |
| 232 #endif | |
| 233 | |
| 234 /* Small Data Area | |
| 235 | |
| 236 The SDA consists of sections .sdata, .sbss, and .scommon. | |
| 237 .scommon isn't a real section, symbols in it have their section index | |
| 238 set to SHN_M32R_SCOMMON, though support for it exists in the linker script. | |
| 239 | |
| 240 Two switches control the SDA: | |
| 241 | |
| 242 -G NNN - specifies the maximum size of variable to go in the SDA | |
| 243 | |
| 244 -msdata=foo - specifies how such variables are handled | |
| 245 | |
| 246 -msdata=none - small data area is disabled | |
| 247 | |
| 248 -msdata=sdata - small data goes in the SDA, special code isn't | |
| 249 generated to use it, and special relocs aren't | |
| 250 generated | |
| 251 | |
| 252 -msdata=use - small data goes in the SDA, special code is generated | |
| 253 to use the SDA and special relocs are generated | |
| 254 | |
| 255 The SDA is not multilib'd, it isn't necessary. | |
| 256 MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd | |
| 257 libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use | |
| 258 -msdata=use will successfully link with them (references in header files | |
| 259 will cause the compiler to emit code that refers to library objects in | |
| 260 .data). ??? There can be a problem if the user passes a -G value greater | |
| 261 than the default and a library object in a header file is that size. | |
| 262 The default is 8 so this should be rare - if it occurs the user | |
| 263 is required to rebuild the libraries or use a smaller value for -G. */ | |
| 264 | |
| 265 /* Maximum size of variables that go in .sdata/.sbss. | |
| 266 The -msdata=foo switch also controls how small variables are handled. */ | |
| 267 #ifndef SDATA_DEFAULT_SIZE | |
| 268 #define SDATA_DEFAULT_SIZE 8 | |
| 269 #endif | |
| 270 | |
| 271 enum m32r_sdata { M32R_SDATA_NONE, M32R_SDATA_SDATA, M32R_SDATA_USE }; | |
| 272 | |
| 273 extern enum m32r_sdata m32r_sdata; | |
| 274 #define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE) | |
| 275 #define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA) | |
| 276 #define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE) | |
| 277 | |
| 278 /* Default is to disable the SDA | |
| 279 [for upward compatibility with previous toolchains]. */ | |
| 280 #ifndef M32R_SDATA_DEFAULT | |
| 281 #define M32R_SDATA_DEFAULT M32R_SDATA_NONE | |
| 282 #endif | |
| 283 | |
| 284 /* Define this macro as a C expression for the initializer of an array of | |
| 285 strings to tell the driver program which options are defaults for this | |
| 286 target and thus do not need to be handled specially when using | |
| 287 `MULTILIB_OPTIONS'. */ | |
| 288 #ifndef SUBTARGET_MULTILIB_DEFAULTS | |
| 289 #define SUBTARGET_MULTILIB_DEFAULTS | |
| 290 #endif | |
| 291 | |
| 292 #ifndef MULTILIB_DEFAULTS | |
| 293 #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS } | |
| 294 #endif | |
| 295 | |
| 296 #ifndef SUBTARGET_OVERRIDE_OPTIONS | |
| 297 #define SUBTARGET_OVERRIDE_OPTIONS | |
| 298 #endif | |
| 299 | |
| 300 /* Target machine storage layout. */ | |
| 301 | |
| 302 /* Define this if most significant bit is lowest numbered | |
| 303 in instructions that operate on numbered bit-fields. */ | |
| 304 #define BITS_BIG_ENDIAN 1 | |
| 305 | |
| 306 /* Define this if most significant byte of a word is the lowest numbered. */ | |
| 307 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) | |
| 308 | |
| 309 /* Define this if most significant word of a multiword number is the lowest | |
| 310 numbered. */ | |
| 311 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) | |
| 312 | |
| 313 /* Width of a word, in units (bytes). */ | |
| 314 #define UNITS_PER_WORD 4 | |
| 315 | |
| 316 /* Define this macro if it is advisable to hold scalars in registers | |
| 317 in a wider mode than that declared by the program. In such cases, | |
| 318 the value is constrained to be within the bounds of the declared | |
| 319 type, but kept valid in the wider mode. The signedness of the | |
| 320 extension may differ from that of the type. */ | |
| 321 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
| 322 if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
| 323 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
| 324 { \ | |
| 325 (MODE) = SImode; \ | |
| 326 } | |
| 327 | |
| 328 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
| 329 #define PARM_BOUNDARY 32 | |
| 330 | |
| 331 /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
| 332 #define STACK_BOUNDARY 32 | |
| 333 | |
| 334 /* ALIGN FRAMES on word boundaries */ | |
| 335 #define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3) | |
| 336 | |
| 337 /* Allocation boundary (in *bits*) for the code of a function. */ | |
| 338 #define FUNCTION_BOUNDARY 32 | |
| 339 | |
| 340 /* Alignment of field after `int : 0' in a structure. */ | |
| 341 #define EMPTY_FIELD_BOUNDARY 32 | |
| 342 | |
| 343 /* Every structure's size must be a multiple of this. */ | |
| 344 #define STRUCTURE_SIZE_BOUNDARY 8 | |
| 345 | |
| 346 /* A bit-field declared as `int' forces `int' alignment for the struct. */ | |
| 347 #define PCC_BITFIELD_TYPE_MATTERS 1 | |
| 348 | |
| 349 /* No data type wants to be aligned rounder than this. */ | |
| 350 #define BIGGEST_ALIGNMENT 32 | |
| 351 | |
| 352 /* The best alignment to use in cases where we have a choice. */ | |
| 353 #define FASTEST_ALIGNMENT 32 | |
| 354 | |
| 355 /* Make strings word-aligned so strcpy from constants will be faster. */ | |
| 356 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
| 357 ((TREE_CODE (EXP) == STRING_CST \ | |
| 358 && (ALIGN) < FASTEST_ALIGNMENT) \ | |
| 359 ? FASTEST_ALIGNMENT : (ALIGN)) | |
| 360 | |
| 361 /* Make arrays of chars word-aligned for the same reasons. */ | |
| 362 #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
| 363 (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
| 364 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
| 365 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
| 366 | |
| 367 /* Set this nonzero if move instructions will actually fail to work | |
| 368 when given unaligned data. */ | |
| 369 #define STRICT_ALIGNMENT 1 | |
| 370 | |
| 371 /* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */ | |
| 372 #define LABEL_ALIGN(insn) 2 | |
| 373 | |
| 374 /* Layout of source language data types. */ | |
| 375 | |
| 376 #define SHORT_TYPE_SIZE 16 | |
| 377 #define INT_TYPE_SIZE 32 | |
| 378 #define LONG_TYPE_SIZE 32 | |
| 379 #define LONG_LONG_TYPE_SIZE 64 | |
| 380 #define FLOAT_TYPE_SIZE 32 | |
| 381 #define DOUBLE_TYPE_SIZE 64 | |
| 382 #define LONG_DOUBLE_TYPE_SIZE 64 | |
| 383 | |
| 384 /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
| 385 #define DEFAULT_SIGNED_CHAR 1 | |
| 386 | |
| 387 #define SIZE_TYPE "long unsigned int" | |
| 388 #define PTRDIFF_TYPE "long int" | |
| 389 #define WCHAR_TYPE "short unsigned int" | |
| 390 #define WCHAR_TYPE_SIZE 16 | |
| 391 | |
| 392 /* Standard register usage. */ | |
| 393 | |
| 394 /* Number of actual hardware registers. | |
| 395 The hardware registers are assigned numbers for the compiler | |
| 396 from 0 to just below FIRST_PSEUDO_REGISTER. | |
| 397 All registers that the compiler knows about must be given numbers, | |
| 398 even those that are not normally considered general registers. */ | |
| 399 | |
| 400 #define M32R_NUM_REGISTERS 19 | |
| 401 | |
| 402 #ifndef SUBTARGET_NUM_REGISTERS | |
| 403 #define SUBTARGET_NUM_REGISTERS 0 | |
| 404 #endif | |
| 405 | |
| 406 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS) | |
| 407 | |
| 408 /* 1 for registers that have pervasive standard uses | |
| 409 and are not available for the register allocator. | |
| 410 | |
| 411 0-3 - arguments/results | |
| 412 4-5 - call used [4 is used as a tmp during prologue/epilogue generation] | |
| 413 6 - call used, gptmp | |
| 414 7 - call used, static chain pointer | |
| 415 8-11 - call saved | |
| 416 12 - call saved [reserved for global pointer] | |
| 417 13 - frame pointer | |
| 418 14 - subroutine link register | |
| 419 15 - stack pointer | |
| 420 16 - arg pointer | |
| 421 17 - carry flag | |
| 422 18 - accumulator | |
| 423 19 - accumulator 1 in the m32r/x | |
| 424 By default, the extension registers are not available. */ | |
| 425 | |
| 426 #ifndef SUBTARGET_FIXED_REGISTERS | |
| 427 #define SUBTARGET_FIXED_REGISTERS | |
| 428 #endif | |
| 429 | |
| 430 #define FIXED_REGISTERS \ | |
| 431 { \ | |
| 432 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 433 0, 0, 0, 0, 0, 0, 0, 1, \ | |
| 434 1, 1, 1 \ | |
| 435 SUBTARGET_FIXED_REGISTERS \ | |
| 436 } | |
| 437 | |
| 438 /* 1 for registers not available across function calls. | |
| 439 These must include the FIXED_REGISTERS and also any | |
| 440 registers that can be used without being saved. | |
| 441 The latter must include the registers where values are returned | |
| 442 and the register where structure-value addresses are passed. | |
| 443 Aside from that, you can include as many other registers as you like. */ | |
| 444 | |
| 445 #ifndef SUBTARGET_CALL_USED_REGISTERS | |
| 446 #define SUBTARGET_CALL_USED_REGISTERS | |
| 447 #endif | |
| 448 | |
| 449 #define CALL_USED_REGISTERS \ | |
| 450 { \ | |
| 451 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 452 0, 0, 0, 0, 0, 0, 1, 1, \ | |
| 453 1, 1, 1 \ | |
| 454 SUBTARGET_CALL_USED_REGISTERS \ | |
| 455 } | |
| 456 | |
| 457 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS | |
| 458 | |
| 459 /* If defined, an initializer for a vector of integers, containing the | |
| 460 numbers of hard registers in the order in which GCC should | |
| 461 prefer to use them (from most preferred to least). */ | |
| 462 | |
| 463 #ifndef SUBTARGET_REG_ALLOC_ORDER | |
| 464 #define SUBTARGET_REG_ALLOC_ORDER | |
| 465 #endif | |
| 466 | |
| 467 #if 1 /* Better for int code. */ | |
| 468 #define REG_ALLOC_ORDER \ | |
| 469 { \ | |
| 470 4, 5, 6, 7, 2, 3, 8, 9, 10, \ | |
| 471 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \ | |
| 472 SUBTARGET_REG_ALLOC_ORDER \ | |
| 473 } | |
| 474 | |
| 475 #else /* Better for fp code at expense of int code. */ | |
| 476 #define REG_ALLOC_ORDER \ | |
| 477 { \ | |
| 478 0, 1, 2, 3, 4, 5, 6, 7, 8, \ | |
| 479 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \ | |
| 480 SUBTARGET_REG_ALLOC_ORDER \ | |
| 481 } | |
| 482 #endif | |
| 483 | |
| 484 /* Return number of consecutive hard regs needed starting at reg REGNO | |
| 485 to hold something of mode MODE. | |
| 486 This is ordinarily the length in words of a value of mode MODE | |
| 487 but can be less for certain modes in special long registers. */ | |
| 488 #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
| 489 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
| 490 | |
| 491 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ | |
| 492 extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER]; | |
| 493 extern unsigned int m32r_mode_class[]; | |
| 494 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
| 495 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0) | |
| 496 | |
| 497 /* A C expression that is nonzero if it is desirable to choose | |
| 498 register allocation so as to avoid move instructions between a | |
| 499 value of mode MODE1 and a value of mode MODE2. | |
| 500 | |
| 501 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, | |
| 502 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, | |
| 503 MODE2)' must be zero. */ | |
| 504 | |
| 505 /* Tie QI/HI/SI modes together. */ | |
| 506 #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
| 507 ( GET_MODE_CLASS (MODE1) == MODE_INT \ | |
| 508 && GET_MODE_CLASS (MODE2) == MODE_INT \ | |
| 509 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \ | |
| 510 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD) | |
| 511 | |
| 512 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ | |
| 513 m32r_hard_regno_rename_ok (OLD_REG, NEW_REG) | |
| 514 | |
| 515 /* Register classes and constants. */ | |
| 516 | |
| 517 /* Define the classes of registers for register constraints in the | |
| 518 machine description. Also define ranges of constants. | |
| 519 | |
| 520 One of the classes must always be named ALL_REGS and include all hard regs. | |
| 521 If there is more than one class, another class must be named NO_REGS | |
| 522 and contain no registers. | |
| 523 | |
| 524 The name GENERAL_REGS must be the name of a class (or an alias for | |
| 525 another name such as ALL_REGS). This is the class of registers | |
| 526 that is allowed by "g" or "r" in a register constraint. | |
| 527 Also, registers outside this class are allocated only when | |
| 528 instructions express preferences for them. | |
| 529 | |
| 530 The classes must be numbered in nondecreasing order; that is, | |
| 531 a larger-numbered class must never be contained completely | |
| 532 in a smaller-numbered class. | |
| 533 | |
| 534 For any two classes, it is very desirable that there be another | |
| 535 class that represents their union. | |
| 536 | |
| 537 It is important that any condition codes have class NO_REGS. | |
| 538 See `register_operand'. */ | |
| 539 | |
| 540 enum reg_class | |
| 541 { | |
| 542 NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES | |
| 543 }; | |
| 544 | |
| 545 #define IRA_COVER_CLASSES \ | |
| 546 { \ | |
| 547 ACCUM_REGS, GENERAL_REGS, LIM_REG_CLASSES \ | |
| 548 } | |
| 549 | |
| 550 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) | |
| 551 | |
| 552 /* Give names of register classes as strings for dump file. */ | |
| 553 #define REG_CLASS_NAMES \ | |
| 554 { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" } | |
| 555 | |
| 556 /* Define which registers fit in which classes. | |
| 557 This is an initializer for a vector of HARD_REG_SET | |
| 558 of length N_REG_CLASSES. */ | |
| 559 | |
| 560 #ifndef SUBTARGET_REG_CLASS_CARRY | |
| 561 #define SUBTARGET_REG_CLASS_CARRY 0 | |
| 562 #endif | |
| 563 | |
| 564 #ifndef SUBTARGET_REG_CLASS_ACCUM | |
| 565 #define SUBTARGET_REG_CLASS_ACCUM 0 | |
| 566 #endif | |
| 567 | |
| 568 #ifndef SUBTARGET_REG_CLASS_GENERAL | |
| 569 #define SUBTARGET_REG_CLASS_GENERAL 0 | |
| 570 #endif | |
| 571 | |
| 572 #ifndef SUBTARGET_REG_CLASS_ALL | |
| 573 #define SUBTARGET_REG_CLASS_ALL 0 | |
| 574 #endif | |
| 575 | |
| 576 #define REG_CLASS_CONTENTS \ | |
| 577 { \ | |
| 578 { 0x00000 }, \ | |
| 579 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \ | |
| 580 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \ | |
| 581 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \ | |
| 582 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \ | |
| 583 } | |
| 584 | |
| 585 /* The same information, inverted: | |
| 586 Return the class number of the smallest class containing | |
| 587 reg number REGNO. This could be a conditional expression | |
| 588 or could index an array. */ | |
| 589 extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER]; | |
| 590 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO]) | |
| 591 | |
| 592 /* The class value for index registers, and the one for base regs. */ | |
| 593 #define INDEX_REG_CLASS GENERAL_REGS | |
| 594 #define BASE_REG_CLASS GENERAL_REGS | |
| 595 | |
| 596 /* These assume that REGNO is a hard or pseudo reg number. | |
| 597 They give nonzero only if REGNO is a hard reg of the suitable class | |
| 598 or a pseudo reg currently allocated to a suitable hard reg. | |
| 599 Since they use reg_renumber, they are safe only once reg_renumber | |
| 600 has been allocated, which happens in local-alloc.c. */ | |
| 601 #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
| 602 ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
| 603 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \ | |
| 604 : GPR_P (reg_renumber[REGNO])) | |
| 605 | |
| 606 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO) | |
| 607 | |
| 608 /* Return the maximum number of consecutive registers | |
| 609 needed to represent mode MODE in a register of class CLASS. */ | |
| 610 #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
| 611 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
| 612 | |
| 613 /* Return true if a value is inside a range. */ | |
| 614 #define IN_RANGE_P(VALUE, LOW, HIGH) \ | |
| 615 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \ | |
| 616 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW)))) | |
| 617 | |
| 618 /* Some range macros. */ | |
| 619 #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff) | |
| 620 #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000) | |
| 621 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff) | |
| 622 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff) | |
| 623 | |
| 624 /* Stack layout and stack pointer usage. */ | |
| 625 | |
| 626 /* Define this macro if pushing a word onto the stack moves the stack | |
| 627 pointer to a smaller address. */ | |
| 628 #define STACK_GROWS_DOWNWARD | |
| 629 | |
| 630 /* Offset from frame pointer to start allocating local variables at. | |
| 631 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
| 632 first local allocated. Otherwise, it is the offset to the BEGINNING | |
| 633 of the first local allocated. */ | |
| 634 /* The frame pointer points at the same place as the stack pointer, except if | |
| 635 alloca has been called. */ | |
| 636 #define STARTING_FRAME_OFFSET \ | |
| 637 M32R_STACK_ALIGN (crtl->outgoing_args_size) | |
| 638 | |
| 639 /* Offset from the stack pointer register to the first location at which | |
| 640 outgoing arguments are placed. */ | |
| 641 #define STACK_POINTER_OFFSET 0 | |
| 642 | |
| 643 /* Offset of first parameter from the argument pointer register value. */ | |
| 644 #define FIRST_PARM_OFFSET(FNDECL) 0 | |
| 645 | |
| 646 /* Register to use for pushing function arguments. */ | |
| 647 #define STACK_POINTER_REGNUM 15 | |
| 648 | |
| 649 /* Base register for access to local variables of the function. */ | |
| 650 #define FRAME_POINTER_REGNUM 13 | |
| 651 | |
| 652 /* Base register for access to arguments of the function. */ | |
| 653 #define ARG_POINTER_REGNUM 16 | |
| 654 | |
| 655 /* Register in which static-chain is passed to a function. | |
| 656 This must not be a register used by the prologue. */ | |
| 657 #define STATIC_CHAIN_REGNUM 7 | |
| 658 | |
| 659 /* These aren't official macros. */ | |
| 660 #define PROLOGUE_TMP_REGNUM 4 | |
| 661 #define RETURN_ADDR_REGNUM 14 | |
| 662 /* #define GP_REGNUM 12 */ | |
| 663 #define CARRY_REGNUM 17 | |
| 664 #define ACCUM_REGNUM 18 | |
| 665 #define M32R_MAX_INT_REGS 16 | |
| 666 | |
| 667 #ifndef SUBTARGET_GPR_P | |
| 668 #define SUBTARGET_GPR_P(REGNO) 0 | |
| 669 #endif | |
| 670 | |
| 671 #ifndef SUBTARGET_ACCUM_P | |
| 672 #define SUBTARGET_ACCUM_P(REGNO) 0 | |
| 673 #endif | |
| 674 | |
| 675 #ifndef SUBTARGET_CARRY_P | |
| 676 #define SUBTARGET_CARRY_P(REGNO) 0 | |
| 677 #endif | |
| 678 | |
| 679 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO)) | |
| 680 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO)) | |
| 681 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO)) | |
| 682 | |
| 683 /* Eliminating the frame and arg pointers. */ | |
| 684 | |
| 685 #if 0 | |
| 686 /* C statement to store the difference between the frame pointer | |
| 687 and the stack pointer values immediately after the function prologue. | |
| 688 If `ELIMINABLE_REGS' is defined, this macro will be not be used and | |
| 689 need not be defined. */ | |
| 690 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ | |
| 691 ((VAR) = m32r_compute_frame_size (get_frame_size ())) | |
| 692 #endif | |
| 693 | |
| 694 /* If defined, this macro specifies a table of register pairs used to | |
| 695 eliminate unneeded registers that point into the stack frame. If | |
| 696 it is not defined, the only elimination attempted by the compiler | |
| 697 is to replace references to the frame pointer with references to | |
| 698 the stack pointer. | |
| 699 | |
| 700 Note that the elimination of the argument pointer with the stack | |
| 701 pointer is specified first since that is the preferred elimination. */ | |
| 702 | |
| 703 #define ELIMINABLE_REGS \ | |
| 704 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
| 705 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
| 706 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }} | |
| 707 | |
| 708 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It | |
| 709 specifies the initial difference between the specified pair of | |
| 710 registers. This macro must be defined if `ELIMINABLE_REGS' is | |
| 711 defined. */ | |
| 712 | |
| 713 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
| 714 do \ | |
| 715 { \ | |
| 716 int size = m32r_compute_frame_size (get_frame_size ()); \ | |
| 717 \ | |
| 718 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
| 719 (OFFSET) = 0; \ | |
| 720 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ | |
| 721 (OFFSET) = size - crtl->args.pretend_args_size; \ | |
| 722 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
| 723 (OFFSET) = size - crtl->args.pretend_args_size; \ | |
| 724 else \ | |
| 725 gcc_unreachable (); \ | |
| 726 } \ | |
| 727 while (0) | |
| 728 | |
| 729 /* Function argument passing. */ | |
| 730 | |
| 731 /* If defined, the maximum amount of space required for outgoing | |
| 732 arguments will be computed and placed into the variable | |
| 733 `crtl->outgoing_args_size'. No space will be pushed | |
| 734 onto the stack for each call; instead, the function prologue should | |
| 735 increase the stack frame size by this amount. */ | |
| 736 #define ACCUMULATE_OUTGOING_ARGS 1 | |
| 737 | |
| 738 /* Define a data type for recording info about an argument list | |
| 739 during the scan of that argument list. This data type should | |
| 740 hold all necessary information about the function itself | |
| 741 and about the args processed so far, enough to enable macros | |
| 742 such as FUNCTION_ARG to determine where the next arg should go. */ | |
| 743 #define CUMULATIVE_ARGS int | |
| 744 | |
| 745 /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
| 746 for a call to a function whose data type is FNTYPE. | |
| 747 For a library call, FNTYPE is 0. */ | |
| 748 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ | |
| 749 ((CUM) = 0) | |
| 750 | |
| 751 /* The number of registers used for parameter passing. Local to this file. */ | |
| 752 #define M32R_MAX_PARM_REGS 4 | |
| 753 | |
| 754 /* 1 if N is a possible register number for function argument passing. */ | |
| 755 #define FUNCTION_ARG_REGNO_P(N) \ | |
| 756 ((unsigned) (N) < M32R_MAX_PARM_REGS) | |
| 757 | |
| 758 | |
| 759 /* Function results. */ | |
| 760 | |
| 761 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */ | |
| 762 #define DEFAULT_PCC_STRUCT_RETURN 0 | |
| 763 | |
| 764 /* Function entry and exit. */ | |
| 765 | |
| 766 /* Initialize data used by insn expanders. This is called from | |
| 767 init_emit, once for each function, before code is generated. */ | |
| 768 #define INIT_EXPANDERS m32r_init_expanders () | |
| 769 | |
| 770 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
| 771 the stack pointer does not matter. The value is tested only in | |
| 772 functions that have frame pointers. | |
| 773 No definition is equivalent to always zero. */ | |
| 774 #define EXIT_IGNORE_STACK 1 | |
| 775 | |
| 776 /* Output assembler code to FILE to increment profiler label # LABELNO | |
| 777 for profiling a function entry. */ | |
| 778 #undef FUNCTION_PROFILER | |
| 779 #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
| 780 do \ | |
| 781 { \ | |
| 782 if (flag_pic) \ | |
| 783 { \ | |
| 784 fprintf (FILE, "\tld24 r14,#mcount\n"); \ | |
| 785 fprintf (FILE, "\tadd r14,r12\n"); \ | |
| 786 fprintf (FILE, "\tld r14,@r14\n"); \ | |
| 787 fprintf (FILE, "\tjl r14\n"); \ | |
| 788 } \ | |
| 789 else \ | |
| 790 { \ | |
| 791 if (TARGET_ADDR24) \ | |
| 792 fprintf (FILE, "\tbl mcount\n"); \ | |
| 793 else \ | |
| 794 { \ | |
| 795 fprintf (FILE, "\tseth r14,#high(mcount)\n"); \ | |
| 796 fprintf (FILE, "\tor3 r14,r14,#low(mcount)\n"); \ | |
| 797 fprintf (FILE, "\tjl r14\n"); \ | |
| 798 } \ | |
| 799 } \ | |
| 800 fprintf (FILE, "\taddi sp,#4\n"); \ | |
| 801 } \ | |
| 802 while (0) | |
| 803 | |
| 804 /* Trampolines. */ | |
| 805 | |
| 806 /* On the M32R, the trampoline is: | |
| 807 | |
| 808 mv r7, lr -> bl L1 ; 178e 7e01 | |
| 809 L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12) | |
| 810 mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6 | |
| 811 ld r6, @r6 -> jmp r6 ; 26c6 1fc6 | |
| 812 L2: .word STATIC | |
| 813 .word FUNCTION */ | |
| 814 | |
| 815 #ifndef CACHE_FLUSH_FUNC | |
| 816 #define CACHE_FLUSH_FUNC "_flush_cache" | |
| 817 #endif | |
| 818 #ifndef CACHE_FLUSH_TRAP | |
| 819 #define CACHE_FLUSH_TRAP 12 | |
| 820 #endif | |
| 821 | |
| 822 /* Length in bytes of the trampoline for entering a nested function. */ | |
| 823 #define TRAMPOLINE_SIZE 24 | |
| 824 | |
| 825 | |
| 826 #define RETURN_ADDR_RTX(COUNT, FRAME) m32r_return_addr (COUNT) | |
| 827 | |
| 828 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) | |
| 829 | |
| 830 /* Addressing modes, and classification of registers for them. */ | |
| 831 | |
| 832 /* Maximum number of registers that can appear in a valid memory address. */ | |
| 833 #define MAX_REGS_PER_ADDRESS 1 | |
| 834 | |
| 835 /* We have post-inc load and pre-dec,pre-inc store, | |
| 836 but only for 4 byte vals. */ | |
| 837 #define HAVE_PRE_DECREMENT 1 | |
| 838 #define HAVE_PRE_INCREMENT 1 | |
| 839 #define HAVE_POST_INCREMENT 1 | |
| 840 | |
| 841 /* Recognize any constant value that is a valid address. */ | |
| 842 #define CONSTANT_ADDRESS_P(X) \ | |
| 843 ( GET_CODE (X) == LABEL_REF \ | |
| 844 || GET_CODE (X) == SYMBOL_REF \ | |
|
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|
845 || CONST_INT_P (X) \ |
| 0 | 846 || (GET_CODE (X) == CONST \ |
| 847 && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X)))) | |
| 848 | |
| 849 /* Nonzero if the constant value X is a legitimate general operand. | |
| 850 We don't allow (plus symbol large-constant) as the relocations can't | |
| 851 describe it. INTVAL > 32767 handles both 16-bit and 24-bit relocations. | |
| 852 We allow all CONST_DOUBLE's as the md file patterns will force the | |
| 853 constant to memory if they can't handle them. */ | |
| 854 | |
| 855 #define LEGITIMATE_CONSTANT_P(X) \ | |
| 856 (! (GET_CODE (X) == CONST \ | |
| 857 && GET_CODE (XEXP (X, 0)) == PLUS \ | |
| 858 && (GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF || GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF) \ | |
|
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|
859 && CONST_INT_P (XEXP (XEXP (X, 0), 1)) \ |
| 0 | 860 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767)) |
| 861 | |
| 862 /* Condition code usage. */ | |
| 863 | |
| 864 /* Return nonzero if SELECT_CC_MODE will never return MODE for a | |
| 865 floating point inequality comparison. */ | |
| 866 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/ | |
| 867 | |
| 868 /* Costs. */ | |
| 869 | |
| 870 /* The cost of a branch insn. */ | |
| 871 /* A value of 2 here causes GCC to avoid using branches in comparisons like | |
| 872 while (a < N && a). Branches aren't that expensive on the M32R so | |
| 873 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */ | |
| 874 #define BRANCH_COST(speed_p, predictable_p) ((TARGET_BRANCH_COST) ? 2 : 1) | |
| 875 | |
| 876 /* Nonzero if access to memory by bytes is slow and undesirable. | |
| 877 For RISC chips, it means that access to memory by bytes is no | |
| 878 better than access by words when possible, so grab a whole word | |
| 879 and maybe make use of that. */ | |
| 880 #define SLOW_BYTE_ACCESS 1 | |
| 881 | |
| 882 /* Define this macro if it is as good or better to call a constant | |
| 883 function address than to call an address kept in a register. */ | |
| 884 #define NO_FUNCTION_CSE | |
| 885 | |
| 886 /* Section selection. */ | |
| 887 | |
| 888 #define TEXT_SECTION_ASM_OP "\t.section .text" | |
| 889 #define DATA_SECTION_ASM_OP "\t.section .data" | |
| 890 #define BSS_SECTION_ASM_OP "\t.section .bss" | |
| 891 | |
| 892 /* Define this macro if jump tables (for tablejump insns) should be | |
| 893 output in the text section, along with the assembler instructions. | |
| 894 Otherwise, the readonly data section is used. | |
| 895 This macro is irrelevant if there is no separate readonly data section. */ | |
| 896 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) | |
| 897 | |
| 898 /* Position Independent Code. */ | |
| 899 | |
| 900 /* The register number of the register used to address a table of static | |
| 901 data addresses in memory. In some cases this register is defined by a | |
| 902 processor's ``application binary interface'' (ABI). When this macro | |
| 903 is defined, RTL is generated for this register once, as with the stack | |
| 904 pointer and frame pointer registers. If this macro is not defined, it | |
| 905 is up to the machine-dependent files to allocate such a register (if | |
| 906 necessary). */ | |
| 907 #define PIC_OFFSET_TABLE_REGNUM 12 | |
| 908 | |
| 909 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is | |
| 910 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM | |
| 911 is not defined. */ | |
| 912 /* This register is call-saved on the M32R. */ | |
| 913 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/ | |
| 914 | |
| 915 /* A C expression that is nonzero if X is a legitimate immediate | |
| 916 operand on the target machine when generating position independent code. | |
| 917 You can assume that X satisfies CONSTANT_P, so you need not | |
| 918 check this. You can also assume `flag_pic' is true, so you need not | |
| 919 check it either. You need not define this macro if all constants | |
| 920 (including SYMBOL_REF) can be immediate operands when generating | |
| 921 position independent code. */ | |
| 922 #define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X) | |
| 923 | |
| 924 /* Control the assembler format that we output. */ | |
| 925 | |
| 926 /* A C string constant describing how to begin a comment in the target | |
| 927 assembler language. The compiler assumes that the comment will | |
| 928 end at the end of the line. */ | |
| 929 #define ASM_COMMENT_START ";" | |
| 930 | |
| 931 /* Output to assembler file text saying following lines | |
| 932 may contain character constants, extra white space, comments, etc. */ | |
| 933 #define ASM_APP_ON "" | |
| 934 | |
| 935 /* Output to assembler file text saying following lines | |
| 936 no longer contain unusual constructs. */ | |
| 937 #define ASM_APP_OFF "" | |
| 938 | |
| 939 /* Globalizing directive for a label. */ | |
| 940 #define GLOBAL_ASM_OP "\t.global\t" | |
| 941 | |
| 942 /* We do not use DBX_LINES_FUNCTION_RELATIVE or | |
| 943 dbxout_stab_value_internal_label_diff here because | |
| 944 we need to use .debugsym for the line label. */ | |
| 945 | |
| 946 #define DBX_OUTPUT_SOURCE_LINE(file, line, counter) \ | |
| 947 do \ | |
| 948 { \ | |
| 949 const char * begin_label = \ | |
| 950 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); \ | |
| 951 char label[64]; \ | |
| 952 ASM_GENERATE_INTERNAL_LABEL (label, "LM", counter); \ | |
| 953 \ | |
| 954 dbxout_begin_stabn_sline (line); \ | |
| 955 assemble_name (file, label); \ | |
| 956 putc ('-', file); \ | |
| 957 assemble_name (file, begin_label); \ | |
| 958 fputs ("\n\t.debugsym ", file); \ | |
| 959 assemble_name (file, label); \ | |
| 960 putc ('\n', file); \ | |
| 961 counter += 1; \ | |
| 962 } \ | |
| 963 while (0) | |
| 964 | |
| 965 /* How to refer to registers in assembler output. | |
| 966 This sequence is indexed by compiler's hard-register-number (see above). */ | |
| 967 #ifndef SUBTARGET_REGISTER_NAMES | |
| 968 #define SUBTARGET_REGISTER_NAMES | |
| 969 #endif | |
| 970 | |
| 971 #define REGISTER_NAMES \ | |
| 972 { \ | |
| 973 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
| 974 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \ | |
| 975 "ap", "cbit", "a0" \ | |
| 976 SUBTARGET_REGISTER_NAMES \ | |
| 977 } | |
| 978 | |
| 979 /* If defined, a C initializer for an array of structures containing | |
| 980 a name and a register number. This macro defines additional names | |
| 981 for hard registers, thus allowing the `asm' option in declarations | |
| 982 to refer to registers using alternate names. */ | |
| 983 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES | |
| 984 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES | |
| 985 #endif | |
| 986 | |
| 987 #define ADDITIONAL_REGISTER_NAMES \ | |
| 988 { \ | |
| 989 /*{ "gp", GP_REGNUM },*/ \ | |
| 990 { "r13", FRAME_POINTER_REGNUM }, \ | |
| 991 { "r14", RETURN_ADDR_REGNUM }, \ | |
| 992 { "r15", STACK_POINTER_REGNUM }, \ | |
| 993 SUBTARGET_ADDITIONAL_REGISTER_NAMES \ | |
| 994 } | |
| 995 | |
| 996 /* If defined, C string expressions to be used for the `%R', `%L', | |
| 997 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These | |
| 998 are useful when a single `md' file must support multiple assembler | |
| 999 formats. In that case, the various `tm.h' files can define these | |
| 1000 macros differently. */ | |
| 1001 #define REGISTER_PREFIX "" | |
| 1002 #define LOCAL_LABEL_PREFIX ".L" | |
| 1003 #define USER_LABEL_PREFIX "" | |
| 1004 #define IMMEDIATE_PREFIX "#" | |
| 1005 | |
| 1006 /* This is how to output an element of a case-vector that is absolute. */ | |
| 1007 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
| 1008 do \ | |
| 1009 { \ | |
| 1010 char label[30]; \ | |
| 1011 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
| 1012 fprintf (FILE, "\t.word\t"); \ | |
| 1013 assemble_name (FILE, label); \ | |
| 1014 fprintf (FILE, "\n"); \ | |
| 1015 } \ | |
| 1016 while (0) | |
| 1017 | |
| 1018 /* This is how to output an element of a case-vector that is relative. */ | |
| 1019 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\ | |
| 1020 do \ | |
| 1021 { \ | |
| 1022 char label[30]; \ | |
| 1023 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
| 1024 fprintf (FILE, "\t.word\t"); \ | |
| 1025 assemble_name (FILE, label); \ | |
| 1026 fprintf (FILE, "-"); \ | |
| 1027 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \ | |
| 1028 assemble_name (FILE, label); \ | |
| 1029 fprintf (FILE, "\n"); \ | |
| 1030 } \ | |
| 1031 while (0) | |
| 1032 | |
| 1033 /* The desired alignment for the location counter at the beginning | |
| 1034 of a loop. */ | |
| 1035 /* On the M32R, align loops to 32 byte boundaries (cache line size) | |
| 1036 if -malign-loops. */ | |
| 1037 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0) | |
| 1038 | |
| 1039 /* Define this to be the maximum number of insns to move around when moving | |
| 1040 a loop test from the top of a loop to the bottom | |
| 1041 and seeing whether to duplicate it. The default is thirty. | |
| 1042 | |
| 1043 Loop unrolling currently doesn't like this optimization, so | |
| 1044 disable doing if we are unrolling loops and saving space. */ | |
| 1045 #define LOOP_TEST_THRESHOLD (optimize_size \ | |
| 1046 && !flag_unroll_loops \ | |
| 1047 && !flag_unroll_all_loops ? 2 : 30) | |
| 1048 | |
| 1049 /* This is how to output an assembler line | |
| 1050 that says to advance the location counter | |
| 1051 to a multiple of 2**LOG bytes. */ | |
| 1052 /* .balign is used to avoid confusion. */ | |
| 1053 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
| 1054 do \ | |
| 1055 { \ | |
| 1056 if ((LOG) != 0) \ | |
| 1057 fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \ | |
| 1058 } \ | |
| 1059 while (0) | |
| 1060 | |
| 1061 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a | |
| 1062 separate, explicit argument. If you define this macro, it is used in | |
| 1063 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in | |
| 1064 handling the required alignment of the variable. The alignment is | |
| 1065 specified as the number of bits. */ | |
| 1066 | |
| 1067 #define SCOMMON_ASM_OP "\t.scomm\t" | |
| 1068 | |
| 1069 #undef ASM_OUTPUT_ALIGNED_COMMON | |
| 1070 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ | |
| 1071 do \ | |
| 1072 { \ | |
| 1073 if (! TARGET_SDATA_NONE \ | |
|
67
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1074 && (SIZE) > 0 \ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1075 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \ |
| 0 | 1076 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \ |
| 1077 else \ | |
| 1078 fprintf ((FILE), "%s", COMMON_ASM_OP); \ | |
| 1079 assemble_name ((FILE), (NAME)); \ | |
| 1080 fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\ | |
| 1081 } \ | |
| 1082 while (0) | |
| 1083 | |
| 1084 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
| 1085 do \ | |
| 1086 { \ | |
| 1087 if (! TARGET_SDATA_NONE \ | |
|
67
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1088 && (SIZE) > 0 \ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1089 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \ |
| 0 | 1090 switch_to_section (get_named_section (NULL, ".sbss", 0)); \ |
| 1091 else \ | |
| 1092 switch_to_section (bss_section); \ | |
| 1093 ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \ | |
| 1094 last_assemble_variable_decl = DECL; \ | |
| 1095 ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \ | |
| 1096 ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \ | |
| 1097 } \ | |
| 1098 while (0) | |
| 1099 | |
| 1100 /* Debugging information. */ | |
| 1101 | |
| 1102 /* Generate DBX and DWARF debugging information. */ | |
| 1103 #define DBX_DEBUGGING_INFO 1 | |
| 1104 #define DWARF2_DEBUGGING_INFO 1 | |
| 1105 | |
| 1106 /* Use DWARF2 debugging info by default. */ | |
| 1107 #undef PREFERRED_DEBUGGING_TYPE | |
| 1108 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG | |
| 1109 | |
| 1110 /* Turn off splitting of long stabs. */ | |
| 1111 #define DBX_CONTIN_LENGTH 0 | |
| 1112 | |
| 1113 /* Miscellaneous. */ | |
| 1114 | |
| 1115 /* Specify the machine mode that this machine uses | |
| 1116 for the index in the tablejump instruction. */ | |
| 1117 #define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode) | |
| 1118 | |
| 1119 /* Define if operations between registers always perform the operation | |
| 1120 on the full register even if a narrower mode is specified. */ | |
| 1121 #define WORD_REGISTER_OPERATIONS | |
| 1122 | |
| 1123 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
| 1124 will either zero-extend or sign-extend. The value of this macro should | |
| 1125 be the code that says which one of the two operations is implicitly | |
| 1126 done, UNKNOWN if none. */ | |
| 1127 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
| 1128 | |
| 1129 /* Max number of bytes we can move from memory | |
| 1130 to memory in one reasonably fast instruction. */ | |
| 1131 #define MOVE_MAX 4 | |
| 1132 | |
| 1133 /* Define this to be nonzero if shift instructions ignore all but the low-order | |
| 1134 few bits. */ | |
| 1135 #define SHIFT_COUNT_TRUNCATED 1 | |
| 1136 | |
| 1137 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
| 1138 is done just by pretending it is already truncated. */ | |
| 1139 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
| 1140 | |
| 1141 /* Specify the machine mode that pointers have. | |
| 1142 After generation of rtl, the compiler makes no further distinction | |
| 1143 between pointers and any other objects of this machine mode. */ | |
| 1144 /* ??? The M32R doesn't have full 32-bit pointers, but making this PSImode has | |
| 1145 its own problems (you have to add extendpsisi2 and truncsipsi2). | |
| 1146 Try to avoid it. */ | |
| 1147 #define Pmode SImode | |
| 1148 | |
| 1149 /* A function address in a call instruction. */ | |
| 1150 #define FUNCTION_MODE SImode | |
| 1151 | |
| 1152 /* M32R function types. */ | |
| 1153 enum m32r_function_type | |
| 1154 { | |
| 1155 M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT | |
| 1156 }; | |
| 1157 | |
| 1158 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT) | |
| 1159 | |
| 1160 /* The maximum number of bytes to copy using pairs of load/store instructions. | |
| 1161 If a block is larger than this then a loop will be generated to copy | |
| 1162 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice. | |
| 1163 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte | |
| 1164 string copy in it. */ | |
| 1165 #define MAX_MOVE_BYTES 32 |